target/linux/brcm63xx/patches-2.6.27/002-add_support_for_broadcom_63xx_cpus.patch

   1 From 0713aadd2a4e543b69022aa40bdec3e1dc5bc1e5 Mon Sep 17 00:00:00 2001
   2 From: Maxime Bizon <mbizon@freebox.fr>
   3 Date: Mon, 18 Aug 2008 13:56:57 +0200
   4 Subject: [PATCH] [MIPS] BCM63XX: Add support for Broadcom 63xx CPUs.
   5
   6 Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
   7 ---
   8  arch/mips/Kconfig                                  |   16 +
   9  arch/mips/Makefile                                 |    7 +
  10  arch/mips/bcm63xx/Kconfig                          |    9 +
  11  arch/mips/bcm63xx/Makefile                         |    2 +
  12  arch/mips/bcm63xx/clk.c                            |  220 ++++++
  13  arch/mips/bcm63xx/cpu.c                            |  245 +++++++
  14  arch/mips/bcm63xx/cs.c                             |  144 ++++
  15  arch/mips/bcm63xx/early_printk.c                   |   30 +
  16  arch/mips/bcm63xx/gpio.c                           |   98 +++
  17  arch/mips/bcm63xx/irq.c                            |  253 +++++++
  18  arch/mips/bcm63xx/prom.c                           |   43 ++
  19  arch/mips/bcm63xx/setup.c                          |  108 +++
  20  arch/mips/bcm63xx/timer.c                          |  205 ++++++
  21  include/asm-mips/fixmap.h                          |    4 +
  22  include/asm-mips/mach-bcm63xx/bcm63xx_clk.h        |   11 +
  23  include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h        |  314 +++++++++
  24  include/asm-mips/mach-bcm63xx/bcm63xx_cs.h         |   10 +
  25  include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h       |   14 +
  26  include/asm-mips/mach-bcm63xx/bcm63xx_io.h         |   93 +++
  27  include/asm-mips/mach-bcm63xx/bcm63xx_irq.h        |   15 +
  28  include/asm-mips/mach-bcm63xx/bcm63xx_regs.h       |  728 ++++++++++++++++++++
  29  include/asm-mips/mach-bcm63xx/bcm63xx_timer.h      |   11 +
  30  .../asm-mips/mach-bcm63xx/cpu-feature-overrides.h  |   51 ++
  31  include/asm-mips/mach-bcm63xx/gpio.h               |   52 ++
  32  include/asm-mips/mach-bcm63xx/war.h                |   25 +
  33  25 files changed, 2708 insertions(+), 0 deletions(-)
  34  create mode 100644 arch/mips/bcm63xx/Kconfig
  35  create mode 100644 arch/mips/bcm63xx/Makefile
  36  create mode 100644 arch/mips/bcm63xx/clk.c
  37  create mode 100644 arch/mips/bcm63xx/cpu.c
  38  create mode 100644 arch/mips/bcm63xx/cs.c
  39  create mode 100644 arch/mips/bcm63xx/early_printk.c
  40  create mode 100644 arch/mips/bcm63xx/gpio.c
  41  create mode 100644 arch/mips/bcm63xx/irq.c
  42  create mode 100644 arch/mips/bcm63xx/prom.c
  43  create mode 100644 arch/mips/bcm63xx/setup.c
  44  create mode 100644 arch/mips/bcm63xx/timer.c
  45  create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_clk.h
  46  create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
  47  create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_cs.h
  48  create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h
  49  create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_io.h
  50  create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_irq.h
  51  create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
  52  create mode 100644 include/asm-mips/mach-bcm63xx/bcm63xx_timer.h
  53  create mode 100644 include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h
  54  create mode 100644 include/asm-mips/mach-bcm63xx/gpio.h
  55  create mode 100644 include/asm-mips/mach-bcm63xx/war.h
  56
  57 --- a/arch/mips/Kconfig
  58 +++ b/arch/mips/Kconfig
  59 @@ -59,6 +59,21 @@ config BCM47XX
  60         help
  61          Support for BCM47XX based boards
  62
  63 +config BCM63XX
  64 +       bool "Broadcom 63xx based boards"
  65 +       select CEVT_R4K
  66 +       select CSRC_R4K
  67 +       select DMA_NONCOHERENT
  68 +       select IRQ_CPU
  69 +       select SYS_HAS_CPU_MIPS32_R1
  70 +       select SYS_SUPPORTS_32BIT_KERNEL
  71 +       select SYS_SUPPORTS_BIG_ENDIAN
  72 +       select SYS_HAS_EARLY_PRINTK
  73 +       select SWAP_IO_SPACE
  74 +       select GENERIC_GPIO
  75 +       help
  76 +        Support for BCM63XX based boards
  77 +
  78  config MIPS_COBALT
  79         bool "Cobalt Server"
  80         select CEVT_R4K
  81 @@ -600,6 +615,7 @@ endchoice
  82
  83  source "arch/mips/au1000/Kconfig"
  84  source "arch/mips/basler/excite/Kconfig"
  85 +source "arch/mips/bcm63xx/Kconfig"
  86  source "arch/mips/jazz/Kconfig"
  87  source "arch/mips/lasat/Kconfig"
  88  source "arch/mips/pmc-sierra/Kconfig"
  89 --- a/arch/mips/Makefile
  90 +++ b/arch/mips/Makefile
  91 @@ -533,6 +533,13 @@ cflags-$(CONFIG_BCM47XX)   += -Iinclude/as
  92  load-$(CONFIG_BCM47XX)         := 0xffffffff80001000
  93
  94  #
  95 +# Broadcom BCM63XX boards
  96 +#
  97 +core-$(CONFIG_BCM63XX)         += arch/mips/bcm63xx/
  98 +cflags-$(CONFIG_BCM63XX)       += -Iinclude/asm-mips/mach-bcm63xx/
  99 +load-$(CONFIG_BCM63XX)         := 0xffffffff80010000
 100 +
 101 +#
 102  # SNI RM
 103  #
 104  core-$(CONFIG_SNI_RM)          += arch/mips/sni/
 105 --- /dev/null
 106 +++ b/arch/mips/bcm63xx/Kconfig
 107 @@ -0,0 +1,9 @@
 108 +menu "CPU support"
 109 +       depends on BCM63XX
 110 +
 111 +config BCM63XX_CPU_6348
 112 +       bool "support 6348 CPU"
 113 +
 114 +config BCM63XX_CPU_6358
 115 +       bool "support 6358 CPU"
 116 +endmenu
 117 --- /dev/null
 118 +++ b/arch/mips/bcm63xx/Makefile
 119 @@ -0,0 +1,2 @@
 120 +obj-y          += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o
 121 +obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
 122 --- /dev/null
 123 +++ b/arch/mips/bcm63xx/clk.c
 124 @@ -0,0 +1,220 @@
 125 +/*
 126 + * This file is subject to the terms and conditions of the GNU General Public
 127 + * License.  See the file "COPYING" in the main directory of this archive
 128 + * for more details.
 129 + *
 130 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 131 + */
 132 +
 133 +#include <linux/module.h>
 134 +#include <linux/mutex.h>
 135 +#include <linux/err.h>
 136 +#include <linux/clk.h>
 137 +#include <bcm63xx_cpu.h>
 138 +#include <bcm63xx_io.h>
 139 +#include <bcm63xx_regs.h>
 140 +#include <bcm63xx_clk.h>
 141 +
 142 +DEFINE_MUTEX(clocks_mutex);
 143 +
 144 +
 145 +static void clk_enable_unlocked(struct clk *clk)
 146 +{
 147 +       if (clk->set && (clk->usage++) == 0)
 148 +               clk->set(clk, 1);
 149 +}
 150 +
 151 +static void clk_disable_unlocked(struct clk *clk)
 152 +{
 153 +       if (clk->set && (--clk->usage) == 0)
 154 +               clk->set(clk, 0);
 155 +}
 156 +
 157 +static void bcm_hwclock_set(u32 mask, int enable)
 158 +{
 159 +       u32 reg;
 160 +
 161 +       reg = bcm_perf_readl(PERF_CKCTL_REG);
 162 +       if (enable)
 163 +               reg |= mask;
 164 +       else
 165 +               reg &= ~mask;
 166 +       bcm_perf_writel(reg, PERF_CKCTL_REG);
 167 +}
 168 +
 169 +/*
 170 + * Ethernet MAC "misc" clock: dma clocks and main clock on 6348
 171 + */
 172 +static void enet_misc_set(struct clk *clk, int enable)
 173 +{
 174 +       u32 mask;
 175 +
 176 +       if (BCMCPU_IS_6348())
 177 +               mask = CKCTL_6348_ENET_EN;
 178 +       else
 179 +               /* BCMCPU_IS_6358 */
 180 +               mask = CKCTL_6358_EMUSB_EN;
 181 +       bcm_hwclock_set(mask, enable);
 182 +}
 183 +
 184 +static struct clk clk_enet_misc = {
 185 +       .set    = enet_misc_set,
 186 +};
 187 +
 188 +/*
 189 + * Ethernet MAC clocks: only revelant on 6358, silently enable misc
 190 + * clocks
 191 + */
 192 +static void enetx_set(struct clk *clk, int enable)
 193 +{
 194 +       if (enable)
 195 +               clk_enable_unlocked(&clk_enet_misc);
 196 +       else
 197 +               clk_disable_unlocked(&clk_enet_misc);
 198 +
 199 +       if (BCMCPU_IS_6358()) {
 200 +               u32 mask;
 201 +
 202 +               if (clk->id == 0)
 203 +                       mask = CKCTL_6358_ENET0_EN;
 204 +               else
 205 +                       mask = CKCTL_6358_ENET1_EN;
 206 +               bcm_hwclock_set(mask, enable);
 207 +       }
 208 +}
 209 +
 210 +static struct clk clk_enet0 = {
 211 +       .id     = 0,
 212 +       .set    = enetx_set,
 213 +};
 214 +
 215 +static struct clk clk_enet1 = {
 216 +       .id     = 1,
 217 +       .set    = enetx_set,
 218 +};
 219 +
 220 +/*
 221 + * Ethernet PHY clock
 222 + */
 223 +static void ephy_set(struct clk *clk, int enable)
 224 +{
 225 +       if (!BCMCPU_IS_6358())
 226 +               return;
 227 +       bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
 228 +}
 229 +
 230 +
 231 +static struct clk clk_ephy = {
 232 +       .set    = ephy_set,
 233 +};
 234 +
 235 +/*
 236 + * PCM clock
 237 + */
 238 +static void pcm_set(struct clk *clk, int enable)
 239 +{
 240 +       if (!BCMCPU_IS_6358())
 241 +               return;
 242 +       bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
 243 +}
 244 +
 245 +static struct clk clk_pcm = {
 246 +       .set    = pcm_set,
 247 +};
 248 +
 249 +/*
 250 + * USB host clock
 251 + */
 252 +static void usbh_set(struct clk *clk, int enable)
 253 +{
 254 +       if (!BCMCPU_IS_6348())
 255 +               return;
 256 +       bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
 257 +}
 258 +
 259 +static struct clk clk_usbh = {
 260 +       .set    = usbh_set,
 261 +};
 262 +
 263 +/*
 264 + * SPI clock
 265 + */
 266 +static void spi_set(struct clk *clk, int enable)
 267 +{
 268 +       u32 mask;
 269 +
 270 +       if (BCMCPU_IS_6348())
 271 +               mask = CKCTL_6348_SPI_EN;
 272 +       else
 273 +               /* BCMCPU_IS_6358 */
 274 +               mask = CKCTL_6358_SPI_EN;
 275 +       bcm_hwclock_set(mask, enable);
 276 +}
 277 +
 278 +static struct clk clk_spi = {
 279 +       .set    = spi_set,
 280 +};
 281 +
 282 +/*
 283 + * Internal peripheral clock
 284 + */
 285 +static struct clk clk_periph = {
 286 +       .rate   = (50 * 1000 * 1000),
 287 +};
 288 +
 289 +
 290 +/*
 291 + * Linux clock API implementation
 292 + */
 293 +int clk_enable(struct clk *clk)
 294 +{
 295 +       mutex_lock(&clocks_mutex);
 296 +       clk_enable_unlocked(clk);
 297 +       mutex_unlock(&clocks_mutex);
 298 +       return 0;
 299 +}
 300 +
 301 +EXPORT_SYMBOL(clk_enable);
 302 +
 303 +void clk_disable(struct clk *clk)
 304 +{
 305 +       mutex_lock(&clocks_mutex);
 306 +       clk_disable_unlocked(clk);
 307 +       mutex_unlock(&clocks_mutex);
 308 +}
 309 +
 310 +EXPORT_SYMBOL(clk_disable);
 311 +
 312 +unsigned long clk_get_rate(struct clk *clk)
 313 +{
 314 +       return clk->rate;
 315 +}
 316 +
 317 +EXPORT_SYMBOL(clk_get_rate);
 318 +
 319 +struct clk *clk_get(struct device *dev, const char *id)
 320 +{
 321 +       if (!strcmp(id, "enet0"))
 322 +               return &clk_enet0;
 323 +       if (!strcmp(id, "enet1"))
 324 +               return &clk_enet1;
 325 +       if (!strcmp(id, "ephy"))
 326 +               return &clk_ephy;
 327 +       if (!strcmp(id, "usbh"))
 328 +               return &clk_usbh;
 329 +       if (!strcmp(id, "spi"))
 330 +               return &clk_spi;
 331 +       if (!strcmp(id, "periph"))
 332 +               return &clk_periph;
 333 +       if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
 334 +               return &clk_pcm;
 335 +       return ERR_PTR(-ENOENT);
 336 +}
 337 +
 338 +EXPORT_SYMBOL(clk_get);
 339 +
 340 +void clk_put(struct clk *clk)
 341 +{
 342 +}
 343 +
 344 +EXPORT_SYMBOL(clk_put);
 345 --- /dev/null
 346 +++ b/arch/mips/bcm63xx/cpu.c
 347 @@ -0,0 +1,245 @@
 348 +/*
 349 + * This file is subject to the terms and conditions of the GNU General Public
 350 + * License.  See the file "COPYING" in the main directory of this archive
 351 + * for more details.
 352 + *
 353 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 354 + */
 355 +
 356 +#include <linux/kernel.h>
 357 +#include <linux/module.h>
 358 +#include <linux/cpu.h>
 359 +#include <bcm63xx_cpu.h>
 360 +#include <bcm63xx_regs.h>
 361 +#include <bcm63xx_io.h>
 362 +#include <bcm63xx_irq.h>
 363 +
 364 +const unsigned long *bcm63xx_regs_base;
 365 +EXPORT_SYMBOL(bcm63xx_regs_base);
 366 +
 367 +const int *bcm63xx_irqs;
 368 +EXPORT_SYMBOL(bcm63xx_irqs);
 369 +
 370 +static u16 bcm63xx_cpu_id;
 371 +static u16 bcm63xx_cpu_rev;
 372 +static unsigned int bcm63xx_cpu_freq;
 373 +static unsigned int bcm63xx_memory_size;
 374 +
 375 +/*
 376 + * 6348 register sets and irqs
 377 + */
 378 +static const unsigned long bcm96348_regs_base[] = {
 379 +       [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
 380 +       [RSET_PERF]             = BCM_6348_PERF_BASE,
 381 +       [RSET_TIMER]            = BCM_6348_TIMER_BASE,
 382 +       [RSET_WDT]              = BCM_6348_WDT_BASE,
 383 +       [RSET_UART0]            = BCM_6348_UART0_BASE,
 384 +       [RSET_GPIO]             = BCM_6348_GPIO_BASE,
 385 +       [RSET_SPI]              = BCM_6348_SPI_BASE,
 386 +       [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
 387 +       [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
 388 +       [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
 389 +       [RSET_MPI]              = BCM_6348_MPI_BASE,
 390 +       [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
 391 +       [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
 392 +       [RSET_DSL]              = BCM_6348_DSL_BASE,
 393 +       [RSET_ENET0]            = BCM_6348_ENET0_BASE,
 394 +       [RSET_ENET1]            = BCM_6348_ENET1_BASE,
 395 +       [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
 396 +       [RSET_MEMC]             = BCM_6348_MEMC_BASE,
 397 +       [RSET_DDR]              = BCM_6348_DDR_BASE,
 398 +};
 399 +
 400 +static const int bcm96348_irqs[] = {
 401 +       [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
 402 +       [IRQ_UART0]             = BCM_6348_UART0_IRQ,
 403 +       [IRQ_DSL]               = BCM_6348_DSL_IRQ,
 404 +       [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
 405 +       [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
 406 +       [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
 407 +       [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
 408 +       [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
 409 +       [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
 410 +       [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
 411 +       [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
 412 +       [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
 413 +       [IRQ_PCI]               = BCM_6348_PCI_IRQ,
 414 +};
 415 +
 416 +/*
 417 + * 6358 register sets and irqs
 418 + */
 419 +static const unsigned long bcm96358_regs_base[] = {
 420 +       [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
 421 +       [RSET_PERF]             = BCM_6358_PERF_BASE,
 422 +       [RSET_TIMER]            = BCM_6358_TIMER_BASE,
 423 +       [RSET_WDT]              = BCM_6358_WDT_BASE,
 424 +       [RSET_UART0]            = BCM_6358_UART0_BASE,
 425 +       [RSET_GPIO]             = BCM_6358_GPIO_BASE,
 426 +       [RSET_SPI]              = BCM_6358_SPI_BASE,
 427 +       [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
 428 +       [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
 429 +       [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
 430 +       [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
 431 +       [RSET_MPI]              = BCM_6358_MPI_BASE,
 432 +       [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
 433 +       [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
 434 +       [RSET_DSL]              = BCM_6358_DSL_BASE,
 435 +       [RSET_ENET0]            = BCM_6358_ENET0_BASE,
 436 +       [RSET_ENET1]            = BCM_6358_ENET1_BASE,
 437 +       [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
 438 +       [RSET_MEMC]             = BCM_6358_MEMC_BASE,
 439 +       [RSET_DDR]              = BCM_6358_DDR_BASE,
 440 +};
 441 +
 442 +static const int bcm96358_irqs[] = {
 443 +       [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
 444 +       [IRQ_UART0]             = BCM_6358_UART0_IRQ,
 445 +       [IRQ_DSL]               = BCM_6358_DSL_IRQ,
 446 +       [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
 447 +       [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
 448 +       [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
 449 +       [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
 450 +       [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
 451 +       [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
 452 +       [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
 453 +       [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
 454 +       [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
 455 +       [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
 456 +       [IRQ_PCI]               = BCM_6358_PCI_IRQ,
 457 +};
 458 +
 459 +u16 __bcm63xx_get_cpu_id(void)
 460 +{
 461 +       return bcm63xx_cpu_id;
 462 +}
 463 +
 464 +EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
 465 +
 466 +u16 bcm63xx_get_cpu_rev(void)
 467 +{
 468 +       return bcm63xx_cpu_rev;
 469 +}
 470 +
 471 +EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
 472 +
 473 +unsigned int bcm63xx_get_cpu_freq(void)
 474 +{
 475 +       return bcm63xx_cpu_freq;
 476 +}
 477 +
 478 +unsigned int bcm63xx_get_memory_size(void)
 479 +{
 480 +       return bcm63xx_memory_size;
 481 +}
 482 +
 483 +static unsigned int detect_cpu_clock(void)
 484 +{
 485 +       unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 486 +
 487 +       /*
 488 +        * frequency depends on PLL configuration:
 489 +        */
 490 +       if (BCMCPU_IS_6348()) {
 491 +               /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
 492 +               tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
 493 +               n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
 494 +               n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
 495 +               m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
 496 +               n1 += 1;
 497 +               n2 += 2;
 498 +               m1 += 1;
 499 +       }
 500 +
 501 +       if (BCMCPU_IS_6358()) {
 502 +               /* 16MHz * N1 * N2 / M1_CPU */
 503 +               tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
 504 +               n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
 505 +               n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
 506 +               m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
 507 +       }
 508 +
 509 +       return (16 * 1000000 * n1 * n2) / m1;
 510 +}
 511 +
 512 +/*
 513 + * attempt to detect the amount of memory installed
 514 + */
 515 +static unsigned int detect_memory_size(void)
 516 +{
 517 +       unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 518 +       u32 val;
 519 +
 520 +       if (BCMCPU_IS_6348()) {
 521 +               val = bcm_sdram_readl(SDRAM_CFG_REG);
 522 +               rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
 523 +               cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
 524 +               is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
 525 +               banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 526 +       }
 527 +
 528 +       if (BCMCPU_IS_6358()) {
 529 +               val = bcm_memc_readl(MEMC_CFG_REG);
 530 +               rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 531 +               cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
 532 +               is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 533 +               banks = 2;
 534 +       }
 535 +
 536 +       /* 0 => 11 address bits ... 2 => 13 address bits */
 537 +       rows += 11;
 538 +
 539 +       /* 0 => 8 address bits ... 2 => 10 address bits */
 540 +       cols += 8;
 541 +
 542 +       return 1 << (cols + rows + (is_32bits + 1) + banks);
 543 +}
 544 +
 545 +void __init bcm63xx_cpu_init(void)
 546 +{
 547 +       unsigned int tmp, expected_cpu_id;
 548 +       struct cpuinfo_mips *c = &current_cpu_data;
 549 +
 550 +       /* soc registers location depends on cpu type */
 551 +       expected_cpu_id = 0;
 552 +
 553 +       switch (c->cputype) {
 554 +       case CPU_BCM6348:
 555 +               expected_cpu_id = BCM6348_CPU_ID;
 556 +               bcm63xx_regs_base = bcm96348_regs_base;
 557 +               bcm63xx_irqs = bcm96348_irqs;
 558 +               break;
 559 +       case CPU_BCM6358:
 560 +               expected_cpu_id = BCM6358_CPU_ID;
 561 +               bcm63xx_regs_base = bcm96358_regs_base;
 562 +               bcm63xx_irqs = bcm96358_irqs;
 563 +               break;
 564 +       }
 565 +
 566 +       /* really early to panic, but delaying panic would not help
 567 +        * since we will never get any working console */
 568 +       if (!expected_cpu_id)
 569 +               panic("unsupported Broadcom CPU");
 570 +
 571 +       /*
 572 +        * bcm63xx_regs_base is set, we can access soc registers
 573 +        */
 574 +
 575 +       /* double check CPU type */
 576 +       tmp = bcm_perf_readl(PERF_REV_REG);
 577 +       bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
 578 +       bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 579 +
 580 +       if (bcm63xx_cpu_id != expected_cpu_id)
 581 +               panic("bcm63xx CPU id mismatch");
 582 +
 583 +       bcm63xx_cpu_freq = detect_cpu_clock();
 584 +       bcm63xx_memory_size = detect_memory_size();
 585 +
 586 +       printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
 587 +              bcm63xx_cpu_id, bcm63xx_cpu_rev);
 588 +       printk(KERN_INFO "CPU frequency is %u MHz\n",
 589 +              bcm63xx_cpu_freq);
 590 +       printk(KERN_INFO "%uMB of RAM installed\n",
 591 +              bcm63xx_memory_size >> 20);
 592 +}
 593 --- /dev/null
 594 +++ b/arch/mips/bcm63xx/cs.c
 595 @@ -0,0 +1,144 @@
 596 +/*
 597 + * This file is subject to the terms and conditions of the GNU General Public
 598 + * License.  See the file "COPYING" in the main directory of this archive
 599 + * for more details.
 600 + *
 601 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 602 + */
 603 +
 604 +#include <linux/kernel.h>
 605 +#include <linux/module.h>
 606 +#include <linux/spinlock.h>
 607 +#include <linux/log2.h>
 608 +#include <bcm63xx_cpu.h>
 609 +#include <bcm63xx_io.h>
 610 +#include <bcm63xx_regs.h>
 611 +#include <bcm63xx_cs.h>
 612 +
 613 +static DEFINE_SPINLOCK(bcm63xx_cs_lock);
 614 +
 615 +/*
 616 + * check if given chip select exists
 617 + */
 618 +static int is_valid_cs(unsigned int cs)
 619 +{
 620 +       if (cs > 6)
 621 +               return 0;
 622 +       return 1;
 623 +}
 624 +
 625 +/*
 626 + * Configure chipselect base address and size (bytes).
 627 + * Size must be a power of two between 8k and 256M.
 628 + */
 629 +int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size)
 630 +{
 631 +       unsigned long flags;
 632 +       u32 val;
 633 +
 634 +       if (!is_valid_cs(cs))
 635 +               return -EINVAL;
 636 +
 637 +       /* sanity check on size */
 638 +       if (size != roundup_pow_of_two(size))
 639 +               return -EINVAL;
 640 +
 641 +       if (size < 8 * 1024 || size > 256 * 1024 * 1024)
 642 +               return -EINVAL;
 643 +
 644 +       val = (base & MPI_CSBASE_BASE_MASK);
 645 +       /* 8k => 0 - 256M => 15 */
 646 +       val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT;
 647 +
 648 +       spin_lock_irqsave(&bcm63xx_cs_lock, flags);
 649 +       bcm_mpi_writel(val, MPI_CSBASE_REG(cs));
 650 +       spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
 651 +
 652 +       return 0;
 653 +}
 654 +
 655 +EXPORT_SYMBOL(bcm63xx_set_cs_base);
 656 +
 657 +/*
 658 + * configure chipselect timing (ns)
 659 + */
 660 +int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
 661 +                          unsigned int setup, unsigned int hold)
 662 +{
 663 +       unsigned long flags;
 664 +       u32 val;
 665 +
 666 +       if (!is_valid_cs(cs))
 667 +               return -EINVAL;
 668 +
 669 +       spin_lock_irqsave(&bcm63xx_cs_lock, flags);
 670 +       val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
 671 +       val &= ~(MPI_CSCTL_WAIT_MASK);
 672 +       val &= ~(MPI_CSCTL_SETUP_MASK);
 673 +       val &= ~(MPI_CSCTL_HOLD_MASK);
 674 +       val |= wait << MPI_CSCTL_WAIT_SHIFT;
 675 +       val |= setup << MPI_CSCTL_SETUP_SHIFT;
 676 +       val |= hold << MPI_CSCTL_HOLD_SHIFT;
 677 +       bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
 678 +       spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
 679 +
 680 +       return 0;
 681 +}
 682 +
 683 +EXPORT_SYMBOL(bcm63xx_set_cs_timing);
 684 +
 685 +/*
 686 + * configure other chipselect parameter (data bus size, ...)
 687 + */
 688 +int bcm63xx_set_cs_param(unsigned int cs, u32 params)
 689 +{
 690 +       unsigned long flags;
 691 +       u32 val;
 692 +
 693 +       if (!is_valid_cs(cs))
 694 +               return -EINVAL;
 695 +
 696 +       /* none of this fields apply to pcmcia */
 697 +       if (cs == MPI_CS_PCMCIA_COMMON ||
 698 +           cs == MPI_CS_PCMCIA_ATTR ||
 699 +           cs == MPI_CS_PCMCIA_IO)
 700 +               return -EINVAL;
 701 +
 702 +       spin_lock_irqsave(&bcm63xx_cs_lock, flags);
 703 +       val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
 704 +       val &= ~(MPI_CSCTL_DATA16_MASK);
 705 +       val &= ~(MPI_CSCTL_SYNCMODE_MASK);
 706 +       val &= ~(MPI_CSCTL_TSIZE_MASK);
 707 +       val &= ~(MPI_CSCTL_ENDIANSWAP_MASK);
 708 +       val |= params;
 709 +       bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
 710 +       spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
 711 +
 712 +       return 0;
 713 +}
 714 +
 715 +EXPORT_SYMBOL(bcm63xx_set_cs_param);
 716 +
 717 +/*
 718 + * set cs status (enable/disable)
 719 + */
 720 +int bcm63xx_set_cs_status(unsigned int cs, int enable)
 721 +{
 722 +       unsigned long flags;
 723 +       u32 val;
 724 +
 725 +       if (!is_valid_cs(cs))
 726 +               return -EINVAL;
 727 +
 728 +       spin_lock_irqsave(&bcm63xx_cs_lock, flags);
 729 +       val = bcm_mpi_readl(MPI_CSCTL_REG(cs));
 730 +       if (enable)
 731 +               val |= MPI_CSCTL_ENABLE_MASK;
 732 +       else
 733 +               val &= ~MPI_CSCTL_ENABLE_MASK;
 734 +       bcm_mpi_writel(val, MPI_CSCTL_REG(cs));
 735 +       spin_unlock_irqrestore(&bcm63xx_cs_lock, flags);
 736 +       return 0;
 737 +}
 738 +
 739 +EXPORT_SYMBOL(bcm63xx_set_cs_status);
 740 --- /dev/null
 741 +++ b/arch/mips/bcm63xx/early_printk.c
 742 @@ -0,0 +1,30 @@
 743 +/*
 744 + * This file is subject to the terms and conditions of the GNU General Public
 745 + * License.  See the file "COPYING" in the main directory of this archive
 746 + * for more details.
 747 + *
 748 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 749 + */
 750 +
 751 +#include <linux/init.h>
 752 +#include <bcm63xx_io.h>
 753 +#include <bcm63xx_regs.h>
 754 +
 755 +static void __init wait_xfered(void)
 756 +{
 757 +       unsigned int val;
 758 +
 759 +       /* wait for any previous char to be transmitted */
 760 +       do {
 761 +               val = bcm_uart0_readl(UART_IR_REG);
 762 +               if (val & UART_IR_STAT(UART_IR_TXEMPTY))
 763 +                       break;
 764 +       } while (1);
 765 +}
 766 +
 767 +void __init prom_putchar(char c)
 768 +{
 769 +       wait_xfered();
 770 +       bcm_uart0_writel(c, UART_FIFO_REG);
 771 +       wait_xfered();
 772 +}
 773 --- /dev/null
 774 +++ b/arch/mips/bcm63xx/gpio.c
 775 @@ -0,0 +1,98 @@
 776 +/*
 777 + * This file is subject to the terms and conditions of the GNU General Public
 778 + * License.  See the file "COPYING" in the main directory of this archive
 779 + * for more details.
 780 + *
 781 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 782 + */
 783 +
 784 +#include <linux/kernel.h>
 785 +#include <linux/module.h>
 786 +#include <linux/spinlock.h>
 787 +#include <bcm63xx_cpu.h>
 788 +#include <bcm63xx_gpio.h>
 789 +#include <bcm63xx_io.h>
 790 +#include <bcm63xx_regs.h>
 791 +
 792 +static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
 793 +
 794 +void bcm63xx_gpio_set_dataout(int gpio, int val)
 795 +{
 796 +       u32 reg;
 797 +       u32 mask;
 798 +       u32 tmp;
 799 +       unsigned long flags;
 800 +
 801 +       if (gpio >= BCM63XX_GPIO_COUNT)
 802 +               BUG();
 803 +
 804 +       if (gpio < 32) {
 805 +               reg = GPIO_DATA_LO_REG;
 806 +               mask = 1 << gpio;
 807 +       } else {
 808 +               reg = GPIO_DATA_HI_REG;
 809 +               mask = 1 << (gpio - 32);
 810 +       }
 811 +
 812 +       spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
 813 +       tmp = bcm_gpio_readl(reg);
 814 +       if (val)
 815 +               tmp |= mask;
 816 +       else
 817 +               tmp &= ~mask;
 818 +       bcm_gpio_writel(tmp, reg);
 819 +       spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
 820 +}
 821 +
 822 +EXPORT_SYMBOL(bcm63xx_gpio_set_dataout);
 823 +
 824 +int bcm63xx_gpio_get_datain(int gpio)
 825 +{
 826 +       u32 reg;
 827 +       u32 mask;
 828 +
 829 +       if (gpio >= BCM63XX_GPIO_COUNT)
 830 +               BUG();
 831 +
 832 +       if (gpio < 32) {
 833 +               reg = GPIO_DATA_LO_REG;
 834 +               mask = 1 << gpio;
 835 +       } else {
 836 +               reg = GPIO_DATA_HI_REG;
 837 +               mask = 1 << (gpio - 32);
 838 +       }
 839 +
 840 +       return !!(bcm_gpio_readl(reg) & mask);
 841 +}
 842 +
 843 +EXPORT_SYMBOL(bcm63xx_gpio_get_datain);
 844 +
 845 +void bcm63xx_gpio_set_direction(int gpio, int dir)
 846 +{
 847 +       u32 reg;
 848 +       u32 mask;
 849 +       u32 tmp;
 850 +       unsigned long flags;
 851 +
 852 +       if (gpio >= BCM63XX_GPIO_COUNT)
 853 +               BUG();
 854 +
 855 +       if (gpio < 32) {
 856 +               reg = GPIO_CTL_LO_REG;
 857 +               mask = 1 << gpio;
 858 +       } else {
 859 +               reg = GPIO_CTL_HI_REG;
 860 +               mask = 1 << (gpio - 32);
 861 +       }
 862 +
 863 +       spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
 864 +       tmp = bcm_gpio_readl(reg);
 865 +       if (dir == GPIO_DIR_IN)
 866 +               tmp &= ~mask;
 867 +       else
 868 +               tmp |= mask;
 869 +       bcm_gpio_writel(tmp, reg);
 870 +       spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
 871 +}
 872 +
 873 +EXPORT_SYMBOL(bcm63xx_gpio_set_direction);
 874 --- /dev/null
 875 +++ b/arch/mips/bcm63xx/irq.c
 876 @@ -0,0 +1,253 @@
 877 +/*
 878 + * This file is subject to the terms and conditions of the GNU General Public
 879 + * License.  See the file "COPYING" in the main directory of this archive
 880 + * for more details.
 881 + *
 882 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 883 + * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
 884 + */
 885 +
 886 +#include <linux/kernel.h>
 887 +#include <linux/init.h>
 888 +#include <linux/interrupt.h>
 889 +#include <linux/module.h>
 890 +#include <asm/irq_cpu.h>
 891 +#include <asm/mipsregs.h>
 892 +#include <bcm63xx_cpu.h>
 893 +#include <bcm63xx_regs.h>
 894 +#include <bcm63xx_io.h>
 895 +#include <bcm63xx_irq.h>
 896 +
 897 +/*
 898 + * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
 899 + * prioritize any interrupt relatively to another. the static counter
 900 + * will resume the loop where it ended the last time we left this
 901 + * function.
 902 + */
 903 +static void bcm63xx_irq_dispatch_internal(void)
 904 +{
 905 +       u32 pending;
 906 +       static int i;
 907 +
 908 +       pending = bcm_perf_readl(PERF_IRQMASK_REG) &
 909 +               bcm_perf_readl(PERF_IRQSTAT_REG);
 910 +
 911 +       if (!pending)
 912 +               return ;
 913 +
 914 +       while (1) {
 915 +               int to_call = i;
 916 +
 917 +               i = (i + 1) & 0x1f;
 918 +               if (pending & (1 << to_call)) {
 919 +                       do_IRQ(to_call + IRQ_INTERNAL_BASE);
 920 +                       break;
 921 +               }
 922 +       }
 923 +}
 924 +
 925 +asmlinkage void plat_irq_dispatch(void)
 926 +{
 927 +       u32 cause;
 928 +
 929 +       do {
 930 +               cause = read_c0_cause() & read_c0_status() & ST0_IM;
 931 +
 932 +               if (!cause)
 933 +                       break;
 934 +
 935 +               if (cause & CAUSEF_IP7)
 936 +                       do_IRQ(7);
 937 +               if (cause & CAUSEF_IP2)
 938 +                       bcm63xx_irq_dispatch_internal();
 939 +               if (cause & CAUSEF_IP3)
 940 +                       do_IRQ(IRQ_EXT_0);
 941 +               if (cause & CAUSEF_IP4)
 942 +                       do_IRQ(IRQ_EXT_1);
 943 +               if (cause & CAUSEF_IP5)
 944 +                       do_IRQ(IRQ_EXT_2);
 945 +               if (cause & CAUSEF_IP6)
 946 +                       do_IRQ(IRQ_EXT_3);
 947 +       } while (1);
 948 +}
 949 +
 950 +/*
 951 + * internal IRQs operations: only mask/unmask on PERF irq mask
 952 + * register.
 953 + */
 954 +static inline void bcm63xx_internal_irq_mask(unsigned int irq)
 955 +{
 956 +       u32 mask;
 957 +
 958 +       irq -= IRQ_INTERNAL_BASE;
 959 +       mask = bcm_perf_readl(PERF_IRQMASK_REG);
 960 +       mask &= ~(1 << irq);
 961 +       bcm_perf_writel(mask, PERF_IRQMASK_REG);
 962 +}
 963 +
 964 +static void bcm63xx_internal_irq_unmask(unsigned int irq)
 965 +{
 966 +       u32 mask;
 967 +
 968 +       irq -= IRQ_INTERNAL_BASE;
 969 +       mask = bcm_perf_readl(PERF_IRQMASK_REG);
 970 +       mask |= (1 << irq);
 971 +       bcm_perf_writel(mask, PERF_IRQMASK_REG);
 972 +}
 973 +
 974 +static unsigned int bcm63xx_internal_irq_startup(unsigned int irq)
 975 +{
 976 +       bcm63xx_internal_irq_unmask(irq);
 977 +       return 0;
 978 +}
 979 +
 980 +/*
 981 + * external IRQs operations: mask/unmask and clear on PERF external
 982 + * irq control register.
 983 + */
 984 +static void bcm63xx_external_irq_mask(unsigned int irq)
 985 +{
 986 +       u32 reg;
 987 +
 988 +       irq -= IRQ_EXT_BASE;
 989 +       reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
 990 +       reg &= ~EXTIRQ_CFG_MASK(irq);
 991 +       bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
 992 +}
 993 +
 994 +static void bcm63xx_external_irq_unmask(unsigned int irq)
 995 +{
 996 +       u32 reg;
 997 +
 998 +       irq -= IRQ_EXT_BASE;
 999 +       reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
1000 +       reg |= EXTIRQ_CFG_MASK(irq);
1001 +       bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
1002 +}
1003 +
1004 +static void bcm63xx_external_irq_clear(unsigned int irq)
1005 +{
1006 +       u32 reg;
1007 +
1008 +       irq -= IRQ_EXT_BASE;
1009 +       reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
1010 +       reg |= EXTIRQ_CFG_CLEAR(irq);
1011 +       bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
1012 +}
1013 +
1014 +static unsigned int bcm63xx_external_irq_startup(unsigned int irq)
1015 +{
1016 +       set_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
1017 +       irq_enable_hazard();
1018 +       bcm63xx_external_irq_unmask(irq);
1019 +       return 0;
1020 +}
1021 +
1022 +static void bcm63xx_external_irq_shutdown(unsigned int irq)
1023 +{
1024 +       bcm63xx_external_irq_mask(irq);
1025 +       clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE));
1026 +       irq_disable_hazard();
1027 +}
1028 +
1029 +static int bcm63xx_external_irq_set_type(unsigned int irq,
1030 +                                        unsigned int flow_type)
1031 +{
1032 +       u32 reg;
1033 +       struct irq_desc *desc = irq_desc + irq;
1034 +
1035 +       irq -= IRQ_EXT_BASE;
1036 +
1037 +       flow_type &= IRQ_TYPE_SENSE_MASK;
1038 +
1039 +       if (flow_type == IRQ_TYPE_NONE)
1040 +               flow_type = IRQ_TYPE_LEVEL_LOW;
1041 +
1042 +       reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
1043 +       switch (flow_type) {
1044 +       case IRQ_TYPE_EDGE_BOTH:
1045 +               reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
1046 +               reg |= EXTIRQ_CFG_BOTHEDGE(irq);
1047 +               break;
1048 +
1049 +       case IRQ_TYPE_EDGE_RISING:
1050 +               reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
1051 +               reg |= EXTIRQ_CFG_SENSE(irq);
1052 +               reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
1053 +               break;
1054 +
1055 +       case IRQ_TYPE_EDGE_FALLING:
1056 +               reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
1057 +               reg &= ~EXTIRQ_CFG_SENSE(irq);
1058 +               reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
1059 +               break;
1060 +
1061 +       case IRQ_TYPE_LEVEL_HIGH:
1062 +               reg |= EXTIRQ_CFG_LEVELSENSE(irq);
1063 +               reg |= EXTIRQ_CFG_SENSE(irq);
1064 +               break;
1065 +
1066 +       case IRQ_TYPE_LEVEL_LOW:
1067 +               reg |= EXTIRQ_CFG_LEVELSENSE(irq);
1068 +               reg &= ~EXTIRQ_CFG_SENSE(irq);
1069 +               break;
1070 +
1071 +       default:
1072 +               printk(KERN_ERR "bogus flow type combination given !\n");
1073 +               return -EINVAL;
1074 +       }
1075 +       bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
1076 +
1077 +       if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))  {
1078 +               desc->status |= IRQ_LEVEL;
1079 +               desc->handle_irq = handle_level_irq;
1080 +       } else {
1081 +               desc->handle_irq = handle_edge_irq;
1082 +       }
1083 +
1084 +       return 0;
1085 +}
1086 +
1087 +static struct irq_chip bcm63xx_internal_irq_chip = {
1088 +       .name           = "bcm63xx_ipic",
1089 +       .startup        = bcm63xx_internal_irq_startup,
1090 +       .shutdown       = bcm63xx_internal_irq_mask,
1091 +
1092 +       .mask           = bcm63xx_internal_irq_mask,
1093 +       .mask_ack       = bcm63xx_internal_irq_mask,
1094 +       .unmask         = bcm63xx_internal_irq_unmask,
1095 +};
1096 +
1097 +static struct irq_chip bcm63xx_external_irq_chip = {
1098 +       .name           = "bcm63xx_epic",
1099 +       .startup        = bcm63xx_external_irq_startup,
1100 +       .shutdown       = bcm63xx_external_irq_shutdown,
1101 +
1102 +       .ack            = bcm63xx_external_irq_clear,
1103 +
1104 +       .mask           = bcm63xx_external_irq_mask,
1105 +       .unmask         = bcm63xx_external_irq_unmask,
1106 +
1107 +       .set_type       = bcm63xx_external_irq_set_type,
1108 +};
1109 +
1110 +static struct irqaction cpu_ip2_cascade_action = {
1111 +       .handler        = no_action,
1112 +       .name           = "cascade_ip2",
1113 +};
1114 +
1115 +void __init arch_init_irq(void)
1116 +{
1117 +       int i;
1118 +
1119 +       mips_cpu_irq_init();
1120 +       for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
1121 +               set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
1122 +                                        handle_level_irq);
1123 +
1124 +       for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
1125 +               set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
1126 +                                        handle_edge_irq);
1127 +
1128 +       setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
1129 +}
1130 --- /dev/null
1131 +++ b/arch/mips/bcm63xx/prom.c
1132 @@ -0,0 +1,43 @@
1133 +/*
1134 + * This file is subject to the terms and conditions of the GNU General Public
1135 + * License.  See the file "COPYING" in the main directory of this archive
1136 + * for more details.
1137 + *
1138 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
1139 + */
1140 +
1141 +#include <linux/init.h>
1142 +#include <linux/bootmem.h>
1143 +#include <asm/bootinfo.h>
1144 +#include <bcm63xx_cpu.h>
1145 +#include <bcm63xx_io.h>
1146 +#include <bcm63xx_regs.h>
1147 +
1148 +void __init prom_init(void)
1149 +{
1150 +       u32 reg, mask;
1151 +
1152 +       bcm63xx_cpu_init();
1153 +
1154 +       /* stop any running watchdog */
1155 +       bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG);
1156 +       bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
1157 +
1158 +       /* disable all hardware blocks clock for now */
1159 +       if (BCMCPU_IS_6348())
1160 +               mask = CKCTL_6348_ALL_SAFE_EN;
1161 +       else
1162 +               /* BCMCPU_IS_6358() */
1163 +               mask = CKCTL_6358_ALL_SAFE_EN;
1164 +
1165 +       reg = bcm_perf_readl(PERF_CKCTL_REG);
1166 +       reg &= ~mask;
1167 +       bcm_perf_writel(reg, PERF_CKCTL_REG);
1168 +
1169 +       /* assign command line from kernel config */
1170 +       strcpy(arcs_cmdline, CONFIG_CMDLINE);
1171 +}
1172 +
1173 +void __init prom_free_prom_memory(void)
1174 +{
1175 +}
1176 --- /dev/null
1177 +++ b/arch/mips/bcm63xx/setup.c
1178 @@ -0,0 +1,108 @@
1179 +/*
1180 + * This file is subject to the terms and conditions of the GNU General Public
1181 + * License.  See the file "COPYING" in the main directory of this archive
1182 + * for more details.
1183 + *
1184 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
1185 + */
1186 +
1187 +#include <linux/init.h>
1188 +#include <linux/kernel.h>
1189 +#include <linux/delay.h>
1190 +#include <linux/bootmem.h>
1191 +#include <linux/ioport.h>
1192 +#include <linux/pm.h>
1193 +#include <asm/bootinfo.h>
1194 +#include <asm/time.h>
1195 +#include <asm/reboot.h>
1196 +#include <asm/cacheflush.h>
1197 +#include <bcm63xx_cpu.h>
1198 +#include <bcm63xx_regs.h>
1199 +#include <bcm63xx_io.h>
1200 +
1201 +void bcm63xx_machine_halt(void)
1202 +{
1203 +       printk(KERN_INFO "System halted\n");
1204 +       while (1);
1205 +}
1206 +
1207 +static void bcm6348_a1_reboot(void)
1208 +{
1209 +       u32 reg;
1210 +
1211 +       /* soft reset all blocks */
1212 +       printk(KERN_INFO "soft-reseting all blocks ...\n");
1213 +       reg = bcm_perf_readl(PERF_SOFTRESET_REG);
1214 +       reg &= ~SOFTRESET_6348_ALL;
1215 +       bcm_perf_writel(reg, PERF_SOFTRESET_REG);
1216 +       mdelay(10);
1217 +
1218 +       reg = bcm_perf_readl(PERF_SOFTRESET_REG);
1219 +       reg |= SOFTRESET_6348_ALL;
1220 +       bcm_perf_writel(reg, PERF_SOFTRESET_REG);
1221 +       mdelay(10);
1222 +
1223 +       /* Jump to the power on address. */
1224 +       printk(KERN_INFO "jumping to reset vector.\n");
1225 +       /* set high vectors (base at 0xbfc00000 */
1226 +       set_c0_status(ST0_BEV | ST0_ERL);
1227 +       /* run uncached in kseg0 */
1228 +       change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
1229 +       __flush_cache_all();
1230 +       /* remove all wired TLB entries */
1231 +       write_c0_wired(0);
1232 +       __asm__ __volatile__(
1233 +               "jr\t%0"
1234 +               :
1235 +               : "r" (0xbfc00000));
1236 +       while (1);
1237 +}
1238 +
1239 +void bcm63xx_machine_reboot(void)
1240 +{
1241 +       u32 reg;
1242 +
1243 +       /* mask and clear all external irq */
1244 +       reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
1245 +       reg &= ~EXTIRQ_CFG_MASK_ALL;
1246 +       reg |= EXTIRQ_CFG_CLEAR_ALL;
1247 +       bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
1248 +
1249 +       if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
1250 +               bcm6348_a1_reboot();
1251 +
1252 +       printk(KERN_INFO "triggering watchdog soft-reset...\n");
1253 +       bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG);
1254 +       while (1);
1255 +}
1256 +
1257 +static void __bcm63xx_machine_reboot(char *p)
1258 +{
1259 +       bcm63xx_machine_reboot();
1260 +}
1261 +
1262 +/*
1263 + * return system type in /proc/cpuinfo
1264 + */
1265 +const char *get_system_type(void)
1266 +{
1267 +       static char buf[128];
1268 +       sprintf(buf, "bcm963xx (0x%04x/0x%04X)",
1269 +               bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
1270 +       return buf;
1271 +}
1272 +
1273 +void __init plat_time_init(void)
1274 +{
1275 +       mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
1276 +}
1277 +void __init plat_mem_setup(void)
1278 +{
1279 +       add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM);
1280 +
1281 +       _machine_halt = bcm63xx_machine_halt;
1282 +       _machine_restart = __bcm63xx_machine_reboot;
1283 +       pm_power_off = bcm63xx_machine_halt;
1284 +
1285 +       set_io_port_base(0);
1286 +}
1287 --- /dev/null
1288 +++ b/arch/mips/bcm63xx/timer.c
1289 @@ -0,0 +1,205 @@
1290 +/*
1291 + * This file is subject to the terms and conditions of the GNU General Public
1292 + * License.  See the file "COPYING" in the main directory of this archive
1293 + * for more details.
1294 + *
1295 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
1296 + */
1297 +
1298 +#include <linux/kernel.h>
1299 +#include <linux/err.h>
1300 +#include <linux/module.h>
1301 +#include <linux/spinlock.h>
1302 +#include <linux/interrupt.h>
1303 +#include <linux/clk.h>
1304 +#include <bcm63xx_cpu.h>
1305 +#include <bcm63xx_io.h>
1306 +#include <bcm63xx_timer.h>
1307 +#include <bcm63xx_regs.h>
1308 +
1309 +static DEFINE_SPINLOCK(timer_reg_lock);
1310 +static DEFINE_SPINLOCK(timer_data_lock);
1311 +static struct clk *periph_clk;
1312 +
1313 +static struct timer_data {
1314 +       void    (*cb)(void *);
1315 +       void    *data;
1316 +} timer_data[BCM63XX_TIMER_COUNT];
1317 +
1318 +static irqreturn_t timer_interrupt(int irq, void *dev_id)
1319 +{
1320 +       u32 stat;
1321 +       int i;
1322 +
1323 +       spin_lock(&timer_reg_lock);
1324 +       stat = bcm_timer_readl(TIMER_IRQSTAT_REG);
1325 +       bcm_timer_writel(stat, TIMER_IRQSTAT_REG);
1326 +       spin_unlock(&timer_reg_lock);
1327 +
1328 +       for (i = 0; i < BCM63XX_TIMER_COUNT; i++) {
1329 +               if (!(stat & TIMER_IRQSTAT_TIMER_CAUSE(i)))
1330 +                       continue;
1331 +
1332 +               spin_lock(&timer_data_lock);
1333 +               if (!timer_data[i].cb) {
1334 +                       spin_unlock(&timer_data_lock);
1335 +                       continue;
1336 +               }
1337 +
1338 +               timer_data[i].cb(timer_data[i].data);
1339 +               spin_unlock(&timer_data_lock);
1340 +       }
1341 +
1342 +       return IRQ_HANDLED;
1343 +}
1344 +
1345 +int bcm63xx_timer_enable(int id)
1346 +{
1347 +       u32 reg;
1348 +       unsigned long flags;
1349 +
1350 +       if (id >= BCM63XX_TIMER_COUNT)
1351 +               return -EINVAL;
1352 +
1353 +       spin_lock_irqsave(&timer_reg_lock, flags);
1354 +
1355 +       reg = bcm_timer_readl(TIMER_CTLx_REG(id));
1356 +       reg |= TIMER_CTL_ENABLE_MASK;
1357 +       bcm_timer_writel(reg, TIMER_CTLx_REG(id));
1358 +
1359 +       reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
1360 +       reg |= TIMER_IRQSTAT_TIMER_IR_EN(id);
1361 +       bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
1362 +
1363 +       spin_unlock_irqrestore(&timer_reg_lock, flags);
1364 +       return 0;
1365 +}
1366 +
1367 +EXPORT_SYMBOL(bcm63xx_timer_enable);
1368 +
1369 +int bcm63xx_timer_disable(int id)
1370 +{
1371 +       u32 reg;
1372 +       unsigned long flags;
1373 +
1374 +       if (id >= BCM63XX_TIMER_COUNT)
1375 +               return -EINVAL;
1376 +
1377 +       spin_lock_irqsave(&timer_reg_lock, flags);
1378 +
1379 +       reg = bcm_timer_readl(TIMER_CTLx_REG(id));
1380 +       reg &= ~TIMER_CTL_ENABLE_MASK;
1381 +       bcm_timer_writel(reg, TIMER_CTLx_REG(id));
1382 +
1383 +       reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
1384 +       reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id);
1385 +       bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
1386 +
1387 +       spin_unlock_irqrestore(&timer_reg_lock, flags);
1388 +       return 0;
1389 +}
1390 +
1391 +EXPORT_SYMBOL(bcm63xx_timer_disable);
1392 +
1393 +int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data)
1394 +{
1395 +       unsigned long flags;
1396 +       int ret;
1397 +
1398 +       if (id >= BCM63XX_TIMER_COUNT || !callback)
1399 +               return -EINVAL;
1400 +
1401 +       ret = 0;
1402 +       spin_lock_irqsave(&timer_data_lock, flags);
1403 +       if (timer_data[id].cb) {
1404 +               ret = -EBUSY;
1405 +               goto out;
1406 +       }
1407 +
1408 +       timer_data[id].cb = callback;
1409 +       timer_data[id].data = data;
1410 +
1411 +out:
1412 +       spin_unlock_irqrestore(&timer_data_lock, flags);
1413 +       return ret;
1414 +}
1415 +
1416 +EXPORT_SYMBOL(bcm63xx_timer_register);
1417 +
1418 +void bcm63xx_timer_unregister(int id)
1419 +{
1420 +       unsigned long flags;
1421 +
1422 +       if (id >= BCM63XX_TIMER_COUNT)
1423 +               return;
1424 +
1425 +       spin_lock_irqsave(&timer_data_lock, flags);
1426 +       timer_data[id].cb = NULL;
1427 +       spin_unlock_irqrestore(&timer_data_lock, flags);
1428 +}
1429 +
1430 +EXPORT_SYMBOL(bcm63xx_timer_unregister);
1431 +
1432 +unsigned int bcm63xx_timer_countdown(unsigned int countdown_us)
1433 +{
1434 +       return (clk_get_rate(periph_clk) / (1000 * 1000)) * countdown_us;
1435 +}
1436 +
1437 +EXPORT_SYMBOL(bcm63xx_timer_countdown);
1438 +
1439 +int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us)
1440 +{
1441 +       u32 reg, countdown;
1442 +       unsigned long flags;
1443 +
1444 +       if (id >= BCM63XX_TIMER_COUNT)
1445 +               return -EINVAL;
1446 +
1447 +       countdown = bcm63xx_timer_countdown(countdown_us);
1448 +       if (countdown & ~TIMER_CTL_COUNTDOWN_MASK)
1449 +               return -EINVAL;
1450 +
1451 +       spin_lock_irqsave(&timer_reg_lock, flags);
1452 +       reg = bcm_timer_readl(TIMER_CTLx_REG(id));
1453 +
1454 +       if (monotonic)
1455 +               reg &= ~TIMER_CTL_MONOTONIC_MASK;
1456 +       else
1457 +               reg |= TIMER_CTL_MONOTONIC_MASK;
1458 +
1459 +       reg &= ~TIMER_CTL_COUNTDOWN_MASK;
1460 +       reg |= countdown;
1461 +       bcm_timer_writel(reg, TIMER_CTLx_REG(id));
1462 +
1463 +       spin_unlock_irqrestore(&timer_reg_lock, flags);
1464 +       return 0;
1465 +}
1466 +
1467 +EXPORT_SYMBOL(bcm63xx_timer_set);
1468 +
1469 +int bcm63xx_timer_init(void)
1470 +{
1471 +       int ret, irq;
1472 +       u32 reg;
1473 +
1474 +       reg = bcm_timer_readl(TIMER_IRQSTAT_REG);
1475 +       reg &= ~TIMER_IRQSTAT_TIMER0_IR_EN;
1476 +       reg &= ~TIMER_IRQSTAT_TIMER1_IR_EN;
1477 +       reg &= ~TIMER_IRQSTAT_TIMER2_IR_EN;
1478 +       bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
1479 +
1480 +       periph_clk = clk_get(NULL, "periph");
1481 +       if (IS_ERR(periph_clk))
1482 +               return -ENODEV;
1483 +
1484 +       irq = bcm63xx_get_irq_number(IRQ_TIMER);
1485 +       ret = request_irq(irq, timer_interrupt, 0, "bcm63xx_timer", NULL);
1486 +       if (ret) {
1487 +               printk(KERN_ERR "bcm63xx_timer: failed to register irq\n");
1488 +               return ret;
1489 +       }
1490 +
1491 +       return 0;
1492 +}
1493 +
1494 +arch_initcall(bcm63xx_timer_init);
1495 --- a/include/asm-mips/fixmap.h
1496 +++ b/include/asm-mips/fixmap.h
1497 @@ -67,11 +67,15 @@ enum fixed_addresses {
1498   * the start of the fixmap, and leave one page empty
1499   * at the top of mem..
1500   */
1501 +#ifdef CONFIG_BCM63XX
1502 +#define FIXADDR_TOP     ((unsigned long)(long)(int)0xff000000)
1503 +#else
1504  #if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX)
1505  #define FIXADDR_TOP    ((unsigned long)(long)(int)(0xff000000 - 0x20000))
1506  #else
1507  #define FIXADDR_TOP    ((unsigned long)(long)(int)0xfffe0000)
1508  #endif
1509 +#endif
1510  #define FIXADDR_SIZE   (__end_of_fixed_addresses << PAGE_SHIFT)
1511  #define FIXADDR_START  (FIXADDR_TOP - FIXADDR_SIZE)
1512
1513 --- /dev/null
1514 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_clk.h
1515 @@ -0,0 +1,11 @@
1516 +#ifndef BCM63XX_CLK_H_
1517 +#define BCM63XX_CLK_H_
1518 +
1519 +struct clk {
1520 +       void            (*set)(struct clk *, int);
1521 +       unsigned int    rate;
1522 +       unsigned int    usage;
1523 +       int             id;
1524 +};
1525 +
1526 +#endif /* ! BCM63XX_CLK_H_ */
1527 --- /dev/null
1528 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
1529 @@ -0,0 +1,314 @@
1530 +#ifndef BCM63XX_CPU_H_
1531 +#define BCM63XX_CPU_H_
1532 +
1533 +#include <linux/types.h>
1534 +#include <linux/init.h>
1535 +
1536 +/*
1537 + * Macro to fetch bcm63xx cpu id and revision, should be optimized at
1538 + * compile time if only one CPU support is enabled (idea stolen from
1539 + * arm mach-types)
1540 + */
1541 +#define BCM6348_CPU_ID         0x6348
1542 +#define BCM6358_CPU_ID         0x6358
1543 +
1544 +void __init bcm63xx_cpu_init(void);
1545 +u16 __bcm63xx_get_cpu_id(void);
1546 +u16 bcm63xx_get_cpu_rev(void);
1547 +unsigned int bcm63xx_get_cpu_freq(void);
1548 +
1549 +#ifdef CONFIG_BCM63XX_CPU_6348
1550 +# ifdef bcm63xx_get_cpu_id
1551 +#  undef bcm63xx_get_cpu_id
1552 +#  define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
1553 +#  define BCMCPU_RUNTIME_DETECT
1554 +# else
1555 +#  define bcm63xx_get_cpu_id() BCM6348_CPU_ID
1556 +# endif
1557 +# define BCMCPU_IS_6348()      (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
1558 +#else
1559 +# define BCMCPU_IS_6348()      (0)
1560 +#endif
1561 +
1562 +#ifdef CONFIG_BCM63XX_CPU_6358
1563 +# ifdef bcm63xx_get_cpu_id
1564 +#  undef bcm63xx_get_cpu_id
1565 +#  define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
1566 +#  define BCMCPU_RUNTIME_DETECT
1567 +# else
1568 +#  define bcm63xx_get_cpu_id() BCM6358_CPU_ID
1569 +# endif
1570 +# define BCMCPU_IS_6358()      (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
1571 +#else
1572 +# define BCMCPU_IS_6358()      (0)
1573 +#endif
1574 +
1575 +#ifndef bcm63xx_get_cpu_id
1576 +#error "No CPU support configured"
1577 +#endif
1578 +
1579 +/*
1580 + * While registers sets are (mostly) the same across 63xx CPU, base
1581 + * address of these sets do change.
1582 + */
1583 +enum bcm63xx_regs_set {
1584 +       RSET_DSL_LMEM = 0,
1585 +       RSET_PERF,
1586 +       RSET_TIMER,
1587 +       RSET_WDT,
1588 +       RSET_UART0,
1589 +       RSET_GPIO,
1590 +       RSET_SPI,
1591 +       RSET_UDC0,
1592 +       RSET_OHCI0,
1593 +       RSET_OHCI_PRIV,
1594 +       RSET_USBH_PRIV,
1595 +       RSET_MPI,
1596 +       RSET_PCMCIA,
1597 +       RSET_DSL,
1598 +       RSET_ENET0,
1599 +       RSET_ENET1,
1600 +       RSET_ENETDMA,
1601 +       RSET_EHCI0,
1602 +       RSET_SDRAM,
1603 +       RSET_MEMC,
1604 +       RSET_DDR,
1605 +};
1606 +
1607 +#define RSET_DSL_LMEM_SIZE             (64 * 1024 * 4)
1608 +#define RSET_DSL_SIZE                  4096
1609 +#define RSET_WDT_SIZE                  12
1610 +#define RSET_ENET_SIZE                 2048
1611 +#define RSET_ENETDMA_SIZE              2048
1612 +#define RSET_UART_SIZE                 24
1613 +#define RSET_UDC_SIZE                  256
1614 +#define RSET_OHCI_SIZE                 256
1615 +#define RSET_EHCI_SIZE                 256
1616 +#define RSET_PCMCIA_SIZE               12
1617 +
1618 +/*
1619 + * 6348 register sets base address
1620 + */
1621 +#define BCM_6348_DSL_LMEM_BASE         (0xfff00000)
1622 +#define BCM_6348_PERF_BASE             (0xfffe0000)
1623 +#define BCM_6348_TIMER_BASE            (0xfffe0200)
1624 +#define BCM_6348_WDT_BASE              (0xfffe021c)
1625 +#define BCM_6348_UART0_BASE            (0xfffe0300)
1626 +#define BCM_6348_GPIO_BASE             (0xfffe0400)
1627 +#define BCM_6348_SPI_BASE              (0xfffe0c00)
1628 +#define BCM_6348_UDC0_BASE             (0xfffe1000)
1629 +#define BCM_6348_OHCI0_BASE            (0xfffe1b00)
1630 +#define BCM_6348_OHCI_PRIV_BASE                (0xfffe1c00)
1631 +#define BCM_6348_USBH_PRIV_BASE                (0xdeadbeef)
1632 +#define BCM_6348_MPI_BASE              (0xfffe2000)
1633 +#define BCM_6348_PCMCIA_BASE           (0xfffe2054)
1634 +#define BCM_6348_SDRAM_REGS_BASE       (0xfffe2300)
1635 +#define BCM_6348_DSL_BASE              (0xfffe3000)
1636 +#define BCM_6348_ENET0_BASE            (0xfffe6000)
1637 +#define BCM_6348_ENET1_BASE            (0xfffe6800)
1638 +#define BCM_6348_ENETDMA_BASE          (0xfffe7000)
1639 +#define BCM_6348_EHCI0_BASE            (0xdeadbeef)
1640 +#define BCM_6348_SDRAM_BASE            (0xfffe2300)
1641 +#define BCM_6348_MEMC_BASE             (0xdeadbeef)
1642 +#define BCM_6348_DDR_BASE              (0xdeadbeef)
1643 +
1644 +/*
1645 + * 6358 register sets base address
1646 + */
1647 +#define BCM_6358_DSL_LMEM_BASE         (0xfff00000)
1648 +#define BCM_6358_PERF_BASE             (0xfffe0000)
1649 +#define BCM_6358_TIMER_BASE            (0xfffe0040)
1650 +#define BCM_6358_WDT_BASE              (0xfffe005c)
1651 +#define BCM_6358_UART0_BASE            (0xfffe0100)
1652 +#define BCM_6358_GPIO_BASE             (0xfffe0080)
1653 +#define BCM_6358_SPI_BASE              (0xdeadbeef)
1654 +#define BCM_6358_UDC0_BASE             (0xfffe0800)
1655 +#define BCM_6358_OHCI0_BASE            (0xfffe1400)
1656 +#define BCM_6358_OHCI_PRIV_BASE                (0xdeadbeef)
1657 +#define BCM_6358_USBH_PRIV_BASE                (0xfffe1500)
1658 +#define BCM_6358_MPI_BASE              (0xfffe1000)
1659 +#define BCM_6358_PCMCIA_BASE           (0xfffe1054)
1660 +#define BCM_6358_SDRAM_REGS_BASE       (0xfffe2300)
1661 +#define BCM_6358_DSL_BASE              (0xfffe3000)
1662 +#define BCM_6358_ENET0_BASE            (0xfffe4000)
1663 +#define BCM_6358_ENET1_BASE            (0xfffe4800)
1664 +#define BCM_6358_ENETDMA_BASE          (0xfffe5000)
1665 +#define BCM_6358_EHCI0_BASE            (0xfffe1300)
1666 +#define BCM_6358_SDRAM_BASE            (0xdeadbeef)
1667 +#define BCM_6358_MEMC_BASE             (0xfffe1200)
1668 +#define BCM_6358_DDR_BASE              (0xfffe12a0)
1669 +
1670 +
1671 +extern const unsigned long *bcm63xx_regs_base;
1672 +
1673 +static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
1674 +{
1675 +#ifdef BCMCPU_RUNTIME_DETECT
1676 +       return bcm63xx_regs_base[set];
1677 +#else
1678 +#ifdef CONFIG_BCM63XX_CPU_6348
1679 +       switch (set) {
1680 +       case RSET_DSL_LMEM:
1681 +               return BCM_6348_DSL_LMEM_BASE;
1682 +       case RSET_PERF:
1683 +               return BCM_6348_PERF_BASE;
1684 +       case RSET_TIMER:
1685 +               return BCM_6348_TIMER_BASE;
1686 +       case RSET_WDT:
1687 +               return BCM_6348_WDT_BASE;
1688 +       case RSET_UART0:
1689 +               return BCM_6348_UART0_BASE;
1690 +       case RSET_GPIO:
1691 +               return BCM_6348_GPIO_BASE;
1692 +       case RSET_SPI:
1693 +               return BCM_6348_SPI_BASE;
1694 +       case RSET_UDC0:
1695 +               return BCM_6348_UDC0_BASE;
1696 +       case RSET_OHCI0:
1697 +               return BCM_6348_OHCI0_BASE;
1698 +       case RSET_OHCI_PRIV:
1699 +               return BCM_6348_OHCI_PRIV_BASE;
1700 +       case RSET_USBH_PRIV:
1701 +               return BCM_6348_USBH_PRIV_BASE;
1702 +       case RSET_MPI:
1703 +               return BCM_6348_MPI_BASE;
1704 +       case RSET_PCMCIA:
1705 +               return BCM_6348_PCMCIA_BASE;
1706 +       case RSET_DSL:
1707 +               return BCM_6348_DSL_BASE;
1708 +       case RSET_ENET0:
1709 +               return BCM_6348_ENET0_BASE;
1710 +       case RSET_ENET1:
1711 +               return BCM_6348_ENET1_BASE;
1712 +       case RSET_ENETDMA:
1713 +               return BCM_6348_ENETDMA_BASE;
1714 +       case RSET_EHCI0:
1715 +               return BCM_6348_EHCI0_BASE;
1716 +       case RSET_SDRAM:
1717 +               return BCM_6348_SDRAM_BASE;
1718 +       case RSET_MEMC:
1719 +               return BCM_6348_MEMC_BASE;
1720 +       case RSET_DDR:
1721 +               return BCM_6348_DDR_BASE;
1722 +       }
1723 +#endif
1724 +#ifdef CONFIG_BCM63XX_CPU_6358
1725 +       switch (set) {
1726 +       case RSET_DSL_LMEM:
1727 +               return BCM_6358_DSL_LMEM_BASE;
1728 +       case RSET_PERF:
1729 +               return BCM_6358_PERF_BASE;
1730 +       case RSET_TIMER:
1731 +               return BCM_6358_TIMER_BASE;
1732 +       case RSET_WDT:
1733 +               return BCM_6358_WDT_BASE;
1734 +       case RSET_UART0:
1735 +               return BCM_6358_UART0_BASE;
1736 +       case RSET_GPIO:
1737 +               return BCM_6358_GPIO_BASE;
1738 +       case RSET_SPI:
1739 +               return BCM_6358_SPI_BASE;
1740 +       case RSET_UDC0:
1741 +               return BCM_6358_UDC0_BASE;
1742 +       case RSET_OHCI0:
1743 +               return BCM_6358_OHCI0_BASE;
1744 +       case RSET_OHCI_PRIV:
1745 +               return BCM_6358_OHCI_PRIV_BASE;
1746 +       case RSET_USBH_PRIV:
1747 +               return BCM_6358_USBH_PRIV_BASE;
1748 +       case RSET_MPI:
1749 +               return BCM_6358_MPI_BASE;
1750 +       case RSET_PCMCIA:
1751 +               return BCM_6358_PCMCIA_BASE;
1752 +       case RSET_ENET0:
1753 +               return BCM_6358_ENET0_BASE;
1754 +       case RSET_ENET1:
1755 +               return BCM_6358_ENET1_BASE;
1756 +       case RSET_ENETDMA:
1757 +               return BCM_6358_ENETDMA_BASE;
1758 +       case RSET_DSL:
1759 +               return BCM_6358_DSL_BASE;
1760 +       case RSET_EHCI0:
1761 +               return BCM_6358_EHCI0_BASE;
1762 +       case RSET_SDRAM:
1763 +               return BCM_6358_SDRAM_BASE;
1764 +       case RSET_MEMC:
1765 +               return BCM_6358_MEMC_BASE;
1766 +       case RSET_DDR:
1767 +               return BCM_6358_DDR_BASE;
1768 +       }
1769 +#endif
1770 +#endif
1771 +       /* unreached */
1772 +       return 0;
1773 +}
1774 +
1775 +/*
1776 + * IRQ number changes across CPU too
1777 + */
1778 +enum bcm63xx_irq {
1779 +       IRQ_TIMER = 0,
1780 +       IRQ_UART0,
1781 +       IRQ_DSL,
1782 +       IRQ_ENET0,
1783 +       IRQ_ENET1,
1784 +       IRQ_ENET_PHY,
1785 +       IRQ_OHCI0,
1786 +       IRQ_EHCI0,
1787 +       IRQ_PCMCIA0,
1788 +       IRQ_ENET0_RXDMA,
1789 +       IRQ_ENET0_TXDMA,
1790 +       IRQ_ENET1_RXDMA,
1791 +       IRQ_ENET1_TXDMA,
1792 +       IRQ_PCI,
1793 +       IRQ_PCMCIA,
1794 +};
1795 +
1796 +/*
1797 + * 6348 irqs
1798 + */
1799 +#define BCM_6348_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
1800 +#define BCM_6348_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
1801 +#define BCM_6348_DSL_IRQ               (IRQ_INTERNAL_BASE + 4)
1802 +#define BCM_6348_ENET1_IRQ             (IRQ_INTERNAL_BASE + 7)
1803 +#define BCM_6348_ENET0_IRQ             (IRQ_INTERNAL_BASE + 8)
1804 +#define BCM_6348_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 9)
1805 +#define BCM_6348_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 12)
1806 +#define BCM_6348_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 20)
1807 +#define BCM_6348_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 21)
1808 +#define BCM_6348_ENET1_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 22)
1809 +#define BCM_6348_ENET1_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 23)
1810 +#define BCM_6348_PCMCIA_IRQ            (IRQ_INTERNAL_BASE + 24)
1811 +#define BCM_6348_PCI_IRQ               (IRQ_INTERNAL_BASE + 24)
1812 +
1813 +/*
1814 + * 6358 irqs
1815 + */
1816 +#define BCM_6358_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
1817 +#define BCM_6358_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
1818 +#define BCM_6358_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 5)
1819 +#define BCM_6358_ENET1_IRQ             (IRQ_INTERNAL_BASE + 6)
1820 +#define BCM_6358_ENET0_IRQ             (IRQ_INTERNAL_BASE + 8)
1821 +#define BCM_6358_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 9)
1822 +#define BCM_6358_EHCI0_IRQ             (IRQ_INTERNAL_BASE + 10)
1823 +#define BCM_6358_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 15)
1824 +#define BCM_6358_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 16)
1825 +#define BCM_6358_ENET1_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 17)
1826 +#define BCM_6358_ENET1_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 18)
1827 +#define BCM_6358_DSL_IRQ               (IRQ_INTERNAL_BASE + 29)
1828 +#define BCM_6358_PCI_IRQ               (IRQ_INTERNAL_BASE + 31)
1829 +#define BCM_6358_PCMCIA_IRQ            (IRQ_INTERNAL_BASE + 24)
1830 +
1831 +extern const int *bcm63xx_irqs;
1832 +
1833 +static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
1834 +{
1835 +       return bcm63xx_irqs[irq];
1836 +}
1837 +
1838 +/*
1839 + * return installed memory size
1840 + */
1841 +unsigned int bcm63xx_get_memory_size(void);
1842 +
1843 +#endif /* !BCM63XX_CPU_H_ */
1844 --- /dev/null
1845 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_cs.h
1846 @@ -0,0 +1,10 @@
1847 +#ifndef BCM63XX_CS_H
1848 +#define BCM63XX_CS_H
1849 +
1850 +int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size);
1851 +int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait,
1852 +                          unsigned int setup, unsigned int hold);
1853 +int bcm63xx_set_cs_param(unsigned int cs, u32 flags);
1854 +int bcm63xx_set_cs_status(unsigned int cs, int enable);
1855 +
1856 +#endif /* !BCM63XX_CS_H */
1857 --- /dev/null
1858 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_gpio.h
1859 @@ -0,0 +1,14 @@
1860 +#ifndef BCM63XX_GPIO_H
1861 +#define BCM63XX_GPIO_H
1862 +
1863 +/* all helpers will BUG() if gpio count is >= 37. */
1864 +#define BCM63XX_GPIO_COUNT     37
1865 +
1866 +void bcm63xx_gpio_set_dataout(int gpio, int val);
1867 +int bcm63xx_gpio_get_datain(int gpio);
1868 +void bcm63xx_gpio_set_direction(int gpio, int dir);
1869 +
1870 +#define GPIO_DIR_OUT   0x0
1871 +#define GPIO_DIR_IN    0x1
1872 +
1873 +#endif /* !BCM63XX_GPIO_H */
1874 --- /dev/null
1875 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_io.h
1876 @@ -0,0 +1,93 @@
1877 +#ifndef BCM63XX_IO_H_
1878 +#define BCM63XX_IO_H_
1879 +
1880 +#include "bcm63xx_cpu.h"
1881 +
1882 +/*
1883 + * Physical memory map, RAM is mapped at 0x0.
1884 + *
1885 + * Note that size MUST be a power of two.
1886 + */
1887 +#define BCM_PCMCIA_COMMON_BASE_PA      (0x20000000)
1888 +#define BCM_PCMCIA_COMMON_SIZE         (16 * 1024 * 1024)
1889 +#define BCM_PCMCIA_COMMON_END_PA       (BCM_PCMCIA_COMMON_BASE_PA +    \
1890 +                                        BCM_PCMCIA_COMMON_SIZE - 1)
1891 +
1892 +#define BCM_PCMCIA_ATTR_BASE_PA                (0x21000000)
1893 +#define BCM_PCMCIA_ATTR_SIZE           (16 * 1024 * 1024)
1894 +#define BCM_PCMCIA_ATTR_END_PA         (BCM_PCMCIA_ATTR_BASE_PA +      \
1895 +                                        BCM_PCMCIA_ATTR_SIZE - 1)
1896 +
1897 +#define BCM_PCMCIA_IO_BASE_PA          (0x22000000)
1898 +#define BCM_PCMCIA_IO_SIZE             (64 * 1024)
1899 +#define BCM_PCMCIA_IO_END_PA           (BCM_PCMCIA_IO_BASE_PA +        \
1900 +                                       BCM_PCMCIA_IO_SIZE - 1)
1901 +
1902 +#define BCM_PCI_MEM_BASE_PA            (0x30000000)
1903 +#define BCM_PCI_MEM_SIZE               (128 * 1024 * 1024)
1904 +#define BCM_PCI_MEM_END_PA             (BCM_PCI_MEM_BASE_PA +          \
1905 +                                       BCM_PCI_MEM_SIZE - 1)
1906 +
1907 +#define BCM_PCI_IO_BASE_PA             (0x08000000)
1908 +#define BCM_PCI_IO_SIZE                        (64 * 1024)
1909 +#define BCM_PCI_IO_END_PA              (BCM_PCI_IO_BASE_PA +           \
1910 +                                       BCM_PCI_IO_SIZE - 1)
1911 +#define BCM_PCI_IO_HALF_PA             (BCM_PCI_IO_BASE_PA +           \
1912 +                                       (BCM_PCI_IO_SIZE / 2) - 1)
1913 +
1914 +#define BCM_CB_MEM_BASE_PA             (0x38000000)
1915 +#define BCM_CB_MEM_SIZE                        (128 * 1024 * 1024)
1916 +#define BCM_CB_MEM_END_PA              (BCM_CB_MEM_BASE_PA +           \
1917 +                                       BCM_CB_MEM_SIZE - 1)
1918 +
1919 +
1920 +/*
1921 + * Internal registers are accessed through KSEG3
1922 + */
1923 +#define BCM_REGS_VA(x) ((void __iomem *)(x))
1924 +
1925 +#define bcm_readb(a)   (*(volatile unsigned char *)    BCM_REGS_VA(a))
1926 +#define bcm_readw(a)   (*(volatile unsigned short *)   BCM_REGS_VA(a))
1927 +#define bcm_readl(a)   (*(volatile unsigned int *)     BCM_REGS_VA(a))
1928 +#define bcm_writeb(v,a)        (*(volatile unsigned char *)    BCM_REGS_VA((a)) = (v))
1929 +#define bcm_writew(v,a)        (*(volatile unsigned short *)   BCM_REGS_VA((a)) = (v))
1930 +#define bcm_writel(v,a)        (*(volatile unsigned int *)     BCM_REGS_VA((a)) = (v))
1931 +
1932 +/*
1933 + * IO helpers to access register set for current CPU
1934 + */
1935 +#define bcm_rset_readb(s,o)    bcm_readb(bcm63xx_regset_address(s) + (o))
1936 +#define bcm_rset_readw(s,o)    bcm_readw(bcm63xx_regset_address(s) + (o))
1937 +#define bcm_rset_readl(s,o)    bcm_readl(bcm63xx_regset_address(s) + (o))
1938 +#define bcm_rset_writeb(s,v,o) bcm_writeb((v), \
1939 +                                       bcm63xx_regset_address(s) + (o))
1940 +#define bcm_rset_writew(s,v,o) bcm_writew((v), \
1941 +                                       bcm63xx_regset_address(s) + (o))
1942 +#define bcm_rset_writel(s,v,o) bcm_writel((v), \
1943 +                                       bcm63xx_regset_address(s) + (o))
1944 +
1945 +/*
1946 + * helpers for frequently used register sets
1947 + */
1948 +#define bcm_perf_readl(o)      bcm_rset_readl(RSET_PERF, (o))
1949 +#define bcm_perf_writel(v,o)   bcm_rset_writel(RSET_PERF, (v), (o))
1950 +#define bcm_timer_readl(o)     bcm_rset_readl(RSET_TIMER, (o))
1951 +#define bcm_timer_writel(v,o)  bcm_rset_writel(RSET_TIMER, (v), (o))
1952 +#define bcm_wdt_readl(o)       bcm_rset_readl(RSET_WDT, (o))
1953 +#define bcm_wdt_writel(v,o)    bcm_rset_writel(RSET_WDT, (v), (o))
1954 +#define bcm_gpio_readl(o)      bcm_rset_readl(RSET_GPIO, (o))
1955 +#define bcm_gpio_writel(v,o)   bcm_rset_writel(RSET_GPIO, (v), (o))
1956 +#define bcm_uart0_readl(o)     bcm_rset_readl(RSET_UART0, (o))
1957 +#define bcm_uart0_writel(v,o)  bcm_rset_writel(RSET_UART0, (v), (o))
1958 +#define bcm_mpi_readl(o)       bcm_rset_readl(RSET_MPI, (o))
1959 +#define bcm_mpi_writel(v,o)    bcm_rset_writel(RSET_MPI, (v), (o))
1960 +#define bcm_pcmcia_readl(o)    bcm_rset_readl(RSET_PCMCIA, (o))
1961 +#define bcm_pcmcia_writel(v,o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
1962 +#define bcm_sdram_readl(o)     bcm_rset_readl(RSET_SDRAM, (o))
1963 +#define bcm_sdram_writel(v,o)  bcm_rset_writel(RSET_SDRAM, (v), (o))
1964 +#define bcm_memc_readl(o)      bcm_rset_readl(RSET_MEMC, (o))
1965 +#define bcm_memc_writel(v,o)   bcm_rset_writel(RSET_MEMC, (v), (o))
1966 +#define bcm_ddr_readl(o)       bcm_rset_readl(RSET_DDR, (o))
1967 +#define bcm_ddr_writel(v,o)    bcm_rset_writel(RSET_DDR, (v), (o))
1968 +
1969 +#endif /* ! BCM63XX_IO_H_ */
1970 --- /dev/null
1971 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_irq.h
1972 @@ -0,0 +1,15 @@
1973 +#ifndef BCM63XX_IRQ_H_
1974 +#define BCM63XX_IRQ_H_
1975 +
1976 +#include <bcm63xx_cpu.h>
1977 +
1978 +#define IRQ_MIPS_BASE                  0
1979 +#define IRQ_INTERNAL_BASE              8
1980 +
1981 +#define IRQ_EXT_BASE                   (IRQ_MIPS_BASE + 3)
1982 +#define IRQ_EXT_0                      (IRQ_EXT_BASE + 0)
1983 +#define IRQ_EXT_1                      (IRQ_EXT_BASE + 1)
1984 +#define IRQ_EXT_2                      (IRQ_EXT_BASE + 2)
1985 +#define IRQ_EXT_3                      (IRQ_EXT_BASE + 3)
1986 +
1987 +#endif /* ! BCM63XX_IRQ_H_ */
1988 --- /dev/null
1989 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_regs.h
1990 @@ -0,0 +1,728 @@
1991 +#ifndef BCM63XX_REGS_H_
1992 +#define BCM63XX_REGS_H_
1993 +
1994 +/*************************************************************************
1995 + * _REG relative to RSET_PERF
1996 + *************************************************************************/
1997 +
1998 +/* Chip Identifier / Revision register */
1999 +#define PERF_REV_REG                   0x0
2000 +#define REV_CHIPID_SHIFT               16
2001 +#define REV_CHIPID_MASK                        (0xffff << REV_CHIPID_SHIFT)
2002 +#define REV_REVID_SHIFT                        0
2003 +#define REV_REVID_MASK                 (0xffff << REV_REVID_SHIFT)
2004 +
2005 +/* Clock Control register */
2006 +#define PERF_CKCTL_REG                 0x4
2007 +
2008 +#define CKCTL_6348_ADSLPHY_EN          (1 << 0)
2009 +#define CKCTL_6348_MPI_EN              (1 << 1)
2010 +#define CKCTL_6348_SDRAM_EN            (1 << 2)
2011 +#define CKCTL_6348_M2M_EN              (1 << 3)
2012 +#define CKCTL_6348_ENET_EN             (1 << 4)
2013 +#define CKCTL_6348_SAR_EN              (1 << 5)
2014 +#define CKCTL_6348_USBS_EN             (1 << 6)
2015 +#define CKCTL_6348_USBH_EN             (1 << 8)
2016 +#define CKCTL_6348_SPI_EN              (1 << 9)
2017 +
2018 +#define CKCTL_6348_ALL_SAFE_EN         (CKCTL_6348_ADSLPHY_EN |        \
2019 +                                       CKCTL_6348_M2M_EN |             \
2020 +                                       CKCTL_6348_ENET_EN |            \
2021 +                                       CKCTL_6348_SAR_EN |             \
2022 +                                       CKCTL_6348_USBS_EN |            \
2023 +                                       CKCTL_6348_USBH_EN |            \
2024 +                                       CKCTL_6348_SPI_EN)
2025 +
2026 +#define CKCTL_6358_ENET_EN             (1 << 4)
2027 +#define CKCTL_6358_ADSLPHY_EN          (1 << 5)
2028 +#define CKCTL_6358_PCM_EN              (1 << 8)
2029 +#define CKCTL_6358_SPI_EN              (1 << 9)
2030 +#define CKCTL_6358_USBS_EN             (1 << 10)
2031 +#define CKCTL_6358_SAR_EN              (1 << 11)
2032 +#define CKCTL_6358_EMUSB_EN            (1 << 17)
2033 +#define CKCTL_6358_ENET0_EN            (1 << 18)
2034 +#define CKCTL_6358_ENET1_EN            (1 << 19)
2035 +#define CKCTL_6358_USBSU_EN            (1 << 20)
2036 +#define CKCTL_6358_EPHY_EN             (1 << 21)
2037 +
2038 +#define CKCTL_6358_ALL_SAFE_EN         (CKCTL_6358_ENET_EN |           \
2039 +                                       CKCTL_6358_ADSLPHY_EN |         \
2040 +                                       CKCTL_6358_PCM_EN |             \
2041 +                                       CKCTL_6358_SPI_EN |             \
2042 +                                       CKCTL_6358_USBS_EN |            \
2043 +                                       CKCTL_6358_SAR_EN |             \
2044 +                                       CKCTL_6358_EMUSB_EN |           \
2045 +                                       CKCTL_6358_ENET0_EN |           \
2046 +                                       CKCTL_6358_ENET1_EN |           \
2047 +                                       CKCTL_6358_USBSU_EN |           \
2048 +                                       CKCTL_6358_EPHY_EN)
2049 +
2050 +/* System PLL Control register  */
2051 +#define PERF_SYS_PLL_CTL_REG           0x8
2052 +#define SYS_PLL_SOFT_RESET             0x1
2053 +
2054 +/* Interrupt Mask register */
2055 +#define PERF_IRQMASK_REG               0xc
2056 +#define PERF_IRQSTAT_REG               0x10
2057 +
2058 +/* Interrupt Status register */
2059 +#define PERF_IRQSTAT_REG               0x10
2060 +
2061 +/* External Interrupt Configuration register */
2062 +#define PERF_EXTIRQ_CFG_REG            0x14
2063 +#define EXTIRQ_CFG_SENSE(x)            (1 << (x))
2064 +#define EXTIRQ_CFG_STAT(x)             (1 << (x + 5))
2065 +#define EXTIRQ_CFG_CLEAR(x)            (1 << (x + 10))
2066 +#define EXTIRQ_CFG_MASK(x)             (1 << (x + 15))
2067 +#define EXTIRQ_CFG_BOTHEDGE(x)         (1 << (x + 20))
2068 +#define EXTIRQ_CFG_LEVELSENSE(x)       (1 << (x + 25))
2069 +
2070 +#define EXTIRQ_CFG_CLEAR_ALL           (0xf << 10)
2071 +#define EXTIRQ_CFG_MASK_ALL            (0xf << 15)
2072 +
2073 +/* Soft Reset register */
2074 +#define PERF_SOFTRESET_REG             0x28
2075 +
2076 +#define SOFTRESET_6348_SPI_MASK                (1 << 0)
2077 +#define SOFTRESET_6348_ENET_MASK       (1 << 2)
2078 +#define SOFTRESET_6348_USBH_MASK       (1 << 3)
2079 +#define SOFTRESET_6348_USBS_MASK       (1 << 4)
2080 +#define SOFTRESET_6348_ADSL_MASK       (1 << 5)
2081 +#define SOFTRESET_6348_DMAMEM_MASK     (1 << 6)
2082 +#define SOFTRESET_6348_SAR_MASK                (1 << 7)
2083 +#define SOFTRESET_6348_ACLC_MASK       (1 << 8)
2084 +#define SOFTRESET_6348_ADSLMIPSPLL_MASK        (1 << 10)
2085 +
2086 +#define SOFTRESET_6348_ALL      (SOFTRESET_6348_SPI_MASK |             \
2087 +                                 SOFTRESET_6348_ENET_MASK |            \
2088 +                                 SOFTRESET_6348_USBH_MASK |            \
2089 +                                 SOFTRESET_6348_USBS_MASK |            \
2090 +                                 SOFTRESET_6348_ADSL_MASK |            \
2091 +                                 SOFTRESET_6348_DMAMEM_MASK |          \
2092 +                                 SOFTRESET_6348_SAR_MASK |             \
2093 +                                 SOFTRESET_6348_ACLC_MASK |            \
2094 +                                 SOFTRESET_6348_ADSLMIPSPLL_MASK)
2095 +
2096 +/* MIPS PLL control register */
2097 +#define PERF_MIPSPLLCTL_REG            0x34
2098 +#define MIPSPLLCTL_N1_SHIFT            20
2099 +#define MIPSPLLCTL_N1_MASK             (0x7 << MIPSPLLCTL_N1_SHIFT)
2100 +#define MIPSPLLCTL_N2_SHIFT            15
2101 +#define MIPSPLLCTL_N2_MASK             (0x1f << MIPSPLLCTL_N2_SHIFT)
2102 +#define MIPSPLLCTL_M1REF_SHIFT         12
2103 +#define MIPSPLLCTL_M1REF_MASK          (0x7 << MIPSPLLCTL_M1REF_SHIFT)
2104 +#define MIPSPLLCTL_M2REF_SHIFT         9
2105 +#define MIPSPLLCTL_M2REF_MASK          (0x7 << MIPSPLLCTL_M2REF_SHIFT)
2106 +#define MIPSPLLCTL_M1CPU_SHIFT         6
2107 +#define MIPSPLLCTL_M1CPU_MASK          (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
2108 +#define MIPSPLLCTL_M1BUS_SHIFT         3
2109 +#define MIPSPLLCTL_M1BUS_MASK          (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
2110 +#define MIPSPLLCTL_M2BUS_SHIFT         0
2111 +#define MIPSPLLCTL_M2BUS_MASK          (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
2112 +
2113 +/* ADSL PHY PLL Control register */
2114 +#define PERF_ADSLPLLCTL_REG            0x38
2115 +#define ADSLPLLCTL_N1_SHIFT            20
2116 +#define ADSLPLLCTL_N1_MASK             (0x7 << ADSLPLLCTL_N1_SHIFT)
2117 +#define ADSLPLLCTL_N2_SHIFT            15
2118 +#define ADSLPLLCTL_N2_MASK             (0x1f << ADSLPLLCTL_N2_SHIFT)
2119 +#define ADSLPLLCTL_M1REF_SHIFT         12
2120 +#define ADSLPLLCTL_M1REF_MASK          (0x7 << ADSLPLLCTL_M1REF_SHIFT)
2121 +#define ADSLPLLCTL_M2REF_SHIFT         9
2122 +#define ADSLPLLCTL_M2REF_MASK          (0x7 << ADSLPLLCTL_M2REF_SHIFT)
2123 +#define ADSLPLLCTL_M1CPU_SHIFT         6
2124 +#define ADSLPLLCTL_M1CPU_MASK          (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
2125 +#define ADSLPLLCTL_M1BUS_SHIFT         3
2126 +#define ADSLPLLCTL_M1BUS_MASK          (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
2127 +#define ADSLPLLCTL_M2BUS_SHIFT         0
2128 +#define ADSLPLLCTL_M2BUS_MASK          (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
2129 +
2130 +#define ADSLPLLCTL_VAL(n1,n2,m1ref,m2ref,m1cpu,m1bus,m2bus)            \
2131 +                               (((n1) << ADSLPLLCTL_N1_SHIFT) |        \
2132 +                               ((n2) << ADSLPLLCTL_N2_SHIFT) |         \
2133 +                               ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) |   \
2134 +                               ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) |   \
2135 +                               ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) |   \
2136 +                               ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) |   \
2137 +                               ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
2138 +
2139 +
2140 +/*************************************************************************
2141 + * _REG relative to RSET_TIMER
2142 + *************************************************************************/
2143 +
2144 +#define BCM63XX_TIMER_COUNT            4
2145 +#define TIMER_T0_ID                    0
2146 +#define TIMER_T1_ID                    1
2147 +#define TIMER_T2_ID                    2
2148 +#define TIMER_WDT_ID                   3
2149 +
2150 +/* Timer irqstat register */
2151 +#define TIMER_IRQSTAT_REG              0
2152 +#define TIMER_IRQSTAT_TIMER_CAUSE(x)   (1 << (x))
2153 +#define TIMER_IRQSTAT_TIMER0_CAUSE     (1 << 0)
2154 +#define TIMER_IRQSTAT_TIMER1_CAUSE     (1 << 1)
2155 +#define TIMER_IRQSTAT_TIMER2_CAUSE     (1 << 2)
2156 +#define TIMER_IRQSTAT_WDT_CAUSE                (1 << 3)
2157 +#define TIMER_IRQSTAT_TIMER_IR_EN(x)   (1 << ((x) + 8))
2158 +#define TIMER_IRQSTAT_TIMER0_IR_EN     (1 << 8)
2159 +#define TIMER_IRQSTAT_TIMER1_IR_EN     (1 << 9)
2160 +#define TIMER_IRQSTAT_TIMER2_IR_EN     (1 << 10)
2161 +
2162 +/* Timer control register */
2163 +#define TIMER_CTLx_REG(x)              (0x4 + (x * 4))
2164 +#define TIMER_CTL0_REG                 0x4
2165 +#define TIMER_CTL1_REG                 0x8
2166 +#define TIMER_CTL2_REG                 0xC
2167 +#define TIMER_CTL_COUNTDOWN_MASK       (0x3fffffff)
2168 +#define TIMER_CTL_MONOTONIC_MASK       (1 << 30)
2169 +#define TIMER_CTL_ENABLE_MASK          (1 << 31)
2170 +
2171 +
2172 +/*************************************************************************
2173 + * _REG relative to RSET_WDT
2174 + *************************************************************************/
2175 +
2176 +/* Watchdog default count register */
2177 +#define WDT_DEFVAL_REG                 0x0
2178 +
2179 +/* Watchdog control register */
2180 +#define WDT_CTL_REG                    0x4
2181 +
2182 +/* Watchdog control register constants */
2183 +#define WDT_START_1                    (0xff00)
2184 +#define WDT_START_2                    (0x00ff)
2185 +#define WDT_STOP_1                     (0xee00)
2186 +#define WDT_STOP_2                     (0x00ee)
2187 +
2188 +/* Watchdog reset length register */
2189 +#define WDT_RSTLEN_REG                 0x8
2190 +
2191 +
2192 +/*************************************************************************
2193 + * _REG relative to RSET_UARTx
2194 + *************************************************************************/
2195 +
2196 +/* UART Control Register */
2197 +#define UART_CTL_REG                   0x0
2198 +#define UART_CTL_RXTMOUTCNT_SHIFT      0
2199 +#define UART_CTL_RXTMOUTCNT_MASK       (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
2200 +#define UART_CTL_RSTTXDN_SHIFT         5
2201 +#define UART_CTL_RSTTXDN_MASK          (1 << UART_CTL_RSTTXDN_SHIFT)
2202 +#define UART_CTL_RSTRXFIFO_SHIFT               6
2203 +#define UART_CTL_RSTRXFIFO_MASK                (1 << UART_CTL_RSTRXFIFO_SHIFT)
2204 +#define UART_CTL_RSTTXFIFO_SHIFT               7
2205 +#define UART_CTL_RSTTXFIFO_MASK                (1 << UART_CTL_RSTTXFIFO_SHIFT)
2206 +#define UART_CTL_STOPBITS_SHIFT                8
2207 +#define UART_CTL_STOPBITS_MASK         (0xf << UART_CTL_STOPBITS_SHIFT)
2208 +#define UART_CTL_STOPBITS_1            (0x7 << UART_CTL_STOPBITS_SHIFT)
2209 +#define UART_CTL_STOPBITS_2            (0xf << UART_CTL_STOPBITS_SHIFT)
2210 +#define UART_CTL_BITSPERSYM_SHIFT      12
2211 +#define UART_CTL_BITSPERSYM_MASK       (0x3 << UART_CTL_BITSPERSYM_SHIFT)
2212 +#define UART_CTL_XMITBRK_SHIFT         14
2213 +#define UART_CTL_XMITBRK_MASK          (1 << UART_CTL_XMITBRK_SHIFT)
2214 +#define UART_CTL_RSVD_SHIFT            15
2215 +#define UART_CTL_RSVD_MASK             (1 << UART_CTL_RSVD_SHIFT)
2216 +#define UART_CTL_RXPAREVEN_SHIFT               16
2217 +#define UART_CTL_RXPAREVEN_MASK                (1 << UART_CTL_RXPAREVEN_SHIFT)
2218 +#define UART_CTL_RXPAREN_SHIFT         17
2219 +#define UART_CTL_RXPAREN_MASK          (1 << UART_CTL_RXPAREN_SHIFT)
2220 +#define UART_CTL_TXPAREVEN_SHIFT               18
2221 +#define UART_CTL_TXPAREVEN_MASK                (1 << UART_CTL_TXPAREVEN_SHIFT)
2222 +#define UART_CTL_TXPAREN_SHIFT         18
2223 +#define UART_CTL_TXPAREN_MASK          (1 << UART_CTL_TXPAREN_SHIFT)
2224 +#define UART_CTL_LOOPBACK_SHIFT                20
2225 +#define UART_CTL_LOOPBACK_MASK         (1 << UART_CTL_LOOPBACK_SHIFT)
2226 +#define UART_CTL_RXEN_SHIFT            21
2227 +#define UART_CTL_RXEN_MASK             (1 << UART_CTL_RXEN_SHIFT)
2228 +#define UART_CTL_TXEN_SHIFT            22
2229 +#define UART_CTL_TXEN_MASK             (1 << UART_CTL_TXEN_SHIFT)
2230 +#define UART_CTL_BRGEN_SHIFT           23
2231 +#define UART_CTL_BRGEN_MASK            (1 << UART_CTL_BRGEN_SHIFT)
2232 +
2233 +/* UART Baudword register */
2234 +#define UART_BAUD_REG                  0x4
2235 +
2236 +/* UART Misc Control register */
2237 +#define UART_MCTL_REG                  0x8
2238 +#define UART_MCTL_DTR_SHIFT            0
2239 +#define UART_MCTL_DTR_MASK             (1 << UART_MCTL_DTR_SHIFT)
2240 +#define UART_MCTL_RTS_SHIFT            1
2241 +#define UART_MCTL_RTS_MASK             (1 << UART_MCTL_RTS_SHIFT)
2242 +#define UART_MCTL_RXFIFOTHRESH_SHIFT   8
2243 +#define UART_MCTL_RXFIFOTHRESH_MASK    (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
2244 +#define UART_MCTL_TXFIFOTHRESH_SHIFT   12
2245 +#define UART_MCTL_TXFIFOTHRESH_MASK    (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
2246 +#define UART_MCTL_RXFIFOFILL_SHIFT     16
2247 +#define UART_MCTL_RXFIFOFILL_MASK      (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
2248 +#define UART_MCTL_TXFIFOFILL_SHIFT     24
2249 +#define UART_MCTL_TXFIFOFILL_MASK      (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
2250 +
2251 +/* UART External Input Configuration register */
2252 +#define UART_EXTINP_REG                        0xc
2253 +#define UART_EXTINP_RI_SHIFT           0
2254 +#define UART_EXTINP_RI_MASK            (1 << UART_EXTINP_RI_SHIFT)
2255 +#define UART_EXTINP_CTS_SHIFT          1
2256 +#define UART_EXTINP_CTS_MASK           (1 << UART_EXTINP_CTS_SHIFT)
2257 +#define UART_EXTINP_DCD_SHIFT          2
2258 +#define UART_EXTINP_DCD_MASK           (1 << UART_EXTINP_DCD_SHIFT)
2259 +#define UART_EXTINP_DSR_SHIFT          3
2260 +#define UART_EXTINP_DSR_MASK           (1 << UART_EXTINP_DSR_SHIFT)
2261 +#define UART_EXTINP_IRSTAT(x)          (1 << (x + 4))
2262 +#define UART_EXTINP_IRMASK(x)          (1 << (x + 8))
2263 +#define UART_EXTINP_IR_RI              0
2264 +#define UART_EXTINP_IR_CTS             1
2265 +#define UART_EXTINP_IR_DCD             2
2266 +#define UART_EXTINP_IR_DSR             3
2267 +#define UART_EXTINP_RI_NOSENSE_SHIFT   16
2268 +#define UART_EXTINP_RI_NOSENSE_MASK    (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
2269 +#define UART_EXTINP_CTS_NOSENSE_SHIFT  17
2270 +#define UART_EXTINP_CTS_NOSENSE_MASK   (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
2271 +#define UART_EXTINP_DCD_NOSENSE_SHIFT  18
2272 +#define UART_EXTINP_DCD_NOSENSE_MASK   (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
2273 +#define UART_EXTINP_DSR_NOSENSE_SHIFT  19
2274 +#define UART_EXTINP_DSR_NOSENSE_MASK   (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
2275 +
2276 +/* UART Interrupt register */
2277 +#define UART_IR_REG                    0x10
2278 +#define UART_IR_MASK(x)                        (1 << (x + 16))
2279 +#define UART_IR_STAT(x)                        (1 << (x))
2280 +#define UART_IR_EXTIP                  0
2281 +#define UART_IR_TXUNDER                        1
2282 +#define UART_IR_TXOVER                 2
2283 +#define UART_IR_TXTRESH                        3
2284 +#define UART_IR_TXRDLATCH              4
2285 +#define UART_IR_TXEMPTY                        5
2286 +#define UART_IR_RXUNDER                        6
2287 +#define UART_IR_RXOVER                 7
2288 +#define UART_IR_RXTIMEOUT              8
2289 +#define UART_IR_RXFULL                 9
2290 +#define UART_IR_RXTHRESH               10
2291 +#define UART_IR_RXNOTEMPTY             11
2292 +#define UART_IR_RXFRAMEERR             12
2293 +#define UART_IR_RXPARERR               13
2294 +#define UART_IR_RXBRK                  14
2295 +#define UART_IR_TXDONE                 15
2296 +
2297 +/* UART Fifo register */
2298 +#define UART_FIFO_REG                  0x14
2299 +#define UART_FIFO_VALID_SHIFT          0
2300 +#define UART_FIFO_VALID_MASK           0xff
2301 +#define UART_FIFO_FRAMEERR_SHIFT       8
2302 +#define UART_FIFO_FRAMEERR_MASK                (1 << UART_FIFO_FRAMEERR_SHIFT)
2303 +#define UART_FIFO_PARERR_SHIFT         9
2304 +#define UART_FIFO_PARERR_MASK          (1 << UART_FIFO_PARERR_SHIFT)
2305 +#define UART_FIFO_BRKDET_SHIFT         10
2306 +#define UART_FIFO_BRKDET_MASK          (1 << UART_FIFO_BRKDET_SHIFT)
2307 +#define UART_FIFO_ANYERR_MASK          (UART_FIFO_FRAMEERR_MASK |      \
2308 +                                       UART_FIFO_PARERR_MASK |         \
2309 +                                       UART_FIFO_BRKDET_MASK)
2310 +
2311 +
2312 +/*************************************************************************
2313 + * _REG relative to RSET_GPIO
2314 + *************************************************************************/
2315 +
2316 +/* GPIO registers */
2317 +#define GPIO_CTL_HI_REG                        0x0
2318 +#define GPIO_CTL_LO_REG                        0x4
2319 +#define GPIO_DATA_HI_REG               0x8
2320 +#define GPIO_DATA_LO_REG               0xC
2321 +
2322 +/* GPIO mux registers and constants */
2323 +#define GPIO_MODE_REG                  0x18
2324 +
2325 +#define GPIO_MODE_6348_G4_DIAG         0x00090000
2326 +#define GPIO_MODE_6348_G4_UTOPIA       0x00080000
2327 +#define GPIO_MODE_6348_G4_LEGACY_LED   0x00030000
2328 +#define GPIO_MODE_6348_G4_MII_SNOOP    0x00020000
2329 +#define GPIO_MODE_6348_G4_EXT_EPHY     0x00010000
2330 +#define GPIO_MODE_6348_G3_DIAG         0x00009000
2331 +#define GPIO_MODE_6348_G3_UTOPIA       0x00008000
2332 +#define GPIO_MODE_6348_G3_EXT_MII      0x00007000
2333 +#define GPIO_MODE_6348_G2_DIAG         0x00000900
2334 +#define GPIO_MODE_6348_G2_PCI          0x00000500
2335 +#define GPIO_MODE_6348_G1_DIAG         0x00000090
2336 +#define GPIO_MODE_6348_G1_UTOPIA       0x00000080
2337 +#define GPIO_MODE_6348_G1_SPI_UART     0x00000060
2338 +#define GPIO_MODE_6348_G1_SPI_MASTER   0x00000060
2339 +#define GPIO_MODE_6348_G1_MII_PCCARD   0x00000040
2340 +#define GPIO_MODE_6348_G1_MII_SNOOP    0x00000020
2341 +#define GPIO_MODE_6348_G1_EXT_EPHY     0x00000010
2342 +#define GPIO_MODE_6348_G0_DIAG         0x00000009
2343 +#define GPIO_MODE_6348_G0_EXT_MII      0x00000007
2344 +
2345 +#define GPIO_MODE_6358_EXTRACS         (1 << 5)
2346 +#define GPIO_MODE_6358_UART1           (1 << 6)
2347 +#define GPIO_MODE_6358_EXTRA_SPI_SS    (1 << 7)
2348 +#define GPIO_MODE_6358_SERIAL_LED      (1 << 10)
2349 +#define GPIO_MODE_6358_UTOPIA          (1 << 12)
2350 +
2351 +
2352 +/*************************************************************************
2353 + * _REG relative to RSET_ENET
2354 + *************************************************************************/
2355 +
2356 +/* Receiver Configuration register */
2357 +#define ENET_RXCFG_REG                 0x0
2358 +#define ENET_RXCFG_ALLMCAST_SHIFT      1
2359 +#define ENET_RXCFG_ALLMCAST_MASK       (1 << ENET_RXCFG_ALLMCAST_SHIFT)
2360 +#define ENET_RXCFG_PROMISC_SHIFT       3
2361 +#define ENET_RXCFG_PROMISC_MASK                (1 << ENET_RXCFG_PROMISC_SHIFT)
2362 +#define ENET_RXCFG_LOOPBACK_SHIFT      4
2363 +#define ENET_RXCFG_LOOPBACK_MASK       (1 << ENET_RXCFG_LOOPBACK_SHIFT)
2364 +#define ENET_RXCFG_ENFLOW_SHIFT                5
2365 +#define ENET_RXCFG_ENFLOW_MASK         (1 << ENET_RXCFG_ENFLOW_SHIFT)
2366 +
2367 +/* Receive Maximum Length register */
2368 +#define ENET_RXMAXLEN_REG              0x4
2369 +#define ENET_RXMAXLEN_SHIFT            0
2370 +#define ENET_RXMAXLEN_MASK             (0x7ff << ENET_RXMAXLEN_SHIFT)
2371 +
2372 +/* Transmit Maximum Length register */
2373 +#define ENET_TXMAXLEN_REG              0x8
2374 +#define ENET_TXMAXLEN_SHIFT            0
2375 +#define ENET_TXMAXLEN_MASK             (0x7ff << ENET_TXMAXLEN_SHIFT)
2376 +
2377 +/* MII Status/Control register */
2378 +#define ENET_MIISC_REG                 0x10
2379 +#define ENET_MIISC_MDCFREQDIV_SHIFT    0
2380 +#define ENET_MIISC_MDCFREQDIV_MASK     (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
2381 +#define ENET_MIISC_PREAMBLEEN_SHIFT    7
2382 +#define ENET_MIISC_PREAMBLEEN_MASK     (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
2383 +
2384 +/* MII Data register */
2385 +#define ENET_MIIDATA_REG               0x14
2386 +#define ENET_MIIDATA_DATA_SHIFT                0
2387 +#define ENET_MIIDATA_DATA_MASK         (0xffff << ENET_MIIDATA_DATA_SHIFT)
2388 +#define ENET_MIIDATA_TA_SHIFT          16
2389 +#define ENET_MIIDATA_TA_MASK           (0x3 << ENET_MIIDATA_TA_SHIFT)
2390 +#define ENET_MIIDATA_REG_SHIFT         18
2391 +#define ENET_MIIDATA_REG_MASK          (0x1f << ENET_MIIDATA_REG_SHIFT)
2392 +#define ENET_MIIDATA_PHYID_SHIFT       23
2393 +#define ENET_MIIDATA_PHYID_MASK                (0x1f << ENET_MIIDATA_PHYID_SHIFT)
2394 +#define ENET_MIIDATA_OP_READ_MASK      (0x6 << 28)
2395 +#define ENET_MIIDATA_OP_WRITE_MASK     (0x5 << 28)
2396 +
2397 +/* Ethernet Interrupt Mask register */
2398 +#define ENET_IRMASK_REG                        0x18
2399 +
2400 +/* Ethernet Interrupt register */
2401 +#define ENET_IR_REG                    0x1c
2402 +#define ENET_IR_MII                    (1 << 0)
2403 +#define ENET_IR_MIB                    (1 << 1)
2404 +#define ENET_IR_FLOWC                  (1 << 2)
2405 +
2406 +/* Ethernet Control register */
2407 +#define ENET_CTL_REG                   0x2c
2408 +#define ENET_CTL_ENABLE_SHIFT          0
2409 +#define ENET_CTL_ENABLE_MASK           (1 << ENET_CTL_ENABLE_SHIFT)
2410 +#define ENET_CTL_DISABLE_SHIFT         1
2411 +#define ENET_CTL_DISABLE_MASK          (1 << ENET_CTL_DISABLE_SHIFT)
2412 +#define ENET_CTL_SRESET_SHIFT          2
2413 +#define ENET_CTL_SRESET_MASK           (1 << ENET_CTL_SRESET_SHIFT)
2414 +#define ENET_CTL_EPHYSEL_SHIFT         3
2415 +#define ENET_CTL_EPHYSEL_MASK          (1 << ENET_CTL_EPHYSEL_SHIFT)
2416 +
2417 +/* Transmit Control register */
2418 +#define ENET_TXCTL_REG                 0x30
2419 +#define ENET_TXCTL_FD_SHIFT            0
2420 +#define ENET_TXCTL_FD_MASK             (1 << ENET_TXCTL_FD_SHIFT)
2421 +
2422 +/* Transmit Watermask register */
2423 +#define ENET_TXWMARK_REG               0x34
2424 +#define ENET_TXWMARK_WM_SHIFT          0
2425 +#define ENET_TXWMARK_WM_MASK           (0x3f << ENET_TXWMARK_WM_SHIFT)
2426 +
2427 +/* MIB Control register */
2428 +#define ENET_MIBCTL_REG                        0x38
2429 +#define ENET_MIBCTL_RDCLEAR_SHIFT      0
2430 +#define ENET_MIBCTL_RDCLEAR_MASK       (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
2431 +
2432 +/* Perfect Match Data Low register */
2433 +#define ENET_PML_REG(x)                        (0x58 + (x) * 8)
2434 +#define ENET_PMH_REG(x)                        (0x5c + (x) * 8)
2435 +#define ENET_PMH_DATAVALID_SHIFT       16
2436 +#define ENET_PMH_DATAVALID_MASK                (1 << ENET_PMH_DATAVALID_SHIFT)
2437 +
2438 +/* MIB register */
2439 +#define ENET_MIB_REG(x)                        (0x200 + (x) * 4)
2440 +#define ENET_MIB_REG_COUNT             55
2441 +
2442 +
2443 +/*************************************************************************
2444 + * _REG relative to RSET_ENETDMA
2445 + *************************************************************************/
2446 +
2447 +/* Controller Configuration Register */
2448 +#define ENETDMA_CFG_REG                        (0x0)
2449 +#define ENETDMA_CFG_EN_SHIFT           0
2450 +#define ENETDMA_CFG_EN_MASK            (1 << ENETDMA_CFG_EN_SHIFT)
2451 +#define ENETDMA_CFG_FLOWCH_MASK(x)     (1 << ((x >> 1) + 1))
2452 +
2453 +/* Flow Control Descriptor Low Threshold register */
2454 +#define ENETDMA_FLOWCL_REG(x)          (0x4 + (x) * 6)
2455 +
2456 +/* Flow Control Descriptor High Threshold register */
2457 +#define ENETDMA_FLOWCH_REG(x)          (0x8 + (x) * 6)
2458 +
2459 +/* Flow Control Descriptor Buffer Alloca Threshold register */
2460 +#define ENETDMA_BUFALLOC_REG(x)                (0xc + (x) * 6)
2461 +#define ENETDMA_BUFALLOC_FORCE_SHIFT   31
2462 +#define ENETDMA_BUFALLOC_FORCE_MASK    (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
2463 +
2464 +/* Channel Configuration register */
2465 +#define ENETDMA_CHANCFG_REG(x)         (0x100 + (x) * 0x10)
2466 +#define ENETDMA_CHANCFG_EN_SHIFT       0
2467 +#define ENETDMA_CHANCFG_EN_MASK                (1 << ENETDMA_CHANCFG_EN_SHIFT)
2468 +#define ENETDMA_CHANCFG_PKTHALT_SHIFT  1
2469 +#define ENETDMA_CHANCFG_PKTHALT_MASK   (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
2470 +
2471 +/* Interrupt Control/Status register */
2472 +#define ENETDMA_IR_REG(x)              (0x104 + (x) * 0x10)
2473 +#define ENETDMA_IR_BUFDONE_MASK                (1 << 0)
2474 +#define ENETDMA_IR_PKTDONE_MASK                (1 << 1)
2475 +#define ENETDMA_IR_NOTOWNER_MASK       (1 << 2)
2476 +
2477 +/* Interrupt Mask register */
2478 +#define ENETDMA_IRMASK_REG(x)          (0x108 + (x) * 0x10)
2479 +
2480 +/* Maximum Burst Length */
2481 +#define ENETDMA_MAXBURST_REG(x)                (0x10C + (x) * 0x10)
2482 +
2483 +/* Ring Start Address register */
2484 +#define ENETDMA_RSTART_REG(x)          (0x200 + (x) * 0x10)
2485 +
2486 +/* State Ram Word 2 */
2487 +#define ENETDMA_SRAM2_REG(x)           (0x204 + (x) * 0x10)
2488 +
2489 +/* State Ram Word 3 */
2490 +#define ENETDMA_SRAM3_REG(x)           (0x208 + (x) * 0x10)
2491 +
2492 +/* State Ram Word 4 */
2493 +#define ENETDMA_SRAM4_REG(x)           (0x20c + (x) * 0x10)
2494 +
2495 +
2496 +/*************************************************************************
2497 + * _REG relative to RSET_OHCI_PRIV
2498 + *************************************************************************/
2499 +
2500 +#define OHCI_PRIV_REG                  0x0
2501 +#define OHCI_PRIV_PORT1_HOST_SHIFT     0
2502 +#define OHCI_PRIV_PORT1_HOST_MASK      (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
2503 +#define OHCI_PRIV_REG_SWAP_SHIFT       3
2504 +#define OHCI_PRIV_REG_SWAP_MASK                (1 << OHCI_PRIV_REG_SWAP_SHIFT)
2505 +
2506 +
2507 +/*************************************************************************
2508 + * _REG relative to RSET_USBH_PRIV
2509 + *************************************************************************/
2510 +
2511 +#define USBH_PRIV_SWAP_REG             0x0
2512 +#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
2513 +#define USBH_PRIV_SWAP_EHCI_ENDN_MASK  (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
2514 +#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
2515 +#define USBH_PRIV_SWAP_EHCI_DATA_MASK  (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
2516 +#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
2517 +#define USBH_PRIV_SWAP_OHCI_ENDN_MASK  (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
2518 +#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
2519 +#define USBH_PRIV_SWAP_OHCI_DATA_MASK  (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
2520 +
2521 +#define USBH_PRIV_TEST_REG             0x24
2522 +
2523 +
2524 +/*************************************************************************
2525 + * _REG relative to RSET_MPI
2526 + *************************************************************************/
2527 +
2528 +/* well known (hard wired) chip select */
2529 +#define MPI_CS_PCMCIA_COMMON           4
2530 +#define MPI_CS_PCMCIA_ATTR             5
2531 +#define MPI_CS_PCMCIA_IO               6
2532 +
2533 +/* Chip select base register */
2534 +#define MPI_CSBASE_REG(x)              (0x0 + (x) * 8)
2535 +#define MPI_CSBASE_BASE_SHIFT          13
2536 +#define MPI_CSBASE_BASE_MASK           (0x1ffff << MPI_CSBASE_BASE_SHIFT)
2537 +#define MPI_CSBASE_SIZE_SHIFT          0
2538 +#define MPI_CSBASE_SIZE_MASK           (0xf << MPI_CSBASE_SIZE_SHIFT)
2539 +
2540 +#define MPI_CSBASE_SIZE_8K             0
2541 +#define MPI_CSBASE_SIZE_16K            1
2542 +#define MPI_CSBASE_SIZE_32K            2
2543 +#define MPI_CSBASE_SIZE_64K            3
2544 +#define MPI_CSBASE_SIZE_128K           4
2545 +#define MPI_CSBASE_SIZE_256K           5
2546 +#define MPI_CSBASE_SIZE_512K           6
2547 +#define MPI_CSBASE_SIZE_1M             7
2548 +#define MPI_CSBASE_SIZE_2M             8
2549 +#define MPI_CSBASE_SIZE_4M             9
2550 +#define MPI_CSBASE_SIZE_8M             10
2551 +#define MPI_CSBASE_SIZE_16M            11
2552 +#define MPI_CSBASE_SIZE_32M            12
2553 +#define MPI_CSBASE_SIZE_64M            13
2554 +#define MPI_CSBASE_SIZE_128M           14
2555 +#define MPI_CSBASE_SIZE_256M           15
2556 +
2557 +/* Chip select control register */
2558 +#define MPI_CSCTL_REG(x)               (0x4 + (x) * 8)
2559 +#define MPI_CSCTL_ENABLE_MASK          (1 << 0)
2560 +#define MPI_CSCTL_WAIT_SHIFT           1
2561 +#define MPI_CSCTL_WAIT_MASK            (0x7 << MPI_CSCTL_WAIT_SHIFT)
2562 +#define MPI_CSCTL_DATA16_MASK          (1 << 4)
2563 +#define MPI_CSCTL_SYNCMODE_MASK                (1 << 7)
2564 +#define MPI_CSCTL_TSIZE_MASK           (1 << 8)
2565 +#define MPI_CSCTL_ENDIANSWAP_MASK      (1 << 10)
2566 +#define MPI_CSCTL_SETUP_SHIFT          16
2567 +#define MPI_CSCTL_SETUP_MASK           (0xf << MPI_CSCTL_SETUP_SHIFT)
2568 +#define MPI_CSCTL_HOLD_SHIFT           20
2569 +#define MPI_CSCTL_HOLD_MASK            (0xf << MPI_CSCTL_HOLD_SHIFT)
2570 +
2571 +/* PCI registers */
2572 +#define MPI_SP0_RANGE_REG              0x100
2573 +#define MPI_SP0_REMAP_REG              0x104
2574 +#define MPI_SP0_REMAP_ENABLE_MASK      (1 << 0)
2575 +#define MPI_SP1_RANGE_REG              0x10C
2576 +#define MPI_SP1_REMAP_REG              0x110
2577 +#define MPI_SP1_REMAP_ENABLE_MASK      (1 << 0)
2578 +
2579 +#define MPI_L2PCFG_REG                 0x11C
2580 +#define MPI_L2PCFG_CFG_TYPE_SHIFT      0
2581 +#define MPI_L2PCFG_CFG_TYPE_MASK       (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
2582 +#define MPI_L2PCFG_REG_SHIFT           2
2583 +#define MPI_L2PCFG_REG_MASK            (0x3f << MPI_L2PCFG_REG_SHIFT)
2584 +#define MPI_L2PCFG_FUNC_SHIFT          8
2585 +#define MPI_L2PCFG_FUNC_MASK           (0x7 << MPI_L2PCFG_FUNC_SHIFT)
2586 +#define MPI_L2PCFG_DEVNUM_SHIFT                11
2587 +#define MPI_L2PCFG_DEVNUM_MASK         (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
2588 +#define MPI_L2PCFG_CFG_USEREG_MASK     (1 << 30)
2589 +#define MPI_L2PCFG_CFG_SEL_MASK                (1 << 31)
2590 +
2591 +#define MPI_L2PMEMRANGE1_REG           0x120
2592 +#define MPI_L2PMEMBASE1_REG            0x124
2593 +#define MPI_L2PMEMREMAP1_REG           0x128
2594 +#define MPI_L2PMEMRANGE2_REG           0x12C
2595 +#define MPI_L2PMEMBASE2_REG            0x130
2596 +#define MPI_L2PMEMREMAP2_REG           0x134
2597 +#define MPI_L2PIORANGE_REG             0x138
2598 +#define MPI_L2PIOBASE_REG              0x13C
2599 +#define MPI_L2PIOREMAP_REG             0x140
2600 +#define MPI_L2P_BASE_MASK              (0xffff8000)
2601 +#define MPI_L2PREMAP_ENABLED_MASK      (1 << 0)
2602 +#define MPI_L2PREMAP_IS_CARDBUS_MASK   (1 << 2)
2603 +
2604 +#define MPI_PCIMODESEL_REG             0x144
2605 +#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK        (1 << 0)
2606 +#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK        (1 << 1)
2607 +#define MPI_PCIMODESEL_EXT_ARB_MASK    (1 << 2)
2608 +#define MPI_PCIMODESEL_PREFETCH_SHIFT  4
2609 +#define MPI_PCIMODESEL_PREFETCH_MASK   (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
2610 +
2611 +#define MPI_LOCBUSCTL_REG              0x14C
2612 +#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
2613 +#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK  (1 << 1)
2614 +
2615 +#define MPI_LOCINT_REG                 0x150
2616 +#define MPI_LOCINT_MASK(x)             (1 << (x + 16))
2617 +#define MPI_LOCINT_STAT(x)             (1 << (x))
2618 +#define MPI_LOCINT_DIR_FAILED          6
2619 +#define MPI_LOCINT_EXT_PCI_INT         7
2620 +#define MPI_LOCINT_SERR                        8
2621 +#define MPI_LOCINT_CSERR               9
2622 +
2623 +#define MPI_PCICFGCTL_REG              0x178
2624 +#define MPI_PCICFGCTL_CFGADDR_SHIFT    2
2625 +#define MPI_PCICFGCTL_CFGADDR_MASK     (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
2626 +#define MPI_PCICFGCTL_WRITEEN_MASK     (1 << 7)
2627 +
2628 +#define MPI_PCICFGDATA_REG             0x17C
2629 +
2630 +/* PCI host bridge custom register */
2631 +#define BCMPCI_REG_TIMERS              0x40
2632 +#define REG_TIMER_TRDY_SHIFT           0
2633 +#define REG_TIMER_TRDY_MASK            (0xff << REG_TIMER_TRDY_SHIFT)
2634 +#define REG_TIMER_RETRY_SHIFT          8
2635 +#define REG_TIMER_RETRY_MASK           (0xff << REG_TIMER_RETRY_SHIFT)
2636 +
2637 +
2638 +/*************************************************************************
2639 + * _REG relative to RSET_PCMCIA
2640 + *************************************************************************/
2641 +
2642 +#define PCMCIA_C1_REG                  0x0
2643 +#define PCMCIA_C1_CD1_MASK             (1 << 0)
2644 +#define PCMCIA_C1_CD2_MASK             (1 << 1)
2645 +#define PCMCIA_C1_VS1_MASK             (1 << 2)
2646 +#define PCMCIA_C1_VS2_MASK             (1 << 3)
2647 +#define PCMCIA_C1_VS1OE_MASK           (1 << 6)
2648 +#define PCMCIA_C1_VS2OE_MASK           (1 << 7)
2649 +#define PCMCIA_C1_CBIDSEL_SHIFT                (8)
2650 +#define PCMCIA_C1_CBIDSEL_MASK         (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
2651 +#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK  (1 << 13)
2652 +#define PCMCIA_C1_EN_PCMCIA_MASK       (1 << 14)
2653 +#define PCMCIA_C1_EN_CARDBUS_MASK      (1 << 15)
2654 +#define PCMCIA_C1_RESET_MASK           (1 << 18)
2655 +
2656 +#define PCMCIA_C2_REG                  0x8
2657 +#define PCMCIA_C2_DATA16_MASK          (1 << 0)
2658 +#define PCMCIA_C2_BYTESWAP_MASK                (1 << 1)
2659 +#define PCMCIA_C2_RWCOUNT_SHIFT                2
2660 +#define PCMCIA_C2_RWCOUNT_MASK         (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
2661 +#define PCMCIA_C2_INACTIVE_SHIFT       8
2662 +#define PCMCIA_C2_INACTIVE_MASK                (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
2663 +#define PCMCIA_C2_SETUP_SHIFT          16
2664 +#define PCMCIA_C2_SETUP_MASK           (0x3f << PCMCIA_C2_SETUP_SHIFT)
2665 +#define PCMCIA_C2_HOLD_SHIFT           24
2666 +#define PCMCIA_C2_HOLD_MASK            (0x3f << PCMCIA_C2_HOLD_SHIFT)
2667 +
2668 +
2669 +/*************************************************************************
2670 + * _REG relative to RSET_SDRAM
2671 + *************************************************************************/
2672 +
2673 +#define SDRAM_CFG_REG                  0x0
2674 +#define SDRAM_CFG_ROW_SHIFT            4
2675 +#define SDRAM_CFG_ROW_MASK             (0x3 << SDRAM_CFG_ROW_SHIFT)
2676 +#define SDRAM_CFG_COL_SHIFT            6
2677 +#define SDRAM_CFG_COL_MASK             (0x3 << SDRAM_CFG_COL_SHIFT)
2678 +#define SDRAM_CFG_32B_SHIFT            10
2679 +#define SDRAM_CFG_32B_MASK             (1 << SDRAM_CFG_32B_SHIFT)
2680 +#define SDRAM_CFG_BANK_SHIFT           13
2681 +#define SDRAM_CFG_BANK_MASK            (1 << SDRAM_CFG_BANK_SHIFT)
2682 +
2683 +#define SDRAM_PRIO_REG                 0x2C
2684 +#define SDRAM_PRIO_MIPS_SHIFT          29
2685 +#define SDRAM_PRIO_MIPS_MASK           (1 << SDRAM_PRIO_MIPS_SHIFT)
2686 +#define SDRAM_PRIO_ADSL_SHIFT          30
2687 +#define SDRAM_PRIO_ADSL_MASK           (1 << SDRAM_PRIO_ADSL_SHIFT)
2688 +#define SDRAM_PRIO_EN_SHIFT            31
2689 +#define SDRAM_PRIO_EN_MASK             (1 << SDRAM_PRIO_EN_SHIFT)
2690 +
2691 +
2692 +/*************************************************************************
2693 + * _REG relative to RSET_MEMC
2694 + *************************************************************************/
2695 +
2696 +#define MEMC_CFG_REG                   0x4
2697 +#define MEMC_CFG_32B_SHIFT             1
2698 +#define MEMC_CFG_32B_MASK              (1 << MEMC_CFG_32B_SHIFT)
2699 +#define MEMC_CFG_COL_SHIFT             3
2700 +#define MEMC_CFG_COL_MASK              (0x3 << MEMC_CFG_COL_SHIFT)
2701 +#define MEMC_CFG_ROW_SHIFT             6
2702 +#define MEMC_CFG_ROW_MASK              (0x3 << MEMC_CFG_ROW_SHIFT)
2703 +
2704 +
2705 +/*************************************************************************
2706 + * _REG relative to RSET_DDR
2707 + *************************************************************************/
2708 +
2709 +#define DDR_DMIPSPLLCFG_REG            0x18
2710 +#define DMIPSPLLCFG_M1_SHIFT           0
2711 +#define DMIPSPLLCFG_M1_MASK            (0xff << DMIPSPLLCFG_M1_SHIFT)
2712 +#define DMIPSPLLCFG_N1_SHIFT           23
2713 +#define DMIPSPLLCFG_N1_MASK            (0x3f << DMIPSPLLCFG_N1_SHIFT)
2714 +#define DMIPSPLLCFG_N2_SHIFT           29
2715 +#define DMIPSPLLCFG_N2_MASK            (0x7 << DMIPSPLLCFG_N2_SHIFT)
2716 +
2717 +#endif /* BCM63XX_REGS_H_ */
2718 +
2719 --- /dev/null
2720 +++ b/include/asm-mips/mach-bcm63xx/bcm63xx_timer.h
2721 @@ -0,0 +1,11 @@
2722 +#ifndef BCM63XX_TIMER_H_
2723 +#define BCM63XX_TIMER_H_
2724 +
2725 +int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data);
2726 +void bcm63xx_timer_unregister(int id);
2727 +int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us);
2728 +int bcm63xx_timer_enable(int id);
2729 +int bcm63xx_timer_disable(int id);
2730 +unsigned int bcm63xx_timer_countdown(unsigned int countdown_us);
2731 +
2732 +#endif /* !BCM63XX_TIMER_H_ */
2733 --- /dev/null
2734 +++ b/include/asm-mips/mach-bcm63xx/cpu-feature-overrides.h
2735 @@ -0,0 +1,51 @@
2736 +#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
2737 +#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H
2738 +
2739 +#include <bcm63xx_cpu.h>
2740 +
2741 +#define cpu_has_tlb                    1
2742 +#define cpu_has_4kex                   1
2743 +#define cpu_has_4k_cache               1
2744 +#define cpu_has_fpu                    0
2745 +#define cpu_has_32fpr                  0
2746 +#define cpu_has_counter                        1
2747 +#define cpu_has_watch                  0
2748 +#define cpu_has_divec                  1
2749 +#define cpu_has_vce                    0
2750 +#define cpu_has_cache_cdex_p           0
2751 +#define cpu_has_cache_cdex_s           0
2752 +#define cpu_has_prefetch               1
2753 +#define cpu_has_mcheck                 1
2754 +#define cpu_has_ejtag                  1
2755 +#define cpu_has_llsc                   1
2756 +#define cpu_has_mips16                 0
2757 +#define cpu_has_mdmx                   0
2758 +#define cpu_has_mips3d                 0
2759 +#define cpu_has_smartmips              0
2760 +#define cpu_has_vtag_icache            0
2761 +
2762 +#if !defined(BCMCPU_RUNTIME_DETECT) && defined(CONFIG_BCMCPU_IS_6348)
2763 +#define cpu_has_dc_aliases             0
2764 +#endif
2765 +
2766 +#define cpu_has_ic_fills_f_dc          0
2767 +#define cpu_has_pindexed_dcache                0
2768 +
2769 +#define cpu_has_mips32r1               1
2770 +#define cpu_has_mips32r2               0
2771 +#define cpu_has_mips64r1               0
2772 +#define cpu_has_mips64r2               0
2773 +
2774 +#define cpu_has_dsp                    0
2775 +#define cpu_has_mipsmt                 0
2776 +#define cpu_has_userlocal              0
2777 +
2778 +#define cpu_has_nofpuex                        0
2779 +#define cpu_has_64bits                 0
2780 +#define cpu_has_64bit_zero_reg         0
2781 +
2782 +#define cpu_dcache_line_size()         16
2783 +#define cpu_icache_line_size()         16
2784 +#define cpu_scache_line_size()         0
2785 +
2786 +#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */
2787 --- /dev/null
2788 +++ b/include/asm-mips/mach-bcm63xx/gpio.h
2789 @@ -0,0 +1,52 @@
2790 +#ifndef __ASM_MIPS_MACH_BCM63XX_GPIO_H
2791 +#define __ASM_MIPS_MACH_BCM63XX_GPIO_H
2792 +
2793 +#include <bcm63xx_gpio.h>
2794 +
2795 +static inline int gpio_is_valid(int number)
2796 +{
2797 +       return (number >= BCM63XX_GPIO_COUNT) ? 0 : 1;
2798 +}
2799 +
2800 +static inline int gpio_request(unsigned gpio, const char *label)
2801 +{
2802 +       return 0;
2803 +}
2804 +
2805 +static inline void gpio_free(unsigned gpio)
2806 +{
2807 +}
2808 +
2809 +static inline int gpio_direction_input(unsigned gpio)
2810 +{
2811 +       bcm63xx_gpio_set_direction(gpio, GPIO_DIR_IN);
2812 +       return 0;
2813 +}
2814 +
2815 +static inline int gpio_direction_output(unsigned gpio, int value)
2816 +{
2817 +       bcm63xx_gpio_set_direction(gpio, GPIO_DIR_OUT);
2818 +       return 0;
2819 +}
2820 +
2821 +static inline int gpio_get_value(unsigned gpio)
2822 +{
2823 +       return bcm63xx_gpio_get_datain(gpio);
2824 +}
2825 +
2826 +static inline void gpio_set_value(unsigned gpio, int value)
2827 +{
2828 +       bcm63xx_gpio_set_dataout(gpio, value);
2829 +}
2830 +
2831 +static inline int gpio_to_irq(unsigned gpio)
2832 +{
2833 +       return gpio;
2834 +}
2835 +
2836 +static inline int irq_to_gpio(unsigned irq)
2837 +{
2838 +       return irq;
2839 +}
2840 +
2841 +#endif /* __ASM_MIPS_MACH_BCM63XX_GPIO_H */
2842 --- /dev/null
2843 +++ b/include/asm-mips/mach-bcm63xx/war.h
2844 @@ -0,0 +1,25 @@
2845 +/*
2846 + * This file is subject to the terms and conditions of the GNU General Public
2847 + * License.  See the file "COPYING" in the main directory of this archive
2848 + * for more details.
2849 + *
2850 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
2851 + */
2852 +#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H
2853 +#define __ASM_MIPS_MACH_BCM63XX_WAR_H
2854 +
2855 +#define R4600_V1_INDEX_ICACHEOP_WAR    0
2856 +#define R4600_V1_HIT_CACHEOP_WAR       0
2857 +#define R4600_V2_HIT_CACHEOP_WAR       0
2858 +#define R5432_CP0_INTERRUPT_WAR                0
2859 +#define BCM1250_M3_WAR                 0
2860 +#define SIBYTE_1956_WAR                        0
2861 +#define MIPS4K_ICACHE_REFILL_WAR       0
2862 +#define MIPS_CACHE_SYNC_WAR            0
2863 +#define TX49XX_ICACHE_INDEX_INV_WAR    0
2864 +#define RM9000_CDEX_SMP_WAR            0
2865 +#define ICACHE_REFILLS_WORKAROUND_WAR  0
2866 +#define R10000_LLSC_WAR                        0
2867 +#define MIPS34K_MISSED_ITLB_WAR                0
2868 +
2869 +#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */