target/linux/brcm47xx/patches-2.6.28/700-ssb-gigabit-ethernet-driver.patch

   1 --- a/drivers/net/tg3.c
   2 +++ b/drivers/net/tg3.c
   3 @@ -40,6 +40,7 @@
   4  #include <linux/workqueue.h>
   5  #include <linux/prefetch.h>
   6  #include <linux/dma-mapping.h>
   7 +#include <linux/ssb/ssb_driver_gige.h>
   8
   9  #include <net/checksum.h>
  10  #include <net/ip.h>
  11 @@ -428,8 +429,9 @@ static void _tw32_flush(struct tg3 *tp,
  12  static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  13  {
  14         tp->write32_mbox(tp, off, val);
  15 -       if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  16 -           !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  17 +       if ((tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) ||
  18 +           (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  19 +            !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)))
  20                 tp->read32_mbox(tp, off);
  21  }
  22
  23 @@ -439,7 +441,7 @@ static void tg3_write32_tx_mbox(struct t
  24         writel(val, mbox);
  25         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  26                 writel(val, mbox);
  27 -       if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  28 +       if ((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES))
  29                 readl(mbox);
  30  }
  31
  32 @@ -711,7 +713,7 @@ static void tg3_switch_clocks(struct tg3
  33
  34  #define PHY_BUSY_LOOPS 5000
  35
  36 -static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  37 +static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 *val)
  38  {
  39         u32 frame_val;
  40         unsigned int loops;
  41 @@ -725,7 +727,7 @@ static int tg3_readphy(struct tg3 *tp, i
  42
  43         *val = 0x0;
  44
  45 -       frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  46 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  47                       MI_COM_PHY_ADDR_MASK);
  48         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  49                       MI_COM_REG_ADDR_MASK);
  50 @@ -760,7 +762,12 @@ static int tg3_readphy(struct tg3 *tp, i
  51         return ret;
  52  }
  53
  54 -static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  55 +static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  56 +{
  57 +       return __tg3_readphy(tp, PHY_ADDR, reg, val);
  58 +}
  59 +
  60 +static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, u32 val)
  61  {
  62         u32 frame_val;
  63         unsigned int loops;
  64 @@ -776,7 +783,7 @@ static int tg3_writephy(struct tg3 *tp,
  65                 udelay(80);
  66         }
  67
  68 -       frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  69 +       frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  70                       MI_COM_PHY_ADDR_MASK);
  71         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  72                       MI_COM_REG_ADDR_MASK);
  73 @@ -809,6 +816,11 @@ static int tg3_writephy(struct tg3 *tp,
  74         return ret;
  75  }
  76
  77 +static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  78 +{
  79 +       return __tg3_writephy(tp, PHY_ADDR, reg, val);
  80 +}
  81 +
  82  static int tg3_bmcr_reset(struct tg3 *tp)
  83  {
  84         u32 phy_control;
  85 @@ -2232,8 +2244,10 @@ static int tg3_set_power_state(struct tg
  86         tg3_frob_aux_power(tp);
  87
  88         /* Workaround for unstable PLL clock */
  89 -       if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  90 -           (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  91 +       if ((tp->phy_id & PHY_ID_MASK != PHY_ID_BCM5750_2) &&
  92 +                               /* !!! FIXME !!! */
  93 +           ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  94 +           (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) {
  95                 u32 val = tr32(0x7d00);
  96
  97                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  98 @@ -2725,6 +2739,14 @@ relink:
  99
 100                 tg3_phy_copper_begin(tp);
 101
 102 +               if (tp->tg3_flags3 & TG3_FLG3_ROBOSWITCH) {
 103 +                       current_link_up = 1;
 104 +                       current_speed = SPEED_1000; //FIXME
 105 +                       current_duplex = DUPLEX_FULL;
 106 +                       tp->link_config.active_speed = current_speed;
 107 +                       tp->link_config.active_duplex = current_duplex;
 108 +               }
 109 +
 110                 tg3_readphy(tp, MII_BMSR, &tmp);
 111                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
 112                     (tmp & BMSR_LSTATUS))
 113 @@ -5659,6 +5681,11 @@ static int tg3_poll_fw(struct tg3 *tp)
 114         int i;
 115         u32 val;
 116
 117 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 118 +               /* We don't use firmware. */
 119 +               return 0;
 120 +       }
 121 +
 122         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 123                 /* Wait up to 20ms for init done. */
 124                 for (i = 0; i < 200; i++) {
 125 @@ -5902,6 +5929,14 @@ static int tg3_chip_reset(struct tg3 *tp
 126                 tw32(0x5000, 0x400);
 127         }
 128
 129 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 130 +               /* BCM4785: In order to avoid repercussions from using potentially
 131 +                * defective internal ROM, stop the Rx RISC CPU, which is not
 132 +                * required. */
 133 +               tg3_stop_fw(tp);
 134 +               tg3_halt_cpu(tp, RX_CPU_BASE);
 135 +       }
 136 +
 137         tw32(GRC_MODE, tp->grc_mode);
 138
 139         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
 140 @@ -6176,9 +6211,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
 141                 return -ENODEV;
 142         }
 143
 144 -       /* Clear firmware's nvram arbitration. */
 145 -       if (tp->tg3_flags & TG3_FLAG_NVRAM)
 146 -               tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
 147 +       if (!(tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)) {
 148 +               /* Clear firmware's nvram arbitration. */
 149 +               if (tp->tg3_flags & TG3_FLAG_NVRAM)
 150 +                       tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
 151 +       }
 152 +
 153         return 0;
 154  }
 155
 156 @@ -6259,6 +6297,11 @@ static int tg3_load_5701_a0_firmware_fix
 157         struct fw_info info;
 158         int err, i;
 159
 160 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 161 +               /* We don't use firmware. */
 162 +               return 0;
 163 +       }
 164 +
 165         info.text_base = TG3_FW_TEXT_ADDR;
 166         info.text_len = TG3_FW_TEXT_LEN;
 167         info.text_data = &tg3FwText[0];
 168 @@ -6817,6 +6860,11 @@ static int tg3_load_tso_firmware(struct
 169         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
 170         int err, i;
 171
 172 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 173 +               /* We don't use firmware. */
 174 +               return 0;
 175 +       }
 176 +
 177         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
 178                 return 0;
 179
 180 @@ -7776,6 +7824,11 @@ static void tg3_timer(unsigned long __op
 181
 182         spin_lock(&tp->lock);
 183
 184 +       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
 185 +               /* BCM4785: Flush posted writes from GbE to host memory. */
 186 +               tr32(HOSTCC_MODE);
 187 +       }
 188 +
 189         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
 190                 /* All of this garbage is because when using non-tagged
 191                  * IRQ status the mailbox/status_block protocol the chip
 192 @@ -9469,6 +9522,11 @@ static int tg3_test_nvram(struct tg3 *tp
 193         __le32 *buf;
 194         int i, j, k, err = 0, size;
 195
 196 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 197 +               /* We don't have NVRAM. */
 198 +               return 0;
 199 +       }
 200 +
 201         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
 202                 return -EIO;
 203
 204 @@ -10262,7 +10320,7 @@ static int tg3_ioctl(struct net_device *
 205                         return -EAGAIN;
 206
 207                 spin_lock_bh(&tp->lock);
 208 -               err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
 209 +               err = __tg3_readphy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
 210                 spin_unlock_bh(&tp->lock);
 211
 212                 data->val_out = mii_regval;
 213 @@ -10281,7 +10339,7 @@ static int tg3_ioctl(struct net_device *
 214                         return -EAGAIN;
 215
 216                 spin_lock_bh(&tp->lock);
 217 -               err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
 218 +               err = __tg3_writephy(tp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
 219                 spin_unlock_bh(&tp->lock);
 220
 221                 return err;
 222 @@ -10759,6 +10817,12 @@ static void __devinit tg3_get_5906_nvram
 223  /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 224  static void __devinit tg3_nvram_init(struct tg3 *tp)
 225  {
 226 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE) {
 227 +               /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
 228 +               tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
 229 +               return;
 230 +       }
 231 +
 232         tw32_f(GRC_EEPROM_ADDR,
 233              (EEPROM_ADDR_FSM_RESET |
 234               (EEPROM_DEFAULT_CLOCK_PERIOD <<
 235 @@ -10900,6 +10964,9 @@ static int tg3_nvram_read(struct tg3 *tp
 236  {
 237         int ret;
 238
 239 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
 240 +               return -ENODEV;
 241 +
 242         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
 243                 return tg3_nvram_read_using_eeprom(tp, offset, val);
 244
 245 @@ -11147,6 +11214,9 @@ static int tg3_nvram_write_block(struct
 246  {
 247         int ret;
 248
 249 +       if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
 250 +               return -ENODEV;
 251 +
 252         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
 253                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
 254                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
 255 @@ -12205,7 +12275,6 @@ static int __devinit tg3_get_invariants(
 256                 tp->write32 = tg3_write_flush_reg32;
 257         }
 258
 259 -
 260         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
 261             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
 262                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
 263 @@ -12241,6 +12310,11 @@ static int __devinit tg3_get_invariants(
 264               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
 265                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
 266
 267 +       if (tp->tg3_flags3 & TG3_FLG3_FLUSH_POSTED_WRITES) {
 268 +               tp->write32_tx_mbox = tg3_write_flush_reg32;
 269 +               tp->write32_rx_mbox = tg3_write_flush_reg32;
 270 +       }
 271 +
 272         /* Get eeprom hw config before calling tg3_set_power_state().
 273          * In particular, the TG3_FLG2_IS_NIC flag must be
 274          * determined before calling tg3_set_power_state() so that
 275 @@ -12640,6 +12714,10 @@ static int __devinit tg3_get_device_addr
 276         }
 277
 278         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
 279 +               if (tp->tg3_flags3 & TG3_FLG3_IS_SSB_CORE)
 280 +                       ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
 281 +       }
 282 +       if (!is_valid_ether_addr(&dev->dev_addr[0])) {
 283  #ifdef CONFIG_SPARC
 284                 if (!tg3_get_default_macaddr_sparc(tp))
 285                         return 0;
 286 @@ -13131,6 +13209,7 @@ static char * __devinit tg3_phy_string(s
 287         case PHY_ID_BCM5704:    return "5704";
 288         case PHY_ID_BCM5705:    return "5705";
 289         case PHY_ID_BCM5750:    return "5750";
 290 +       case PHY_ID_BCM5750_2:  return "5750-2";
 291         case PHY_ID_BCM5752:    return "5752";
 292         case PHY_ID_BCM5714:    return "5714";
 293         case PHY_ID_BCM5780:    return "5780";
 294 @@ -13317,6 +13396,13 @@ static int __devinit tg3_init_one(struct
 295                 tp->msg_enable = tg3_debug;
 296         else
 297                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
 298 +       if (pdev_is_ssb_gige_core(pdev)) {
 299 +               tp->tg3_flags3 |= TG3_FLG3_IS_SSB_CORE;
 300 +               if (ssb_gige_must_flush_posted_writes(pdev))
 301 +                       tp->tg3_flags3 |= TG3_FLG3_FLUSH_POSTED_WRITES;
 302 +               if (ssb_gige_have_roboswitch(pdev))
 303 +                       tp->tg3_flags3 |= TG3_FLG3_ROBOSWITCH;
 304 +       }
 305
 306         /* The word/byte swap controls here control register access byte
 307          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
 308 --- a/drivers/net/tg3.h
 309 +++ b/drivers/net/tg3.h
 310 @@ -2516,6 +2516,9 @@ struct tg3 {
 311  #define TG3_FLG3_RGMII_STD_IBND_DISABLE        0x00000100
 312  #define TG3_FLG3_RGMII_EXT_IBND_RX_EN  0x00000200
 313  #define TG3_FLG3_RGMII_EXT_IBND_TX_EN  0x00000400
 314 +#define TG3_FLG3_IS_SSB_CORE           0x00000800
 315 +#define TG3_FLG3_FLUSH_POSTED_WRITES   0x00001000
 316 +#define TG3_FLG3_ROBOSWITCH            0x00002000
 317
 318         struct timer_list               timer;
 319         u16                             timer_counter;
 320 @@ -2574,6 +2577,7 @@ struct tg3 {
 321  #define PHY_ID_BCM5714                 0x60008340
 322  #define PHY_ID_BCM5780                 0x60008350
 323  #define PHY_ID_BCM5755                 0xbc050cc0
 324 +#define PHY_ID_BCM5750_2               0xbc050cd0
 325  #define PHY_ID_BCM5787                 0xbc050ce0
 326  #define PHY_ID_BCM5756                 0xbc050ed0
 327  #define PHY_ID_BCM5784                 0xbc050fa0
 328 @@ -2613,7 +2617,7 @@ struct tg3 {
 329          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
 330          (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
 331          (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
 332 -        (X) == PHY_ID_BCM8002)
 333 +        (X) == PHY_ID_BCM8002 || (X) == PHY_ID_BCM5750_2)
 334
 335         struct tg3_hw_stats             *hw_stats;
 336         dma_addr_t                      stats_mapping;