target/linux/brcm47xx/patches-2.6.28/220-bcm5354.patch

   1 diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c
   2 --- a/drivers/ssb/driver_chipcommon.c
   3 +++ b/drivers/ssb/driver_chipcommon.c
   4 @@ -270,6 +270,8 @@ void ssb_chipco_resume(struct ssb_chipcommon *cc)
   5  void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
   6                               u32 *plltype, u32 *n, u32 *m)
   7  {
   8 +       if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
   9 +               return;
  10         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
  11         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
  12         switch (*plltype) {
  13 @@ -293,6 +295,8 @@ void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
  14  void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
  15                                  u32 *plltype, u32 *n, u32 *m)
  16  {
  17 +       if ((chipco_read32(cc, SSB_CHIPCO_CHIPID) & SSB_CHIPCO_IDMASK) == 0x5354)
  18 +               return;
  19         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
  20         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
  21         switch (*plltype) {
  22 diff --git a/drivers/ssb/driver_mipscore.c b/drivers/ssb/driver_mipscore.c
  23 --- a/drivers/ssb/driver_mipscore.c
  24 +++ b/drivers/ssb/driver_mipscore.c
  25 @@ -161,6 +161,8 @@ u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
  26
  27         if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
  28                 rate = 200000000;
  29 +       } else if (bus->chip_id == 0x5354) {
  30 +               rate = 240000000;
  31         } else {
  32                 rate = ssb_calc_clock_rate(pll_type, n, m);
  33         }
  34 diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c
  35 --- a/drivers/ssb/main.c
  36 +++ b/drivers/ssb/main.c
  37 @@ -1011,6 +1011,8 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
  38
  39         if (bus->chip_id == 0x5365) {
  40                 rate = 100000000;
  41 +       } else if (bus->chip_id == 0x5354) {
  42 +               rate = 120000000;
  43         } else {
  44                 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
  45                 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */