target/linux/at91/patches-2.6.21/000-at91patches.patch

   1 Index: linux-2.6.21.7/arch/arm/boot/compressed/head-at91rm9200.S
   2 ===================================================================
   3 --- linux-2.6.21.7.orig/arch/arm/boot/compressed/head-at91rm9200.S
   4 +++ linux-2.6.21.7/arch/arm/boot/compressed/head-at91rm9200.S
   5 @@ -67,6 +67,12 @@
   6                 cmp     r7, r3
   7                 beq     99f
   8
   9 +               @ Promwad Chub : 1181
  10 +               mov     r3,     #(MACH_TYPE_CHUB & 0xff)
  11 +               orr     r3, r3, #(MACH_TYPE_CHUB & 0xff00)
  12 +               cmp     r7, r3
  13 +               beq     99f
  14 +
  15                 @ Unknown board, use the AT91RM9200DK board
  16                 @ mov   r7, #MACH_TYPE_AT91RM9200
  17                 mov     r7,     #(MACH_TYPE_AT91RM9200DK & 0xff)
  18 Index: linux-2.6.21.7/arch/arm/mach-at91/Kconfig
  19 ===================================================================
  20 --- linux-2.6.21.7.orig/arch/arm/mach-at91/Kconfig
  21 +++ linux-2.6.21.7/arch/arm/mach-at91/Kconfig
  22 @@ -17,6 +17,9 @@ config ARCH_AT91SAM9261
  23  config ARCH_AT91SAM9263
  24         bool "AT91SAM9263"
  25
  26 +config ARCH_AT91SAM9RL
  27 +       bool "AT91SAM9RL"
  28 +
  29  endchoice
  30
  31  # ----------------------------------------------------------
  32 @@ -87,6 +90,12 @@ config MACH_KAFA
  33         help
  34           Select this if you are using Sperry-Sun's KAFA board.
  35
  36 +config MACH_CHUB
  37 +       bool "Promwad Chub board"
  38 +       depends on ARCH_AT91RM9200
  39 +       help
  40 +         Select this if you are using Promwad's Chub board.
  41 +
  42  endif
  43
  44  # ----------------------------------------------------------
  45 @@ -111,6 +120,13 @@ config MACH_AT91SAM9260EK
  46           Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
  47           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
  48
  49 +config MACH_CAM60
  50 +       bool "KwikByte CAM60 board"
  51 +       depends on ARCH_AT91SAM9260
  52 +       help
  53 +         Select this if you are using KwikByte's CAM60 board based on the Atmel AT91SAM9260.
  54 +         <http://www.kwikbyte.com>
  55 +
  56  endif
  57
  58  # ----------------------------------------------------------
  59 @@ -145,6 +161,20 @@ endif
  60
  61  # ----------------------------------------------------------
  62
  63 +if ARCH_AT91SAM9RL
  64 +
  65 +comment "AT91SAM9RL Board Type"
  66 +
  67 +config MACH_AT91SAM9RLEK
  68 +       bool "Atmel AT91SAM9RL-EK Evaluation Kit"
  69 +       depends on ARCH_AT91SAM9RL
  70 +       help
  71 +         Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
  72 +
  73 +endif
  74 +
  75 +# ----------------------------------------------------------
  76 +
  77  comment "AT91 Board Options"
  78
  79  config MTD_AT91_DATAFLASH_CARD
  80 @@ -160,6 +190,20 @@ config MTD_NAND_AT91_BUSWIDTH_16
  81           On AT91SAM926x boards both types of NAND flash can be present
  82           (8 and 16 bit data bus width).
  83
  84 +config CSB300_WAKE_SW0
  85 +       bool "CSB300 SW0 irq0 wakeup"
  86 +       depends on MACH_CSB337 && PM
  87 +       help
  88 +         If you have a CSB300 connected to your CSB337, this lets
  89 +         SW0 serve as a wakeup button.  It uses IRQ0.
  90 +
  91 +config CSB300_WAKE_SW1
  92 +       bool "CSB300 SW1 gpio wakeup"
  93 +       depends on MACH_CSB337 && PM
  94 +       help
  95 +         If you have a CSB300 connected to your CSB337, this lets
  96 +         SW1 serve as a wakeup button.  It uses GPIO.
  97 +
  98  # ----------------------------------------------------------
  99
 100  comment "AT91 Feature Selections"
 101 @@ -170,6 +214,20 @@ config AT91_PROGRAMMABLE_CLOCKS
 102           Select this if you need to program one or more of the PCK0..PCK3
 103           programmable clock outputs.
 104
 105 +config ATMEL_TCLIB
 106 +       bool "Timer/Counter Library"
 107 +       help
 108 +         Select this if you want a library to allocate the Timer/Counter
 109 +         blocks found on many Atmel processors.  This facilitates using
 110 +         these modules despite processor differences.
 111 +
 112 +config AT91_SLOW_CLOCK
 113 +       bool "Suspend-to-RAM uses slow clock mode (EXPERIMENTAL)"
 114 +       depends on PM && EXPERIMENTAL
 115 +       help
 116 +         Select this if you wish to put the CPU into slow clock mode
 117 +         while in the "Suspend to RAM" state, to save more power.
 118 +
 119  endmenu
 120
 121  endif
 122 Index: linux-2.6.21.7/arch/arm/mach-at91/Makefile
 123 ===================================================================
 124 --- linux-2.6.21.7.orig/arch/arm/mach-at91/Makefile
 125 +++ linux-2.6.21.7/arch/arm/mach-at91/Makefile
 126 @@ -8,12 +8,15 @@ obj-n         :=
 127  obj-           :=
 128
 129  obj-$(CONFIG_PM)               += pm.o
 130 +obj-$(CONFIG_AT91_SLOW_CLOCK)  += pm_slowclock.o
 131 +obj-$(CONFIG_ATMEL_TCLIB)      += tclib.o
 132
 133  # CPU-specific support
 134  obj-$(CONFIG_ARCH_AT91RM9200)  += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
 135  obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
 136  obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
 137  obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
 138 +obj-$(CONFIG_ARCH_AT91SAM9RL)  += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o
 139
 140  # AT91RM9200 board-specific support
 141  obj-$(CONFIG_MACH_ONEARM)      += board-1arm.o
 142 @@ -25,9 +28,11 @@ obj-$(CONFIG_MACH_CARMEVA)   += board-carm
 143  obj-$(CONFIG_MACH_KB9200)      += board-kb9202.o
 144  obj-$(CONFIG_MACH_ATEB9200)    += board-eb9200.o
 145  obj-$(CONFIG_MACH_KAFA)                += board-kafa.o
 146 +obj-$(CONFIG_MACH_CHUB)                += board-chub.o
 147
 148  # AT91SAM9260 board-specific support
 149  obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 150 +obj-$(CONFIG_MACH_CAM60)       += board-cam60.o
 151
 152  # AT91SAM9261 board-specific support
 153  obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
 154 @@ -35,9 +40,13 @@ obj-$(CONFIG_MACH_AT91SAM9261EK) += boar
 155  # AT91SAM9263 board-specific support
 156  obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
 157
 158 +# AT91SAM9RL board-specific support
 159 +obj-$(CONFIG_MACH_AT91SAM9RLEK)        += board-sam9rlek.o
 160 +
 161  # LEDs support
 162  led-$(CONFIG_ARCH_AT91RM9200DK)        += leds.o
 163  led-$(CONFIG_MACH_AT91RM9200EK)        += leds.o
 164 +led-$(CONFIG_MACH_AT91SAM9261EK)+= leds.o
 165  led-$(CONFIG_MACH_CSB337)      += leds.o
 166  led-$(CONFIG_MACH_CSB637)      += leds.o
 167  led-$(CONFIG_MACH_KB9200)      += leds.o
 168 @@ -45,7 +54,7 @@ led-$(CONFIG_MACH_KAFA)               += leds.o
 169  obj-$(CONFIG_LEDS) += $(led-y)
 170
 171  # VGA support
 172 -#obj-$(CONFIG_FB_S1D13XXX)     += ics1523.o
 173 +obj-$(CONFIG_FB_S1D13XXX)      += ics1523.o
 174
 175
 176  ifeq ($(CONFIG_PM_DEBUG),y)
 177 Index: linux-2.6.21.7/arch/arm/mach-at91/at91rm9200.c
 178 ===================================================================
 179 --- linux-2.6.21.7.orig/arch/arm/mach-at91/at91rm9200.c
 180 +++ linux-2.6.21.7/arch/arm/mach-at91/at91rm9200.c
 181 @@ -117,6 +117,21 @@ static struct clk pioD_clk = {
 182         .pmc_mask       = 1 << AT91RM9200_ID_PIOD,
 183         .type           = CLK_TYPE_PERIPHERAL,
 184  };
 185 +static struct clk ssc0_clk = {
 186 +       .name           = "ssc0_clk",
 187 +       .pmc_mask       = 1 << AT91RM9200_ID_SSC0,
 188 +       .type           = CLK_TYPE_PERIPHERAL,
 189 +};
 190 +static struct clk ssc1_clk = {
 191 +       .name           = "ssc1_clk",
 192 +       .pmc_mask       = 1 << AT91RM9200_ID_SSC1,
 193 +       .type           = CLK_TYPE_PERIPHERAL,
 194 +};
 195 +static struct clk ssc2_clk = {
 196 +       .name           = "ssc2_clk",
 197 +       .pmc_mask       = 1 << AT91RM9200_ID_SSC2,
 198 +       .type           = CLK_TYPE_PERIPHERAL,
 199 +};
 200  static struct clk tc0_clk = {
 201         .name           = "tc0_clk",
 202         .pmc_mask       = 1 << AT91RM9200_ID_TC0,
 203 @@ -161,7 +176,9 @@ static struct clk *periph_clocks[] __ini
 204         &udc_clk,
 205         &twi_clk,
 206         &spi_clk,
 207 -       // ssc 0 .. ssc2
 208 +       &ssc0_clk,
 209 +       &ssc1_clk,
 210 +       &ssc2_clk,
 211         &tc0_clk,
 212         &tc1_clk,
 213         &tc2_clk,
 214 @@ -250,6 +267,33 @@ static void at91rm9200_reset(void)
 215
 216
 217  /* --------------------------------------------------------------------
 218 + *  Timer/Counter library initialization
 219 + * -------------------------------------------------------------------- */
 220 +#ifdef CONFIG_ATMEL_TCLIB
 221 +
 222 +#include "tclib.h"
 223 +
 224 +static struct atmel_tcblock at91rm9200_tcblocks[] = {
 225 +       [0] = {
 226 +               .physaddr       = AT91RM9200_BASE_TCB0,
 227 +               .irq            = { AT91RM9200_ID_TC0, AT91RM9200_ID_TC1, AT91RM9200_ID_TC2 },
 228 +               .clk            = { &tc0_clk, &tc1_clk, &tc2_clk },
 229 +       },
 230 +       [1] = {
 231 +               .physaddr       = AT91RM9200_BASE_TCB1,
 232 +               .irq            = { AT91RM9200_ID_TC3, AT91RM9200_ID_TC4, AT91RM9200_ID_TC5 },
 233 +               .clk            = { &tc3_clk, &tc4_clk, &tc5_clk },
 234 +       },
 235 +};
 236 +
 237 +#define at91rm9200_tc_init()   atmel_tc_init(at91rm9200_tcblocks, ARRAY_SIZE(at91rm9200_tcblocks))
 238 +
 239 +#else
 240 +#define at91rm9200_tc_init()   do {} while(0)
 241 +#endif
 242 +
 243 +
 244 +/* --------------------------------------------------------------------
 245   *  AT91RM9200 processor initialization
 246   * -------------------------------------------------------------------- */
 247  void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks)
 248 @@ -271,6 +315,9 @@ void __init at91rm9200_initialize(unsign
 249
 250         /* Initialize GPIO subsystem */
 251         at91_gpio_init(at91rm9200_gpio, banks);
 252 +
 253 +       /* Initialize the Timer/Counter blocks */
 254 +       at91rm9200_tc_init();
 255  }
 256
 257
 258 @@ -284,28 +331,28 @@ void __init at91rm9200_initialize(unsign
 259  static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 260         7,      /* Advanced Interrupt Controller (FIQ) */
 261         7,      /* System Peripherals */
 262 -       0,      /* Parallel IO Controller A */
 263 -       0,      /* Parallel IO Controller B */
 264 -       0,      /* Parallel IO Controller C */
 265 -       0,      /* Parallel IO Controller D */
 266 -       6,      /* USART 0 */
 267 -       6,      /* USART 1 */
 268 -       6,      /* USART 2 */
 269 -       6,      /* USART 3 */
 270 +       1,      /* Parallel IO Controller A */
 271 +       1,      /* Parallel IO Controller B */
 272 +       1,      /* Parallel IO Controller C */
 273 +       1,      /* Parallel IO Controller D */
 274 +       5,      /* USART 0 */
 275 +       5,      /* USART 1 */
 276 +       5,      /* USART 2 */
 277 +       5,      /* USART 3 */
 278         0,      /* Multimedia Card Interface */
 279 -       4,      /* USB Device Port */
 280 -       0,      /* Two-Wire Interface */
 281 -       6,      /* Serial Peripheral Interface */
 282 -       5,      /* Serial Synchronous Controller 0 */
 283 -       5,      /* Serial Synchronous Controller 1 */
 284 -       5,      /* Serial Synchronous Controller 2 */
 285 +       2,      /* USB Device Port */
 286 +       6,      /* Two-Wire Interface */
 287 +       5,      /* Serial Peripheral Interface */
 288 +       4,      /* Serial Synchronous Controller 0 */
 289 +       4,      /* Serial Synchronous Controller 1 */
 290 +       4,      /* Serial Synchronous Controller 2 */
 291         0,      /* Timer Counter 0 */
 292         0,      /* Timer Counter 1 */
 293         0,      /* Timer Counter 2 */
 294         0,      /* Timer Counter 3 */
 295         0,      /* Timer Counter 4 */
 296         0,      /* Timer Counter 5 */
 297 -       3,      /* USB Host port */
 298 +       2,      /* USB Host port */
 299         3,      /* Ethernet MAC */
 300         0,      /* Advanced Interrupt Controller (IRQ0) */
 301         0,      /* Advanced Interrupt Controller (IRQ1) */
 302 Index: linux-2.6.21.7/arch/arm/mach-at91/at91rm9200_devices.c
 303 ===================================================================
 304 --- linux-2.6.21.7.orig/arch/arm/mach-at91/at91rm9200_devices.c
 305 +++ linux-2.6.21.7/arch/arm/mach-at91/at91rm9200_devices.c
 306 @@ -480,7 +480,18 @@ void __init at91_add_device_i2c(void) {}
 307   *  SPI
 308   * -------------------------------------------------------------------- */
 309
 310 -#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
 311 +#if defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)                /* legacy SPI driver */
 312 +#define SPI_DEVNAME    "at91_spi"
 313 +
 314 +#elif defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE)      /* SPI bitbanging driver */
 315 +#define SPI_DEVNAME    "at91_spi"
 316 +
 317 +#elif defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)    /* new SPI driver */
 318 +#define SPI_DEVNAME    "atmel_spi"
 319 +
 320 +#endif
 321 +
 322 +#ifdef SPI_DEVNAME
 323  static u64 spi_dmamask = 0xffffffffUL;
 324
 325  static struct resource spi_resources[] = {
 326 @@ -497,7 +508,7 @@ static struct resource spi_resources[] =
 327  };
 328
 329  static struct platform_device at91rm9200_spi_device = {
 330 -       .name           = "at91_spi",
 331 +       .name           = SPI_DEVNAME,
 332         .id             = 0,
 333         .dev            = {
 334                                 .dma_mask               = &spi_dmamask,
 335 @@ -606,6 +617,32 @@ void __init at91_init_leds(u8 cpu_led, u
 336  #endif
 337
 338
 339 +#if defined(CONFIG_NEW_LEDS)
 340 +
 341 +static struct platform_device at91_leds = {
 342 +       .name           = "at91_leds",
 343 +       .id             = -1,
 344 +};
 345 +
 346 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
 347 +{
 348 +       if (!nr)
 349 +               return;
 350 +
 351 +       at91_leds.dev.platform_data = leds;
 352 +
 353 +       for ( ; nr; nr--, leds++) {
 354 +               leds->index = nr;       /* first record stores number of leds */
 355 +               at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
 356 +       }
 357 +
 358 +       platform_device_register(&at91_leds);
 359 +}
 360 +#else
 361 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
 362 +#endif
 363 +
 364 +
 365  /* --------------------------------------------------------------------
 366   *  UART
 367   * -------------------------------------------------------------------- */
 368 Index: linux-2.6.21.7/arch/arm/mach-at91/at91sam9260.c
 369 ===================================================================
 370 --- linux-2.6.21.7.orig/arch/arm/mach-at91/at91sam9260.c
 371 +++ linux-2.6.21.7/arch/arm/mach-at91/at91sam9260.c
 372 @@ -119,6 +119,11 @@ static struct clk spi1_clk = {
 373         .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
 374         .type           = CLK_TYPE_PERIPHERAL,
 375  };
 376 +static struct clk ssc_clk = {
 377 +       .name           = "ssc_clk",
 378 +       .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
 379 +       .type           = CLK_TYPE_PERIPHERAL,
 380 +};
 381  static struct clk tc0_clk = {
 382         .name           = "tc0_clk",
 383         .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
 384 @@ -193,7 +198,7 @@ static struct clk *periph_clocks[] __ini
 385         &twi_clk,
 386         &spi0_clk,
 387         &spi1_clk,
 388 -       // ssc
 389 +       &ssc_clk,
 390         &tc0_clk,
 391         &tc1_clk,
 392         &tc2_clk,
 393 @@ -264,6 +269,33 @@ static void at91sam9260_reset(void)
 394
 395
 396  /* --------------------------------------------------------------------
 397 + *  Timer/Counter library initialization
 398 + * -------------------------------------------------------------------- */
 399 +#ifdef CONFIG_ATMEL_TCLIB
 400 +
 401 +#include "tclib.h"
 402 +
 403 +static struct atmel_tcblock at91sam9260_tcblocks[] = {
 404 +       [0] = {
 405 +               .physaddr       = AT91SAM9260_BASE_TCB0,
 406 +               .irq            = { AT91SAM9260_ID_TC0, AT91SAM9260_ID_TC1, AT91SAM9260_ID_TC2 },
 407 +               .clk            = { &tc0_clk, &tc1_clk, &tc2_clk },
 408 +       },
 409 +       [1] = {
 410 +               .physaddr       = AT91SAM9260_BASE_TCB1,
 411 +               .irq            = { AT91SAM9260_ID_TC3, AT91SAM9260_ID_TC4, AT91SAM9260_ID_TC5 },
 412 +               .clk            = { &tc3_clk, &tc4_clk, &tc5_clk },
 413 +       },
 414 +};
 415 +
 416 +#define at91sam9260_tc_init()  atmel_tc_init(at91sam9260_tcblocks, ARRAY_SIZE(at91sam9260_tcblocks))
 417 +
 418 +#else
 419 +#define at91sam9260_tc_init()  do {} while(0)
 420 +#endif
 421 +
 422 +
 423 +/* --------------------------------------------------------------------
 424   *  AT91SAM9260 processor initialization
 425   * -------------------------------------------------------------------- */
 426
 427 @@ -310,6 +342,9 @@ void __init at91sam9260_initialize(unsig
 428
 429         /* Register GPIO subsystem */
 430         at91_gpio_init(at91sam9260_gpio, 3);
 431 +
 432 +       /* Initialize the Timer/Counter blocks */
 433 +       at91sam9260_tc_init();
 434  }
 435
 436  /* --------------------------------------------------------------------
 437 @@ -322,30 +357,30 @@ void __init at91sam9260_initialize(unsig
 438  static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 439         7,      /* Advanced Interrupt Controller */
 440         7,      /* System Peripherals */
 441 -       0,      /* Parallel IO Controller A */
 442 -       0,      /* Parallel IO Controller B */
 443 -       0,      /* Parallel IO Controller C */
 444 +       1,      /* Parallel IO Controller A */
 445 +       1,      /* Parallel IO Controller B */
 446 +       1,      /* Parallel IO Controller C */
 447         0,      /* Analog-to-Digital Converter */
 448 -       6,      /* USART 0 */
 449 -       6,      /* USART 1 */
 450 -       6,      /* USART 2 */
 451 +       5,      /* USART 0 */
 452 +       5,      /* USART 1 */
 453 +       5,      /* USART 2 */
 454         0,      /* Multimedia Card Interface */
 455 -       4,      /* USB Device Port */
 456 -       0,      /* Two-Wire Interface */
 457 -       6,      /* Serial Peripheral Interface 0 */
 458 -       6,      /* Serial Peripheral Interface 1 */
 459 +       2,      /* USB Device Port */
 460 +       6,      /* Two-Wire Interface */
 461 +       5,      /* Serial Peripheral Interface 0 */
 462 +       5,      /* Serial Peripheral Interface 1 */
 463         5,      /* Serial Synchronous Controller */
 464         0,
 465         0,
 466         0,      /* Timer Counter 0 */
 467         0,      /* Timer Counter 1 */
 468         0,      /* Timer Counter 2 */
 469 -       3,      /* USB Host port */
 470 +       2,      /* USB Host port */
 471         3,      /* Ethernet */
 472         0,      /* Image Sensor Interface */
 473 -       6,      /* USART 3 */
 474 -       6,      /* USART 4 */
 475 -       6,      /* USART 5 */
 476 +       5,      /* USART 3 */
 477 +       5,      /* USART 4 */
 478 +       5,      /* USART 5 */
 479         0,      /* Timer Counter 3 */
 480         0,      /* Timer Counter 4 */
 481         0,      /* Timer Counter 5 */
 482 Index: linux-2.6.21.7/arch/arm/mach-at91/at91sam9260_devices.c
 483 ===================================================================
 484 --- linux-2.6.21.7.orig/arch/arm/mach-at91/at91sam9260_devices.c
 485 +++ linux-2.6.21.7/arch/arm/mach-at91/at91sam9260_devices.c
 486 @@ -527,6 +527,32 @@ void __init at91_init_leds(u8 cpu_led, u
 487  #endif
 488
 489
 490 +#if defined(CONFIG_NEW_LEDS)
 491 +
 492 +static struct platform_device at91_leds = {
 493 +       .name           = "at91_leds",
 494 +       .id             = -1,
 495 +};
 496 +
 497 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
 498 +{
 499 +       if (!nr)
 500 +               return;
 501 +
 502 +       at91_leds.dev.platform_data = leds;
 503 +
 504 +       for ( ; nr; nr--, leds++) {
 505 +               leds->index = nr;       /* first record stores number of leds */
 506 +               at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
 507 +       }
 508 +
 509 +       platform_device_register(&at91_leds);
 510 +}
 511 +#else
 512 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
 513 +#endif
 514 +
 515 +
 516  /* --------------------------------------------------------------------
 517   *  UART
 518   * -------------------------------------------------------------------- */
 519 Index: linux-2.6.21.7/arch/arm/mach-at91/at91sam9261.c
 520 ===================================================================
 521 --- linux-2.6.21.7.orig/arch/arm/mach-at91/at91sam9261.c
 522 +++ linux-2.6.21.7/arch/arm/mach-at91/at91sam9261.c
 523 @@ -97,6 +97,21 @@ static struct clk spi1_clk = {
 524         .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
 525         .type           = CLK_TYPE_PERIPHERAL,
 526  };
 527 +static struct clk ssc0_clk = {
 528 +       .name           = "ssc0_clk",
 529 +       .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
 530 +       .type           = CLK_TYPE_PERIPHERAL,
 531 +};
 532 +static struct clk ssc1_clk = {
 533 +       .name           = "ssc1_clk",
 534 +       .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
 535 +       .type           = CLK_TYPE_PERIPHERAL,
 536 +};
 537 +static struct clk ssc2_clk = {
 538 +       .name           = "ssc2_clk",
 539 +       .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
 540 +       .type           = CLK_TYPE_PERIPHERAL,
 541 +};
 542  static struct clk tc0_clk = {
 543         .name           = "tc0_clk",
 544         .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
 545 @@ -135,7 +150,9 @@ static struct clk *periph_clocks[] __ini
 546         &twi_clk,
 547         &spi0_clk,
 548         &spi1_clk,
 549 -       // ssc 0 .. ssc2
 550 +       &ssc0_clk,
 551 +       &ssc1_clk,
 552 +       &ssc2_clk,
 553         &tc0_clk,
 554         &tc1_clk,
 555         &tc2_clk,
 556 @@ -230,6 +247,28 @@ static void at91sam9261_reset(void)
 557
 558
 559  /* --------------------------------------------------------------------
 560 + *  Timer/Counter library initialization
 561 + * -------------------------------------------------------------------- */
 562 +#ifdef CONFIG_ATMEL_TCLIB
 563 +
 564 +#include "tclib.h"
 565 +
 566 +static struct atmel_tcblock at91sam9261_tcblocks[] = {
 567 +       [0] = {
 568 +               .physaddr       = AT91SAM9261_BASE_TCB0,
 569 +               .irq            = { AT91SAM9261_ID_TC0, AT91SAM9261_ID_TC1, AT91SAM9261_ID_TC2 },
 570 +               .clk            = { &tc0_clk, &tc1_clk, &tc2_clk },
 571 +       }
 572 +};
 573 +
 574 +#define at91sam9261_tc_init()  atmel_tc_init(at91sam9261_tcblocks, ARRAY_SIZE(at91sam9261_tcblocks))
 575 +
 576 +#else
 577 +#define at91sam9261_tc_init()  do {} while(0)
 578 +#endif
 579 +
 580 +
 581 +/* --------------------------------------------------------------------
 582   *  AT91SAM9261 processor initialization
 583   * -------------------------------------------------------------------- */
 584
 585 @@ -250,6 +289,9 @@ void __init at91sam9261_initialize(unsig
 586
 587         /* Register GPIO subsystem */
 588         at91_gpio_init(at91sam9261_gpio, 3);
 589 +
 590 +       /* Initialize the Timer/Counter blocks */
 591 +       at91sam9261_tc_init();
 592  }
 593
 594  /* --------------------------------------------------------------------
 595 @@ -262,25 +304,25 @@ void __init at91sam9261_initialize(unsig
 596  static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 597         7,      /* Advanced Interrupt Controller */
 598         7,      /* System Peripherals */
 599 -       0,      /* Parallel IO Controller A */
 600 -       0,      /* Parallel IO Controller B */
 601 -       0,      /* Parallel IO Controller C */
 602 -       0,
 603 -       6,      /* USART 0 */
 604 -       6,      /* USART 1 */
 605 -       6,      /* USART 2 */
 606 +       1,      /* Parallel IO Controller A */
 607 +       1,      /* Parallel IO Controller B */
 608 +       1,      /* Parallel IO Controller C */
 609 +       0,
 610 +       5,      /* USART 0 */
 611 +       5,      /* USART 1 */
 612 +       5,      /* USART 2 */
 613         0,      /* Multimedia Card Interface */
 614 -       4,      /* USB Device Port */
 615 -       0,      /* Two-Wire Interface */
 616 -       6,      /* Serial Peripheral Interface 0 */
 617 -       6,      /* Serial Peripheral Interface 1 */
 618 -       5,      /* Serial Synchronous Controller 0 */
 619 -       5,      /* Serial Synchronous Controller 1 */
 620 -       5,      /* Serial Synchronous Controller 2 */
 621 +       2,      /* USB Device Port */
 622 +       6,      /* Two-Wire Interface */
 623 +       5,      /* Serial Peripheral Interface 0 */
 624 +       5,      /* Serial Peripheral Interface 1 */
 625 +       4,      /* Serial Synchronous Controller 0 */
 626 +       4,      /* Serial Synchronous Controller 1 */
 627 +       4,      /* Serial Synchronous Controller 2 */
 628         0,      /* Timer Counter 0 */
 629         0,      /* Timer Counter 1 */
 630         0,      /* Timer Counter 2 */
 631 -       3,      /* USB Host port */
 632 +       2,      /* USB Host port */
 633         3,      /* LCD Controller */
 634         0,
 635         0,
 636 Index: linux-2.6.21.7/arch/arm/mach-at91/at91sam9261_devices.c
 637 ===================================================================
 638 --- linux-2.6.21.7.orig/arch/arm/mach-at91/at91sam9261_devices.c
 639 +++ linux-2.6.21.7/arch/arm/mach-at91/at91sam9261_devices.c
 640 @@ -14,6 +14,9 @@
 641  #include <asm/mach/map.h>
 642
 643  #include <linux/platform_device.h>
 644 +#include <linux/fb.h>
 645 +
 646 +#include <video/atmel_lcdc.h>
 647
 648  #include <asm/arch/board.h>
 649  #include <asm/arch/gpio.h>
 650 @@ -430,9 +433,9 @@ void __init at91_add_device_spi(struct s
 651   *  LCD Controller
 652   * -------------------------------------------------------------------- */
 653
 654 -#if defined(CONFIG_FB_AT91) || defined(CONFIG_FB_AT91_MODULE)
 655 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
 656  static u64 lcdc_dmamask = 0xffffffffUL;
 657 -static struct at91fb_info lcdc_data;
 658 +static struct atmel_lcdfb_info lcdc_data;
 659
 660  static struct resource lcdc_resources[] = {
 661         [0] = {
 662 @@ -455,7 +458,7 @@ static struct resource lcdc_resources[]
 663  };
 664
 665  static struct platform_device at91_lcdc_device = {
 666 -       .name           = "at91-fb",
 667 +       .name           = "atmel_lcdfb",
 668         .id             = 0,
 669         .dev            = {
 670                                 .dma_mask               = &lcdc_dmamask,
 671 @@ -466,7 +469,7 @@ static struct platform_device at91_lcdc_
 672         .num_resources  = ARRAY_SIZE(lcdc_resources),
 673  };
 674
 675 -void __init at91_add_device_lcdc(struct at91fb_info *data)
 676 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
 677  {
 678         if (!data) {
 679                 return;
 680 @@ -499,7 +502,7 @@ void __init at91_add_device_lcdc(struct
 681         platform_device_register(&at91_lcdc_device);
 682  }
 683  #else
 684 -void __init at91_add_device_lcdc(struct at91fb_info *data) {}
 685 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 686  #endif
 687
 688
 689 @@ -525,6 +528,32 @@ void __init at91_init_leds(u8 cpu_led, u
 690  #endif
 691
 692
 693 +#if defined(CONFIG_NEW_LEDS)
 694 +
 695 +static struct platform_device at91_leds = {
 696 +       .name           = "at91_leds",
 697 +       .id             = -1,
 698 +};
 699 +
 700 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
 701 +{
 702 +       if (!nr)
 703 +               return;
 704 +
 705 +       at91_leds.dev.platform_data = leds;
 706 +
 707 +       for ( ; nr; nr--, leds++) {
 708 +               leds->index = nr;       /* first record stores number of leds */
 709 +               at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
 710 +       }
 711 +
 712 +       platform_device_register(&at91_leds);
 713 +}
 714 +#else
 715 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
 716 +#endif
 717 +
 718 +
 719  /* --------------------------------------------------------------------
 720   *  UART
 721   * -------------------------------------------------------------------- */
 722 Index: linux-2.6.21.7/arch/arm/mach-at91/at91sam9263.c
 723 ===================================================================
 724 --- linux-2.6.21.7.orig/arch/arm/mach-at91/at91sam9263.c
 725 +++ linux-2.6.21.7/arch/arm/mach-at91/at91sam9263.c
 726 @@ -87,6 +87,11 @@ static struct clk mmc1_clk = {
 727         .pmc_mask       = 1 << AT91SAM9263_ID_MCI1,
 728         .type           = CLK_TYPE_PERIPHERAL,
 729  };
 730 +static struct clk can_clk = {
 731 +       .name           = "can_clk",
 732 +       .pmc_mask       = 1 << AT91SAM9263_ID_CAN,
 733 +       .type           = CLK_TYPE_PERIPHERAL,
 734 +};
 735  static struct clk twi_clk = {
 736         .name           = "twi_clk",
 737         .pmc_mask       = 1 << AT91SAM9263_ID_TWI,
 738 @@ -102,16 +107,46 @@ static struct clk spi1_clk = {
 739         .pmc_mask       = 1 << AT91SAM9263_ID_SPI1,
 740         .type           = CLK_TYPE_PERIPHERAL,
 741  };
 742 +static struct clk ssc0_clk = {
 743 +       .name           = "ssc0_clk",
 744 +       .pmc_mask       = 1 << AT91SAM9263_ID_SSC0,
 745 +       .type           = CLK_TYPE_PERIPHERAL,
 746 +};
 747 +static struct clk ssc1_clk = {
 748 +       .name           = "ssc1_clk",
 749 +       .pmc_mask       = 1 << AT91SAM9263_ID_SSC1,
 750 +       .type           = CLK_TYPE_PERIPHERAL,
 751 +};
 752 +static struct clk ac97_clk = {
 753 +       .name           = "ac97_clk",
 754 +       .pmc_mask       = 1 << AT91SAM9263_ID_AC97C,
 755 +       .type           = CLK_TYPE_PERIPHERAL,
 756 +};
 757  static struct clk tcb_clk = {
 758         .name           = "tcb_clk",
 759         .pmc_mask       = 1 << AT91SAM9263_ID_TCB,
 760         .type           = CLK_TYPE_PERIPHERAL,
 761  };
 762 +static struct clk pwmc_clk = {
 763 +       .name           = "pwmc_clk",
 764 +       .pmc_mask       = 1 << AT91SAM9263_ID_PWMC,
 765 +       .type           = CLK_TYPE_PERIPHERAL,
 766 +};
 767  static struct clk macb_clk = {
 768         .name           = "macb_clk",
 769         .pmc_mask       = 1 << AT91SAM9263_ID_EMAC,
 770         .type           = CLK_TYPE_PERIPHERAL,
 771  };
 772 +static struct clk dma_clk = {
 773 +       .name           = "dma_clk",
 774 +       .pmc_mask       = 1 << AT91SAM9263_ID_DMA,
 775 +       .type           = CLK_TYPE_PERIPHERAL,
 776 +};
 777 +static struct clk twodge_clk = {
 778 +       .name           = "2dge_clk",
 779 +       .pmc_mask       = 1 << AT91SAM9263_ID_2DGE,
 780 +       .type           = CLK_TYPE_PERIPHERAL,
 781 +};
 782  static struct clk udc_clk = {
 783         .name           = "udc_clk",
 784         .pmc_mask       = 1 << AT91SAM9263_ID_UDP,
 785 @@ -142,20 +177,21 @@ static struct clk *periph_clocks[] __ini
 786         &usart2_clk,
 787         &mmc0_clk,
 788         &mmc1_clk,
 789 -       // can
 790 +       &can_clk,
 791         &twi_clk,
 792         &spi0_clk,
 793         &spi1_clk,
 794 -       // ssc0 .. ssc1
 795 -       // ac97
 796 +       &ssc0_clk,
 797 +       &ssc1_clk,
 798 +       &ac97_clk,
 799         &tcb_clk,
 800 -       // pwmc
 801 +       &pwmc_clk,
 802         &macb_clk,
 803 -       // 2dge
 804 +       &twodge_clk,
 805         &udc_clk,
 806         &isi_clk,
 807         &lcdc_clk,
 808 -       // dma
 809 +       &dma_clk,
 810         &ohci_clk,
 811         // irq0 .. irq1
 812  };
 813 @@ -237,6 +273,28 @@ static void at91sam9263_reset(void)
 814
 815
 816  /* --------------------------------------------------------------------
 817 + *  Timer/Counter library initialization
 818 + * -------------------------------------------------------------------- */
 819 +#ifdef CONFIG_ATMEL_TCLIB
 820 +
 821 +#include "tclib.h"
 822 +
 823 +static struct atmel_tcblock at91sam9263_tcblocks[] = {
 824 +       [0] = {
 825 +               .physaddr       = AT91SAM9263_BASE_TCB0,
 826 +               .irq            = { AT91SAM9263_ID_TCB, AT91SAM9263_ID_TCB, AT91SAM9263_ID_TCB },
 827 +               .clk            = { &tcb_clk, &tcb_clk, &tcb_clk },
 828 +       }
 829 +};
 830 +
 831 +#define at91sam9263_tc_init()  atmel_tc_init(at91sam9263_tcblocks, ARRAY_SIZE(at91sam9263_tcblocks))
 832 +
 833 +#else
 834 +#define at91sam9263_tc_init()  do {} while(0)
 835 +#endif
 836 +
 837 +
 838 +/* --------------------------------------------------------------------
 839   *  AT91SAM9263 processor initialization
 840   * -------------------------------------------------------------------- */
 841
 842 @@ -256,6 +314,9 @@ void __init at91sam9263_initialize(unsig
 843
 844         /* Register GPIO subsystem */
 845         at91_gpio_init(at91sam9263_gpio, 5);
 846 +
 847 +       /* Initialize the Timer/Counter blocks */
 848 +       at91sam9263_tc_init();
 849  }
 850
 851  /* --------------------------------------------------------------------
 852 @@ -268,34 +329,34 @@ void __init at91sam9263_initialize(unsig
 853  static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
 854         7,      /* Advanced Interrupt Controller (FIQ) */
 855         7,      /* System Peripherals */
 856 -       0,      /* Parallel IO Controller A */
 857 -       0,      /* Parallel IO Controller B */
 858 -       0,      /* Parallel IO Controller C, D and E */
 859 +       1,      /* Parallel IO Controller A */
 860 +       1,      /* Parallel IO Controller B */
 861 +       1,      /* Parallel IO Controller C, D and E */
 862         0,
 863         0,
 864 -       6,      /* USART 0 */
 865 -       6,      /* USART 1 */
 866 -       6,      /* USART 2 */
 867 +       5,      /* USART 0 */
 868 +       5,      /* USART 1 */
 869 +       5,      /* USART 2 */
 870         0,      /* Multimedia Card Interface 0 */
 871         0,      /* Multimedia Card Interface 1 */
 872 -       4,      /* CAN */
 873 -       0,      /* Two-Wire Interface */
 874 -       6,      /* Serial Peripheral Interface 0 */
 875 -       6,      /* Serial Peripheral Interface 1 */
 876 -       5,      /* Serial Synchronous Controller 0 */
 877 -       5,      /* Serial Synchronous Controller 1 */
 878 -       6,      /* AC97 Controller */
 879 +       3,      /* CAN */
 880 +       6,      /* Two-Wire Interface */
 881 +       5,      /* Serial Peripheral Interface 0 */
 882 +       5,      /* Serial Peripheral Interface 1 */
 883 +       4,      /* Serial Synchronous Controller 0 */
 884 +       4,      /* Serial Synchronous Controller 1 */
 885 +       5,      /* AC97 Controller */
 886         0,      /* Timer Counter 0, 1 and 2 */
 887         0,      /* Pulse Width Modulation Controller */
 888         3,      /* Ethernet */
 889         0,
 890         0,      /* 2D Graphic Engine */
 891 -       3,      /* USB Device Port */
 892 +       2,      /* USB Device Port */
 893         0,      /* Image Sensor Interface */
 894         3,      /* LDC Controller */
 895         0,      /* DMA Controller */
 896         0,
 897 -       3,      /* USB Host port */
 898 +       2,      /* USB Host port */
 899         0,      /* Advanced Interrupt Controller (IRQ0) */
 900         0,      /* Advanced Interrupt Controller (IRQ1) */
 901  };
 902 Index: linux-2.6.21.7/arch/arm/mach-at91/at91sam9263_devices.c
 903 ===================================================================
 904 --- linux-2.6.21.7.orig/arch/arm/mach-at91/at91sam9263_devices.c
 905 +++ linux-2.6.21.7/arch/arm/mach-at91/at91sam9263_devices.c
 906 @@ -13,6 +13,9 @@
 907  #include <asm/mach/map.h>
 908
 909  #include <linux/platform_device.h>
 910 +#include <linux/fb.h>
 911 +
 912 +#include <video/atmel_lcdc.h>
 913
 914  #include <asm/arch/board.h>
 915  #include <asm/arch/gpio.h>
 916 @@ -573,6 +576,180 @@ void __init at91_add_device_spi(struct s
 917
 918
 919  /* --------------------------------------------------------------------
 920 + *  AC97
 921 + * -------------------------------------------------------------------- */
 922 +
 923 +#if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
 924 +static u64 ac97_dmamask = 0xffffffffUL;
 925 +static struct atmel_ac97_data ac97_data;
 926 +
 927 +static struct resource ac97_resources[] = {
 928 +       [0] = {
 929 +               .start  = AT91SAM9263_BASE_AC97C,
 930 +               .end    = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
 931 +               .flags  = IORESOURCE_MEM,
 932 +       },
 933 +       [1] = {
 934 +               .start  = AT91SAM9263_ID_AC97C,
 935 +               .end    = AT91SAM9263_ID_AC97C,
 936 +               .flags  = IORESOURCE_IRQ,
 937 +       },
 938 +};
 939 +
 940 +static struct platform_device at91sam9263_ac97_device = {
 941 +       .name           = "ac97c",
 942 +       .id             = 1,
 943 +       .dev            = {
 944 +                               .dma_mask               = &ac97_dmamask,
 945 +                               .coherent_dma_mask      = 0xffffffff,
 946 +                               .platform_data          = &ac97_data,
 947 +       },
 948 +       .resource       = ac97_resources,
 949 +       .num_resources  = ARRAY_SIZE(ac97_resources),
 950 +};
 951 +
 952 +void __init at91_add_device_ac97(struct atmel_ac97_data *data)
 953 +{
 954 +       if (!data)
 955 +               return;
 956 +
 957 +       at91_set_A_periph(AT91_PIN_PB0, 0);     /* AC97FS */
 958 +       at91_set_A_periph(AT91_PIN_PB1, 0);     /* AC97CK */
 959 +       at91_set_A_periph(AT91_PIN_PB2, 0);     /* AC97TX */
 960 +       at91_set_A_periph(AT91_PIN_PB3, 0);     /* AC97RX */
 961 +
 962 +       /* reset */
 963 +       if (data->reset_pin)
 964 +               at91_set_gpio_output(data->reset_pin, 0);
 965 +
 966 +       ac97_data = *ek_data;
 967 +       platform_device_register(&at91sam9263_ac97_device);
 968 +}
 969 +#else
 970 +void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
 971 +#endif
 972 +
 973 +
 974 +/* --------------------------------------------------------------------
 975 + *  Image Sensor Interface
 976 + * -------------------------------------------------------------------- */
 977 +
 978 +#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
 979 +
 980 +struct resource isi_resources[] = {
 981 +       [0] = {
 982 +               .start  = AT91SAM9263_BASE_ISI,
 983 +               .end    = AT91SAM9263_BASE_ISI + SZ_16K - 1,
 984 +               .flags  = IORESOURCE_MEM,
 985 +       },
 986 +       [1] = {
 987 +               .start  = AT91SAM9263_ID_ISI,
 988 +               .end    = AT91SAM9263_ID_ISI,
 989 +               .flags  = IORESOURCE_IRQ,
 990 +       },
 991 +};
 992 +
 993 +static struct platform_device at91sam9263_isi_device = {
 994 +       .name           = "at91_isi",
 995 +       .id             = -1,
 996 +       .resource       = isi_resources,
 997 +       .num_resources  = ARRAY_SIZE(isi_resources),
 998 +};
 999 +
1000 +void __init at91_add_device_isi(void)
1001 +{
1002 +       at91_set_A_periph(AT91_PIN_PE0, 0);     /* ISI_D0 */
1003 +       at91_set_A_periph(AT91_PIN_PE1, 0);     /* ISI_D1 */
1004 +       at91_set_A_periph(AT91_PIN_PE2, 0);     /* ISI_D2 */
1005 +       at91_set_A_periph(AT91_PIN_PE3, 0);     /* ISI_D3 */
1006 +       at91_set_A_periph(AT91_PIN_PE4, 0);     /* ISI_D4 */
1007 +       at91_set_A_periph(AT91_PIN_PE5, 0);     /* ISI_D5 */
1008 +       at91_set_A_periph(AT91_PIN_PE6, 0);     /* ISI_D6 */
1009 +       at91_set_A_periph(AT91_PIN_PE7, 0);     /* ISI_D7 */
1010 +       at91_set_A_periph(AT91_PIN_PE8, 0);     /* ISI_PCK */
1011 +       at91_set_A_periph(AT91_PIN_PE9, 0);     /* ISI_HSYNC */
1012 +       at91_set_A_periph(AT91_PIN_PE10, 0);    /* ISI_VSYNC */
1013 +       at91_set_B_periph(AT91_PIN_PE11, 0);    /* ISI_MCK (PCK3) */
1014 +       at91_set_B_periph(AT91_PIN_PE12, 0);    /* ISI_PD8 */
1015 +       at91_set_B_periph(AT91_PIN_PE13, 0);    /* ISI_PD9 */
1016 +       at91_set_B_periph(AT91_PIN_PE14, 0);    /* ISI_PD10 */
1017 +       at91_set_B_periph(AT91_PIN_PE15, 0);    /* ISI_PD11 */
1018 +}
1019 +#else
1020 +void __init at91_add_device_isi(void) {}
1021 +#endif
1022 +
1023 +
1024 +/* --------------------------------------------------------------------
1025 + *  LCD Controller
1026 + * -------------------------------------------------------------------- */
1027 +
1028 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
1029 +static u64 lcdc_dmamask = 0xffffffffUL;
1030 +static struct atmel_lcdfb_info lcdc_data;
1031 +
1032 +static struct resource lcdc_resources[] = {
1033 +       [0] = {
1034 +               .start  = AT91SAM9263_LCDC_BASE,
1035 +               .end    = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
1036 +               .flags  = IORESOURCE_MEM,
1037 +       },
1038 +       [1] = {
1039 +               .start  = AT91SAM9263_ID_LCDC,
1040 +               .end    = AT91SAM9263_ID_LCDC,
1041 +               .flags  = IORESOURCE_IRQ,
1042 +       },
1043 +};
1044 +
1045 +static struct platform_device at91_lcdc_device = {
1046 +       .name           = "atmel_lcdfb",
1047 +       .id             = 0,
1048 +       .dev            = {
1049 +                               .dma_mask               = &lcdc_dmamask,
1050 +                               .coherent_dma_mask      = 0xffffffff,
1051 +                               .platform_data          = &lcdc_data,
1052 +       },
1053 +       .resource       = lcdc_resources,
1054 +       .num_resources  = ARRAY_SIZE(lcdc_resources),
1055 +};
1056 +
1057 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
1058 +{
1059 +       if (!data)
1060 +               return;
1061 +
1062 +       at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
1063 +       at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
1064 +       at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
1065 +       at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
1066 +       at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
1067 +       at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
1068 +       at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
1069 +       at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
1070 +       at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
1071 +       at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
1072 +       at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
1073 +       at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
1074 +       at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
1075 +       at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD13 */
1076 +       at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
1077 +       at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
1078 +       at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
1079 +       at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
1080 +       at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
1081 +       at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD21 */
1082 +       at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
1083 +       at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
1084 +
1085 +       lcdc_data = *data;
1086 +       platform_device_register(&at91_lcdc_device);
1087 +}
1088 +#else
1089 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1090 +#endif
1091 +
1092 +
1093 +/* --------------------------------------------------------------------
1094   *  LEDs
1095   * -------------------------------------------------------------------- */
1096
1097 @@ -594,6 +771,32 @@ void __init at91_init_leds(u8 cpu_led, u
1098  #endif
1099
1100
1101 +#if defined(CONFIG_NEW_LEDS)
1102 +
1103 +static struct platform_device at91_leds = {
1104 +       .name           = "at91_leds",
1105 +       .id             = -1,
1106 +};
1107 +
1108 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
1109 +{
1110 +       if (!nr)
1111 +               return;
1112 +
1113 +       at91_leds.dev.platform_data = leds;
1114 +
1115 +       for ( ; nr; nr--, leds++) {
1116 +               leds->index = nr;       /* first record stores number of leds */
1117 +               at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
1118 +       }
1119 +
1120 +       platform_device_register(&at91_leds);
1121 +}
1122 +#else
1123 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
1124 +#endif
1125 +
1126 +
1127  /* --------------------------------------------------------------------
1128   *  UART
1129   * -------------------------------------------------------------------- */
1130 Index: linux-2.6.21.7/arch/arm/mach-at91/at91sam9rl.c
1131 ===================================================================
1132 --- /dev/null
1133 +++ linux-2.6.21.7/arch/arm/mach-at91/at91sam9rl.c
1134 @@ -0,0 +1,366 @@
1135 +/*
1136 + * arch/arm/mach-at91/at91sam9rl.c
1137 + *
1138 + *  Copyright (C) 2005 SAN People
1139 + *  Copyright (C) 2007 Atmel Corporation
1140 + *
1141 + * This file is subject to the terms and conditions of the GNU General Public
1142 + * License.  See the file COPYING in the main directory of this archive for
1143 + * more details.
1144 + */
1145 +
1146 +#include <linux/module.h>
1147 +
1148 +#include <asm/mach/arch.h>
1149 +#include <asm/mach/map.h>
1150 +#include <asm/arch/cpu.h>
1151 +#include <asm/arch/at91sam9rl.h>
1152 +#include <asm/arch/at91_pmc.h>
1153 +#include <asm/arch/at91_rstc.h>
1154 +
1155 +#include "generic.h"
1156 +#include "clock.h"
1157 +
1158 +static struct map_desc at91sam9rl_io_desc[] __initdata = {
1159 +       {
1160 +               .virtual        = AT91_VA_BASE_SYS,
1161 +               .pfn            = __phys_to_pfn(AT91_BASE_SYS),
1162 +               .length         = SZ_16K,
1163 +               .type           = MT_DEVICE,
1164 +       },
1165 +};
1166 +
1167 +static struct map_desc at91sam9rl_sram_desc[] __initdata = {
1168 +       {
1169 +               .pfn            = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
1170 +               .type           = MT_DEVICE,
1171 +       }
1172 +};
1173 +
1174 +/* --------------------------------------------------------------------
1175 + *  Clocks
1176 + * -------------------------------------------------------------------- */
1177 +
1178 +/*
1179 + * The peripheral clocks.
1180 + */
1181 +static struct clk pioA_clk = {
1182 +       .name           = "pioA_clk",
1183 +       .pmc_mask       = 1 << AT91SAM9RL_ID_PIOA,
1184 +       .type           = CLK_TYPE_PERIPHERAL,
1185 +};
1186 +static struct clk pioB_clk = {
1187 +       .name           = "pioB_clk",
1188 +       .pmc_mask       = 1 << AT91SAM9RL_ID_PIOB,
1189 +       .type           = CLK_TYPE_PERIPHERAL,
1190 +};
1191 +static struct clk pioC_clk = {
1192 +       .name           = "pioC_clk",
1193 +       .pmc_mask       = 1 << AT91SAM9RL_ID_PIOC,
1194 +       .type           = CLK_TYPE_PERIPHERAL,
1195 +};
1196 +static struct clk pioD_clk = {
1197 +       .name           = "pioD_clk",
1198 +       .pmc_mask       = 1 << AT91SAM9RL_ID_PIOD,
1199 +       .type           = CLK_TYPE_PERIPHERAL,
1200 +};
1201 +static struct clk usart0_clk = {
1202 +       .name           = "usart0_clk",
1203 +       .pmc_mask       = 1 << AT91SAM9RL_ID_US0,
1204 +       .type           = CLK_TYPE_PERIPHERAL,
1205 +};
1206 +static struct clk usart1_clk = {
1207 +       .name           = "usart1_clk",
1208 +       .pmc_mask       = 1 << AT91SAM9RL_ID_US1,
1209 +       .type           = CLK_TYPE_PERIPHERAL,
1210 +};
1211 +static struct clk usart2_clk = {
1212 +       .name           = "usart2_clk",
1213 +       .pmc_mask       = 1 << AT91SAM9RL_ID_US2,
1214 +       .type           = CLK_TYPE_PERIPHERAL,
1215 +};
1216 +static struct clk usart3_clk = {
1217 +       .name           = "usart3_clk",
1218 +       .pmc_mask       = 1 << AT91SAM9RL_ID_US3,
1219 +       .type           = CLK_TYPE_PERIPHERAL,
1220 +};
1221 +static struct clk mmc_clk = {
1222 +       .name           = "mci_clk",
1223 +       .pmc_mask       = 1 << AT91SAM9RL_ID_MCI,
1224 +       .type           = CLK_TYPE_PERIPHERAL,
1225 +};
1226 +static struct clk twi0_clk = {
1227 +       .name           = "twi0_clk",
1228 +       .pmc_mask       = 1 << AT91SAM9RL_ID_TWI0,
1229 +       .type           = CLK_TYPE_PERIPHERAL,
1230 +};
1231 +static struct clk twi1_clk = {
1232 +       .name           = "twi1_clk",
1233 +       .pmc_mask       = 1 << AT91SAM9RL_ID_TWI1,
1234 +       .type           = CLK_TYPE_PERIPHERAL,
1235 +};
1236 +static struct clk spi_clk = {
1237 +       .name           = "spi_clk",
1238 +       .pmc_mask       = 1 << AT91SAM9RL_ID_SPI,
1239 +       .type           = CLK_TYPE_PERIPHERAL,
1240 +};
1241 +static struct clk ssc0_clk = {
1242 +       .name           = "ssc0_clk",
1243 +       .pmc_mask       = 1 << AT91SAM9RL_ID_SSC0,
1244 +       .type           = CLK_TYPE_PERIPHERAL,
1245 +};
1246 +static struct clk ssc1_clk = {
1247 +       .name           = "ssc1_clk",
1248 +       .pmc_mask       = 1 << AT91SAM9RL_ID_SSC1,
1249 +       .type           = CLK_TYPE_PERIPHERAL,
1250 +};
1251 +static struct clk tc0_clk = {
1252 +       .name           = "tc0_clk",
1253 +       .pmc_mask       = 1 << AT91SAM9RL_ID_TC0,
1254 +       .type           = CLK_TYPE_PERIPHERAL,
1255 +};
1256 +static struct clk tc1_clk = {
1257 +       .name           = "tc1_clk",
1258 +       .pmc_mask       = 1 << AT91SAM9RL_ID_TC1,
1259 +       .type           = CLK_TYPE_PERIPHERAL,
1260 +};
1261 +static struct clk tc2_clk = {
1262 +       .name           = "tc2_clk",
1263 +       .pmc_mask       = 1 << AT91SAM9RL_ID_TC2,
1264 +       .type           = CLK_TYPE_PERIPHERAL,
1265 +};
1266 +static struct clk pwmc_clk = {
1267 +       .name           = "pwmc_clk",
1268 +       .pmc_mask       = 1 << AT91SAM9RL_ID_PWMC,
1269 +       .type           = CLK_TYPE_PERIPHERAL,
1270 +};
1271 +static struct clk tsc_clk = {
1272 +       .name           = "tsc_clk",
1273 +       .pmc_mask       = 1 << AT91SAM9RL_ID_TSC,
1274 +       .type           = CLK_TYPE_PERIPHERAL,
1275 +};
1276 +static struct clk dma_clk = {
1277 +       .name           = "dma_clk",
1278 +       .pmc_mask       = 1 << AT91SAM9RL_ID_DMA,
1279 +       .type           = CLK_TYPE_PERIPHERAL,
1280 +};
1281 +static struct clk udphs_clk = {
1282 +       .name           = "udphs_clk",
1283 +       .pmc_mask       = 1 << AT91SAM9RL_ID_UDPHS,
1284 +       .type           = CLK_TYPE_PERIPHERAL,
1285 +};
1286 +static struct clk lcdc_clk = {
1287 +       .name           = "lcdc_clk",
1288 +       .pmc_mask       = 1 << AT91SAM9RL_ID_LCDC,
1289 +       .type           = CLK_TYPE_PERIPHERAL,
1290 +};
1291 +static struct clk ac97_clk = {
1292 +       .name           = "ac97_clk",
1293 +       .pmc_mask       = 1 << AT91SAM9RL_ID_AC97C,
1294 +       .type           = CLK_TYPE_PERIPHERAL,
1295 +};
1296 +
1297 +static struct clk *periph_clocks[] __initdata = {
1298 +       &pioA_clk,
1299 +       &pioB_clk,
1300 +       &pioC_clk,
1301 +       &pioD_clk,
1302 +       &usart0_clk,
1303 +       &usart1_clk,
1304 +       &usart2_clk,
1305 +       &usart3_clk,
1306 +       &mmc_clk,
1307 +       &twi0_clk,
1308 +       &twi1_clk,
1309 +       &spi_clk,
1310 +       &ssc0_clk,
1311 +       &ssc1_clk,
1312 +       &tc0_clk,
1313 +       &tc1_clk,
1314 +       &tc2_clk,
1315 +       &pwmc_clk,
1316 +       &tsc_clk,
1317 +       &dma_clk,
1318 +       &udphs_clk,
1319 +       &lcdc_clk,
1320 +       &ac97_clk,
1321 +       // irq0
1322 +};
1323 +
1324 +/*
1325 + * The two programmable clocks.
1326 + * You must configure pin multiplexing to bring these signals out.
1327 + */
1328 +static struct clk pck0 = {
1329 +       .name           = "pck0",
1330 +       .pmc_mask       = AT91_PMC_PCK0,
1331 +       .type           = CLK_TYPE_PROGRAMMABLE,
1332 +       .id             = 0,
1333 +};
1334 +static struct clk pck1 = {
1335 +       .name           = "pck1",
1336 +       .pmc_mask       = AT91_PMC_PCK1,
1337 +       .type           = CLK_TYPE_PROGRAMMABLE,
1338 +       .id             = 1,
1339 +};
1340 +
1341 +static void __init at91sam9rl_register_clocks(void)
1342 +{
1343 +       int i;
1344 +
1345 +       for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
1346 +               clk_register(periph_clocks[i]);
1347 +
1348 +       clk_register(&pck0);
1349 +       clk_register(&pck1);
1350 +}
1351 +
1352 +/* --------------------------------------------------------------------
1353 + *  GPIO
1354 + * -------------------------------------------------------------------- */
1355 +
1356 +static struct at91_gpio_bank at91sam9rl_gpio[] = {
1357 +       {
1358 +               .id             = AT91SAM9RL_ID_PIOA,
1359 +               .offset         = AT91_PIOA,
1360 +               .clock          = &pioA_clk,
1361 +       }, {
1362 +               .id             = AT91SAM9RL_ID_PIOB,
1363 +               .offset         = AT91_PIOB,
1364 +               .clock          = &pioB_clk,
1365 +       }, {
1366 +               .id             = AT91SAM9RL_ID_PIOC,
1367 +               .offset         = AT91_PIOC,
1368 +               .clock          = &pioC_clk,
1369 +       }, {
1370 +               .id             = AT91SAM9RL_ID_PIOD,
1371 +               .offset         = AT91_PIOD,
1372 +               .clock          = &pioD_clk,
1373 +       }
1374 +};
1375 +
1376 +static void at91sam9rl_reset(void)
1377 +{
1378 +       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
1379 +}
1380 +
1381 +
1382 +/* --------------------------------------------------------------------
1383 + *  Timer/Counter library initialization
1384 + * -------------------------------------------------------------------- */
1385 +#ifdef CONFIG_ATMEL_TCLIB
1386 +
1387 +#include "tclib.h"
1388 +
1389 +static struct atmel_tcblock at91sam9rl_tcblocks[] = {
1390 +       [0] = {
1391 +               .physaddr       = AT91SAM9RL_BASE_TCB0,
1392 +               .irq            = { AT91SAM9RL_ID_TC0, AT91SAM9RL_ID_TC1, AT91SAM9RL_ID_TC2 },
1393 +               .clk            = { &tc0_clk, &tc1_clk, &tc2_clk },
1394 +       }
1395 +};
1396 +
1397 +#define at91sam9rl_tc_init()   atmel_tc_init(at91sam9rl_tcblocks, ARRAY_SIZE(at91sam9rl_tcblocks))
1398 +
1399 +#else
1400 +#define at91sam9rl_tc_init()   do {} while(0)
1401 +#endif
1402 +
1403 +
1404 +/* --------------------------------------------------------------------
1405 + *  AT91SAM9RL processor initialization
1406 + * -------------------------------------------------------------------- */
1407 +
1408 +void __init at91sam9rl_initialize(unsigned long main_clock)
1409 +{
1410 +       unsigned long cidr, sram_size;
1411 +
1412 +       /* Map peripherals */
1413 +       iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc));
1414 +
1415 +       cidr = at91_sys_read(AT91_DBGU_CIDR);
1416 +
1417 +       switch (cidr & AT91_CIDR_SRAMSIZ) {
1418 +               case AT91_CIDR_SRAMSIZ_32K:
1419 +                       sram_size = 2 * SZ_16K;
1420 +                       break;
1421 +               case AT91_CIDR_SRAMSIZ_16K:
1422 +               default:
1423 +                       sram_size = SZ_16K;
1424 +       }
1425 +
1426 +       at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
1427 +       at91sam9rl_sram_desc->length = sram_size;
1428 +
1429 +       /* Map SRAM */
1430 +       iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
1431 +
1432 +       at91_arch_reset = at91sam9rl_reset;
1433 +       at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
1434 +
1435 +       /* Init clock subsystem */
1436 +       at91_clock_init(main_clock);
1437 +
1438 +       /* Register the processor-specific clocks */
1439 +       at91sam9rl_register_clocks();
1440 +
1441 +       /* Register GPIO subsystem */
1442 +       at91_gpio_init(at91sam9rl_gpio, 4);
1443 +
1444 +       /* Initialize the Timer/Counter blocks */
1445 +       at91sam9rl_tc_init();
1446 +}
1447 +
1448 +/* --------------------------------------------------------------------
1449 + *  Interrupt initialization
1450 + * -------------------------------------------------------------------- */
1451 +
1452 +/*
1453 + * The default interrupt priority levels (0 = lowest, 7 = highest).
1454 + */
1455 +static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
1456 +       7,      /* Advanced Interrupt Controller */
1457 +       7,      /* System Peripherals */
1458 +       1,      /* Parallel IO Controller A */
1459 +       1,      /* Parallel IO Controller B */
1460 +       1,      /* Parallel IO Controller C */
1461 +       1,      /* Parallel IO Controller D */
1462 +       5,      /* USART 0 */
1463 +       5,      /* USART 1 */
1464 +       5,      /* USART 2 */
1465 +       5,      /* USART 3 */
1466 +       0,      /* Multimedia Card Interface */
1467 +       6,      /* Two-Wire Interface 0 */
1468 +       6,      /* Two-Wire Interface 1 */
1469 +       5,      /* Serial Peripheral Interface */
1470 +       4,      /* Serial Synchronous Controller 0 */
1471 +       4,      /* Serial Synchronous Controller 1 */
1472 +       0,      /* Timer Counter 0 */
1473 +       0,      /* Timer Counter 1 */
1474 +       0,      /* Timer Counter 2 */
1475 +       0,
1476 +       0,      /* Touch Screen Controller */
1477 +       0,      /* DMA Controller */
1478 +       2,      /* USB Device High speed port */
1479 +       2,      /* LCD Controller */
1480 +       6,      /* AC97 Controller */
1481 +       0,
1482 +       0,
1483 +       0,
1484 +       0,
1485 +       0,
1486 +       0,
1487 +       0,      /* Advanced Interrupt Controller */
1488 +};
1489 +
1490 +void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])
1491 +{
1492 +       if (!priority)
1493 +               priority = at91sam9rl_default_irq_priority;
1494 +
1495 +       /* Initialize the AIC interrupt controller */
1496 +       at91_aic_init(priority);
1497 +
1498 +       /* Enable GPIO interrupts */
1499 +       at91_gpio_irq_setup();
1500 +}
1501 Index: linux-2.6.21.7/arch/arm/mach-at91/at91sam9rl_devices.c
1502 ===================================================================
1503 --- /dev/null
1504 +++ linux-2.6.21.7/arch/arm/mach-at91/at91sam9rl_devices.c
1505 @@ -0,0 +1,660 @@
1506 +/*
1507 + *  Copyright (C) 2007 Atmel Corporation
1508 + *
1509 + * This file is subject to the terms and conditions of the GNU General Public
1510 + * License.  See the file COPYING in the main directory of this archive for
1511 + * more details.
1512 + */
1513 +
1514 +#include <asm/mach/arch.h>
1515 +#include <asm/mach/map.h>
1516 +
1517 +#include <linux/platform_device.h>
1518 +#include <linux/fb.h>
1519 +
1520 +#include <video/atmel_lcdc.h>
1521 +
1522 +#include <asm/arch/board.h>
1523 +#include <asm/arch/gpio.h>
1524 +#include <asm/arch/at91sam9rl.h>
1525 +#include <asm/arch/at91sam9rl_matrix.h>
1526 +#include <asm/arch/at91sam926x_mc.h>
1527 +
1528 +#include "generic.h"
1529 +
1530 +#define SZ_512 0x00000200
1531 +#define SZ_256 0x00000100
1532 +#define SZ_16  0x00000010
1533 +
1534 +
1535 +/* --------------------------------------------------------------------
1536 + *  MMC / SD
1537 + * -------------------------------------------------------------------- */
1538 +
1539 +#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
1540 +static u64 mmc_dmamask = 0xffffffffUL;
1541 +static struct at91_mmc_data mmc_data;
1542 +
1543 +static struct resource mmc_resources[] = {
1544 +       [0] = {
1545 +               .start  = AT91SAM9RL_BASE_MCI,
1546 +               .end    = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
1547 +               .flags  = IORESOURCE_MEM,
1548 +       },
1549 +       [1] = {
1550 +               .start  = AT91SAM9RL_ID_MCI,
1551 +               .end    = AT91SAM9RL_ID_MCI,
1552 +               .flags  = IORESOURCE_IRQ,
1553 +       },
1554 +};
1555 +
1556 +static struct platform_device at91sam9rl_mmc_device = {
1557 +       .name           = "at91_mci",
1558 +       .id             = -1,
1559 +       .dev            = {
1560 +                               .dma_mask               = &mmc_dmamask,
1561 +                               .coherent_dma_mask      = 0xffffffff,
1562 +                               .platform_data          = &mmc_data,
1563 +       },
1564 +       .resource       = mmc_resources,
1565 +       .num_resources  = ARRAY_SIZE(mmc_resources),
1566 +};
1567 +
1568 +void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
1569 +{
1570 +       if (!data)
1571 +               return;
1572 +
1573 +       /* input/irq */
1574 +       if (data->det_pin) {
1575 +               at91_set_gpio_input(data->det_pin, 1);
1576 +               at91_set_deglitch(data->det_pin, 1);
1577 +       }
1578 +       if (data->wp_pin)
1579 +               at91_set_gpio_input(data->wp_pin, 1);
1580 +       if (data->vcc_pin)
1581 +               at91_set_gpio_output(data->vcc_pin, 0);
1582 +
1583 +       /* CLK */
1584 +       at91_set_A_periph(AT91_PIN_PA2, 0);
1585 +
1586 +       /* CMD */
1587 +       at91_set_A_periph(AT91_PIN_PA1, 1);
1588 +
1589 +       /* DAT0, maybe DAT1..DAT3 */
1590 +       at91_set_A_periph(AT91_PIN_PA0, 1);
1591 +       if (data->wire4) {
1592 +               at91_set_A_periph(AT91_PIN_PA3, 1);
1593 +               at91_set_A_periph(AT91_PIN_PA4, 1);
1594 +               at91_set_A_periph(AT91_PIN_PA5, 1);
1595 +       }
1596 +
1597 +       mmc_data = *data;
1598 +       platform_device_register(&at91sam9rl_mmc_device);
1599 +}
1600 +#else
1601 +void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
1602 +#endif
1603 +
1604 +
1605 +/* --------------------------------------------------------------------
1606 + *  NAND / SmartMedia
1607 + * -------------------------------------------------------------------- */
1608 +
1609 +#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
1610 +static struct at91_nand_data nand_data;
1611 +
1612 +#define NAND_BASE      AT91_CHIPSELECT_3
1613 +
1614 +static struct resource nand_resources[] = {
1615 +       {
1616 +               .start  = NAND_BASE,
1617 +               .end    = NAND_BASE + SZ_256M - 1,
1618 +               .flags  = IORESOURCE_MEM,
1619 +       }
1620 +};
1621 +
1622 +static struct platform_device at91_nand_device = {
1623 +       .name           = "at91_nand",
1624 +       .id             = -1,
1625 +       .dev            = {
1626 +                               .platform_data  = &nand_data,
1627 +       },
1628 +       .resource       = nand_resources,
1629 +       .num_resources  = ARRAY_SIZE(nand_resources),
1630 +};
1631 +
1632 +void __init at91_add_device_nand(struct at91_nand_data *data)
1633 +{
1634 +       unsigned long csa;
1635 +
1636 +       if (!data)
1637 +               return;
1638 +
1639 +       csa = at91_sys_read(AT91_MATRIX_EBICSA);
1640 +       at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
1641 +
1642 +       /* set the bus interface characteristics */
1643 +       at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
1644 +                       | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
1645 +
1646 +       at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
1647 +                       | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
1648 +
1649 +       at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
1650 +
1651 +       at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
1652 +
1653 +       /* enable pin */
1654 +       if (data->enable_pin)
1655 +               at91_set_gpio_output(data->enable_pin, 1);
1656 +
1657 +       /* ready/busy pin */
1658 +       if (data->rdy_pin)
1659 +               at91_set_gpio_input(data->rdy_pin, 1);
1660 +
1661 +       /* card detect pin */
1662 +       if (data->det_pin)
1663 +               at91_set_gpio_input(data->det_pin, 1);
1664 +
1665 +       at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
1666 +       at91_set_A_periph(AT91_PIN_PB5, 0);             /* NANDWE */
1667 +
1668 +       nand_data = *data;
1669 +       platform_device_register(&at91_nand_device);
1670 +}
1671 +
1672 +#else
1673 +void __init at91_add_device_nand(struct at91_nand_data *data) {}
1674 +#endif
1675 +
1676 +
1677 +/* --------------------------------------------------------------------
1678 + *  TWI (i2c)
1679 + * -------------------------------------------------------------------- */
1680 +
1681 +#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
1682 +
1683 +static struct resource twi_resources[] = {
1684 +       [0] = {
1685 +               .start  = AT91SAM9RL_BASE_TWI0,
1686 +               .end    = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
1687 +               .flags  = IORESOURCE_MEM,
1688 +       },
1689 +       [1] = {
1690 +               .start  = AT91SAM9RL_ID_TWI0,
1691 +               .end    = AT91SAM9RL_ID_TWI0,
1692 +               .flags  = IORESOURCE_IRQ,
1693 +       },
1694 +};
1695 +
1696 +static struct platform_device at91sam9rl_twi_device = {
1697 +       .name           = "at91_i2c",
1698 +       .id             = -1,
1699 +       .resource       = twi_resources,
1700 +       .num_resources  = ARRAY_SIZE(twi_resources),
1701 +};
1702 +
1703 +void __init at91_add_device_i2c(void)
1704 +{
1705 +       /* pins used for TWI interface */
1706 +       at91_set_A_periph(AT91_PIN_PA23, 0);            /* TWD */
1707 +       at91_set_multi_drive(AT91_PIN_PA23, 1);
1708 +
1709 +       at91_set_A_periph(AT91_PIN_PA24, 0);            /* TWCK */
1710 +       at91_set_multi_drive(AT91_PIN_PA24, 1);
1711 +
1712 +       platform_device_register(&at91sam9rl_twi_device);
1713 +}
1714 +#else
1715 +void __init at91_add_device_i2c(void) {}
1716 +#endif
1717 +
1718 +
1719 +/* --------------------------------------------------------------------
1720 + *  SPI
1721 + * -------------------------------------------------------------------- */
1722 +
1723 +#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
1724 +static u64 spi_dmamask = 0xffffffffUL;
1725 +
1726 +static struct resource spi_resources[] = {
1727 +       [0] = {
1728 +               .start  = AT91SAM9RL_BASE_SPI,
1729 +               .end    = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
1730 +               .flags  = IORESOURCE_MEM,
1731 +       },
1732 +       [1] = {
1733 +               .start  = AT91SAM9RL_ID_SPI,
1734 +               .end    = AT91SAM9RL_ID_SPI,
1735 +               .flags  = IORESOURCE_IRQ,
1736 +       },
1737 +};
1738 +
1739 +static struct platform_device at91sam9rl_spi_device = {
1740 +       .name           = "atmel_spi",
1741 +       .id             = 0,
1742 +       .dev            = {
1743 +                               .dma_mask               = &spi_dmamask,
1744 +                               .coherent_dma_mask      = 0xffffffff,
1745 +       },
1746 +       .resource       = spi_resources,
1747 +       .num_resources  = ARRAY_SIZE(spi_resources),
1748 +};
1749 +
1750 +static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
1751 +
1752 +
1753 +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
1754 +{
1755 +       int i;
1756 +       unsigned long cs_pin;
1757 +
1758 +       at91_set_A_periph(AT91_PIN_PA25, 0);    /* MISO */
1759 +       at91_set_A_periph(AT91_PIN_PA26, 0);    /* MOSI */
1760 +       at91_set_A_periph(AT91_PIN_PA27, 0);    /* SPCK */
1761 +
1762 +       /* Enable SPI chip-selects */
1763 +       for (i = 0; i < nr_devices; i++) {
1764 +               if (devices[i].controller_data)
1765 +                       cs_pin = (unsigned long) devices[i].controller_data;
1766 +               else
1767 +                       cs_pin = spi_standard_cs[devices[i].chip_select];
1768 +
1769 +               /* enable chip-select pin */
1770 +               at91_set_gpio_output(cs_pin, 1);
1771 +
1772 +               /* pass chip-select pin to driver */
1773 +               devices[i].controller_data = (void *) cs_pin;
1774 +       }
1775 +
1776 +       spi_register_board_info(devices, nr_devices);
1777 +       platform_device_register(&at91sam9rl_spi_device);
1778 +}
1779 +#else
1780 +void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
1781 +#endif
1782 +
1783 +
1784 +/* --------------------------------------------------------------------
1785 + *  LCD Controller
1786 + * -------------------------------------------------------------------- */
1787 +
1788 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
1789 +static u64 lcdc_dmamask = 0xffffffffUL;
1790 +static struct atmel_lcdfb_info lcdc_data;
1791 +
1792 +static struct resource lcdc_resources[] = {
1793 +       [0] = {
1794 +               .start  = AT91SAM9RL_LCDC_BASE,
1795 +               .end    = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
1796 +               .flags  = IORESOURCE_MEM,
1797 +       },
1798 +       [1] = {
1799 +               .start  = AT91SAM9RL_ID_LCDC,
1800 +               .end    = AT91SAM9RL_ID_LCDC,
1801 +               .flags  = IORESOURCE_IRQ,
1802 +       },
1803 +#if defined(CONFIG_FB_INTSRAM)
1804 +       [2] = {
1805 +               .start  = AT91SAM9RL_SRAM_BASE,
1806 +               .end    = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
1807 +               .flags  = IORESOURCE_MEM,
1808 +       },
1809 +#endif
1810 +};
1811 +
1812 +static struct platform_device at91_lcdc_device = {
1813 +       .name           = "atmel_lcdfb",
1814 +       .id             = 0,
1815 +       .dev            = {
1816 +                               .dma_mask               = &lcdc_dmamask,
1817 +                               .coherent_dma_mask      = 0xffffffff,
1818 +                               .platform_data          = &lcdc_data,
1819 +       },
1820 +       .resource       = lcdc_resources,
1821 +       .num_resources  = ARRAY_SIZE(lcdc_resources),
1822 +};
1823 +
1824 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
1825 +{
1826 +       if (!data) {
1827 +               return;
1828 +       }
1829 +
1830 +#warning "Check this"
1831 +       at91_set_B_periph(AT91_PIN_PC5, 0);     /* LCDHSYNC */
1832 +       at91_set_B_periph(AT91_PIN_PC6, 0);     /* LCDDOTCK */
1833 +       at91_set_B_periph(AT91_PIN_PC7, 0);     /* LCDDEN */
1834 +       at91_set_B_periph(AT91_PIN_PC3, 0);     /* LCDCC */
1835 +       at91_set_B_periph(AT91_PIN_PC9, 0);     /* LCDD3 */
1836 +       at91_set_B_periph(AT91_PIN_PC10, 0);    /* LCDD4 */
1837 +       at91_set_B_periph(AT91_PIN_PC11, 0);    /* LCDD5 */
1838 +       at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD6 */
1839 +       at91_set_B_periph(AT91_PIN_PC13, 0);    /* LCDD7 */
1840 +       at91_set_B_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
1841 +       at91_set_B_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
1842 +       at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
1843 +       at91_set_B_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
1844 +       at91_set_B_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
1845 +       at91_set_B_periph(AT91_PIN_PC20, 0);    /* LCDD18 */
1846 +       at91_set_B_periph(AT91_PIN_PC21, 0);    /* LCDD19 */
1847 +       at91_set_B_periph(AT91_PIN_PC22, 0);    /* LCDD20 */
1848 +       at91_set_B_periph(AT91_PIN_PC23, 0);    /* LCDD21 */
1849 +       at91_set_B_periph(AT91_PIN_PC24, 0);    /* LCDD22 */
1850 +       at91_set_B_periph(AT91_PIN_PC25, 0);    /* LCDD23 */
1851 +
1852 +       lcdc_data = *data;
1853 +       platform_device_register(&at91_lcdc_device);
1854 +}
1855 +#else
1856 +void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1857 +#endif
1858 +
1859 +
1860 +/* --------------------------------------------------------------------
1861 + *  LEDs
1862 + * -------------------------------------------------------------------- */
1863 +
1864 +#if defined(CONFIG_LEDS)
1865 +u8 at91_leds_cpu;
1866 +u8 at91_leds_timer;
1867 +
1868 +void __init at91_init_leds(u8 cpu_led, u8 timer_led)
1869 +{
1870 +       /* Enable GPIO to access the LEDs */
1871 +       at91_set_gpio_output(cpu_led, 1);
1872 +       at91_set_gpio_output(timer_led, 1);
1873 +
1874 +       at91_leds_cpu   = cpu_led;
1875 +       at91_leds_timer = timer_led;
1876 +}
1877 +#else
1878 +void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
1879 +#endif
1880 +
1881 +
1882 +#if defined(CONFIG_NEW_LEDS)
1883 +
1884 +static struct platform_device at91_leds = {
1885 +       .name           = "at91_leds",
1886 +       .id             = -1,
1887 +};
1888 +
1889 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr)
1890 +{
1891 +       if (!nr)
1892 +               return;
1893 +
1894 +       at91_leds.dev.platform_data = leds;
1895 +
1896 +       for ( ; nr; nr--, leds++) {
1897 +               leds->index = nr;       /* first record stores number of leds */
1898 +               at91_set_gpio_output(leds->gpio, (leds->flags & 1) == 0);
1899 +       }
1900 +
1901 +       platform_device_register(&at91_leds);
1902 +}
1903 +#else
1904 +void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr) {}
1905 +#endif
1906 +
1907 +
1908 +/* --------------------------------------------------------------------
1909 + *  UART
1910 + * -------------------------------------------------------------------- */
1911 +
1912 +#if defined(CONFIG_SERIAL_ATMEL)
1913 +static struct resource dbgu_resources[] = {
1914 +       [0] = {
1915 +               .start  = AT91_VA_BASE_SYS + AT91_DBGU,
1916 +               .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1917 +               .flags  = IORESOURCE_MEM,
1918 +       },
1919 +       [1] = {
1920 +               .start  = AT91_ID_SYS,
1921 +               .end    = AT91_ID_SYS,
1922 +               .flags  = IORESOURCE_IRQ,
1923 +       },
1924 +};
1925 +
1926 +static struct atmel_uart_data dbgu_data = {
1927 +       .use_dma_tx     = 0,
1928 +       .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
1929 +       .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1930 +};
1931 +
1932 +static struct platform_device at91sam9rl_dbgu_device = {
1933 +       .name           = "atmel_usart",
1934 +       .id             = 0,
1935 +       .dev            = {
1936 +                               .platform_data  = &dbgu_data,
1937 +                               .coherent_dma_mask = 0xffffffff,
1938 +       },
1939 +       .resource       = dbgu_resources,
1940 +       .num_resources  = ARRAY_SIZE(dbgu_resources),
1941 +};
1942 +
1943 +static inline void configure_dbgu_pins(void)
1944 +{
1945 +       at91_set_A_periph(AT91_PIN_PA21, 0);            /* DRXD */
1946 +       at91_set_A_periph(AT91_PIN_PA22, 1);            /* DTXD */
1947 +}
1948 +
1949 +static struct resource uart0_resources[] = {
1950 +       [0] = {
1951 +               .start  = AT91SAM9RL_BASE_US0,
1952 +               .end    = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
1953 +               .flags  = IORESOURCE_MEM,
1954 +       },
1955 +       [1] = {
1956 +               .start  = AT91SAM9RL_ID_US0,
1957 +               .end    = AT91SAM9RL_ID_US0,
1958 +               .flags  = IORESOURCE_IRQ,
1959 +       },
1960 +};
1961 +
1962 +static struct atmel_uart_data uart0_data = {
1963 +       .use_dma_tx     = 1,
1964 +       .use_dma_rx     = 1,
1965 +};
1966 +
1967 +static struct platform_device at91sam9rl_uart0_device = {
1968 +       .name           = "atmel_usart",
1969 +       .id             = 1,
1970 +       .dev            = {
1971 +                               .platform_data  = &uart0_data,
1972 +                               .coherent_dma_mask = 0xffffffff,
1973 +       },
1974 +       .resource       = uart0_resources,
1975 +       .num_resources  = ARRAY_SIZE(uart0_resources),
1976 +};
1977 +
1978 +static inline void configure_usart0_pins(void)
1979 +{
1980 +       at91_set_A_periph(AT91_PIN_PA6, 1);             /* TXD0 */
1981 +       at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
1982 +       at91_set_A_periph(AT91_PIN_PA9, 0);             /* RTS0 */
1983 +       at91_set_A_periph(AT91_PIN_PA10, 0);            /* CTS0 */
1984 +}
1985 +
1986 +static struct resource uart1_resources[] = {
1987 +       [0] = {
1988 +               .start  = AT91SAM9RL_BASE_US1,
1989 +               .end    = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
1990 +               .flags  = IORESOURCE_MEM,
1991 +       },
1992 +       [1] = {
1993 +               .start  = AT91SAM9RL_ID_US1,
1994 +               .end    = AT91SAM9RL_ID_US1,
1995 +               .flags  = IORESOURCE_IRQ,
1996 +       },
1997 +};
1998 +
1999 +static struct atmel_uart_data uart1_data = {
2000 +       .use_dma_tx     = 1,
2001 +       .use_dma_rx     = 1,
2002 +};
2003 +
2004 +static struct platform_device at91sam9rl_uart1_device = {
2005 +       .name           = "atmel_usart",
2006 +       .id             = 2,
2007 +       .dev            = {
2008 +                               .platform_data  = &uart1_data,
2009 +                               .coherent_dma_mask = 0xffffffff,
2010 +       },
2011 +       .resource       = uart1_resources,
2012 +       .num_resources  = ARRAY_SIZE(uart1_resources),
2013 +};
2014 +
2015 +static inline void configure_usart1_pins(void)
2016 +{
2017 +       at91_set_A_periph(AT91_PIN_PA11, 1);            /* TXD1 */
2018 +       at91_set_A_periph(AT91_PIN_PA12, 0);            /* RXD1 */
2019 +}
2020 +
2021 +static struct resource uart2_resources[] = {
2022 +       [0] = {
2023 +               .start  = AT91SAM9RL_BASE_US2,
2024 +               .end    = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
2025 +               .flags  = IORESOURCE_MEM,
2026 +       },
2027 +       [1] = {
2028 +               .start  = AT91SAM9RL_ID_US2,
2029 +               .end    = AT91SAM9RL_ID_US2,
2030 +               .flags  = IORESOURCE_IRQ,
2031 +       },
2032 +};
2033 +
2034 +static struct atmel_uart_data uart2_data = {
2035 +       .use_dma_tx     = 1,
2036 +       .use_dma_rx     = 1,
2037 +};
2038 +
2039 +static struct platform_device at91sam9rl_uart2_device = {
2040 +       .name           = "atmel_usart",
2041 +       .id             = 3,
2042 +       .dev            = {
2043 +                               .platform_data  = &uart2_data,
2044 +                               .coherent_dma_mask = 0xffffffff,
2045 +       },
2046 +       .resource       = uart2_resources,
2047 +       .num_resources  = ARRAY_SIZE(uart2_resources),
2048 +};
2049 +
2050 +static inline void configure_usart2_pins(void)
2051 +{
2052 +       at91_set_A_periph(AT91_PIN_PA13, 1);            /* TXD2 */
2053 +       at91_set_A_periph(AT91_PIN_PA14, 0);            /* RXD2 */
2054 +}
2055 +
2056 +static struct resource uart3_resources[] = {
2057 +       [0] = {
2058 +               .start  = AT91SAM9RL_BASE_US3,
2059 +               .end    = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
2060 +               .flags  = IORESOURCE_MEM,
2061 +       },
2062 +       [1] = {
2063 +               .start  = AT91SAM9RL_ID_US3,
2064 +               .end    = AT91SAM9RL_ID_US3,
2065 +               .flags  = IORESOURCE_IRQ,
2066 +       },
2067 +};
2068 +
2069 +static struct atmel_uart_data uart3_data = {
2070 +       .use_dma_tx     = 1,
2071 +       .use_dma_rx     = 1,
2072 +};
2073 +
2074 +static struct platform_device at91sam9rl_uart3_device = {
2075 +       .name           = "atmel_usart",
2076 +       .id             = 4,
2077 +       .dev            = {
2078 +                               .platform_data  = &uart3_data,
2079 +                               .coherent_dma_mask = 0xffffffff,
2080 +       },
2081 +       .resource       = uart3_resources,
2082 +       .num_resources  = ARRAY_SIZE(uart3_resources),
2083 +};
2084 +
2085 +static inline void configure_usart3_pins(void)
2086 +{
2087 +       at91_set_A_periph(AT91_PIN_PB0, 1);             /* TXD3 */
2088 +       at91_set_A_periph(AT91_PIN_PB1, 0);             /* RXD3 */
2089 +}
2090 +
2091 +struct platform_device *at91_uarts[ATMEL_MAX_UART];    /* the UARTs to use */
2092 +struct platform_device *atmel_default_console_device;  /* the serial console device */
2093 +
2094 +void __init at91_init_serial(struct at91_uart_config *config)
2095 +{
2096 +       int i;
2097 +
2098 +       /* Fill in list of supported UARTs */
2099 +       for (i = 0; i < config->nr_tty; i++) {
2100 +               switch (config->tty_map[i]) {
2101 +                       case 0:
2102 +                               configure_usart0_pins();
2103 +                               at91_uarts[i] = &at91sam9rl_uart0_device;
2104 +                               at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
2105 +                               break;
2106 +                       case 1:
2107 +                               configure_usart1_pins();
2108 +                               at91_uarts[i] = &at91sam9rl_uart1_device;
2109 +                               at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
2110 +                               break;
2111 +                       case 2:
2112 +                               configure_usart2_pins();
2113 +                               at91_uarts[i] = &at91sam9rl_uart2_device;
2114 +                               at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
2115 +                               break;
2116 +                       case 3:
2117 +                               configure_usart3_pins();
2118 +                               at91_uarts[i] = &at91sam9rl_uart3_device;
2119 +                               at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
2120 +                               break;
2121 +                       case 4:
2122 +                               configure_dbgu_pins();
2123 +                               at91_uarts[i] = &at91sam9rl_dbgu_device;
2124 +                               at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
2125 +                               break;
2126 +                       default:
2127 +                               continue;
2128 +               }
2129 +               at91_uarts[i]->id = i;          /* update ID number to mapped ID */
2130 +       }
2131 +
2132 +       /* Set serial console device */
2133 +       if (config->console_tty < ATMEL_MAX_UART)
2134 +               atmel_default_console_device = at91_uarts[config->console_tty];
2135 +       if (!atmel_default_console_device)
2136 +               printk(KERN_INFO "AT91: No default serial console defined.\n");
2137 +}
2138 +
2139 +void __init at91_add_device_serial(void)
2140 +{
2141 +       int i;
2142 +
2143 +       for (i = 0; i < ATMEL_MAX_UART; i++) {
2144 +               if (at91_uarts[i])
2145 +                       platform_device_register(at91_uarts[i]);
2146 +       }
2147 +}
2148 +#else
2149 +void __init at91_init_serial(struct at91_uart_config *config) {}
2150 +void __init at91_add_device_serial(void) {}
2151 +#endif
2152 +
2153 +
2154 +/* -------------------------------------------------------------------- */
2155 +
2156 +/*
2157 + * These devices are always present and don't need any board-specific
2158 + * setup.
2159 + */
2160 +static int __init at91_add_standard_devices(void)
2161 +{
2162 +       return 0;
2163 +}
2164 +
2165 +arch_initcall(at91_add_standard_devices);
2166 Index: linux-2.6.21.7/arch/arm/mach-at91/board-cam60.c
2167 ===================================================================
2168 --- /dev/null
2169 +++ linux-2.6.21.7/arch/arm/mach-at91/board-cam60.c
2170 @@ -0,0 +1,148 @@
2171 +/*
2172 + * KwikByte CAM60
2173 + *
2174 + * based on board-sam9260ek.c
2175 + *   Copyright (C) 2005 SAN People
2176 + *   Copyright (C) 2006 Atmel
2177 + *
2178 + * This program is free software; you can redistribute it and/or modify
2179 + * it under the terms of the GNU General Public License as published by
2180 + * the Free Software Foundation; either version 2 of the License, or
2181 + * (at your option) any later version.
2182 + *
2183 + * This program is distributed in the hope that it will be useful,
2184 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2185 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2186 + * GNU General Public License for more details.
2187 + *
2188 + * You should have received a copy of the GNU General Public License
2189 + * along with this program; if not, write to the Free Software
2190 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2191 + */
2192 +
2193 +#include <linux/types.h>
2194 +#include <linux/init.h>
2195 +#include <linux/mm.h>
2196 +#include <linux/module.h>
2197 +#include <linux/platform_device.h>
2198 +#include <linux/spi/spi.h>
2199 +#include <linux/spi/flash.h>
2200 +
2201 +#include <asm/hardware.h>
2202 +#include <asm/setup.h>
2203 +#include <asm/mach-types.h>
2204 +#include <asm/irq.h>
2205 +
2206 +#include <asm/mach/arch.h>
2207 +#include <asm/mach/map.h>
2208 +#include <asm/mach/irq.h>
2209 +
2210 +#include <asm/arch/board.h>
2211 +#include <asm/arch/gpio.h>
2212 +#include <asm/arch/at91sam926x_mc.h>
2213 +
2214 +#include "generic.h"
2215 +
2216 +
2217 +/*
2218 + * Serial port configuration.
2219 + *    0 .. 5 = USART0 .. USART5
2220 + *    6      = DBGU
2221 + */
2222 +static struct at91_uart_config __initdata cam60_uart_config = {
2223 +       .console_tty    = 0,                            /* ttyS0 */
2224 +       .nr_tty         = 1,
2225 +       .tty_map        = { 6, -1, -1, -1, -1, -1, -1 } /* ttyS0, ..., ttyS6 */
2226 +};
2227 +
2228 +static void __init cam60_map_io(void)
2229 +{
2230 +       /* Initialize processor: 10 MHz crystal */
2231 +       at91sam9260_initialize(10000000);
2232 +
2233 +       /* Setup the serial ports and console */
2234 +       at91_init_serial(&cam60_uart_config);
2235 +}
2236 +
2237 +static void __init cam60_init_irq(void)
2238 +{
2239 +       at91sam9260_init_interrupts(NULL);
2240 +}
2241 +
2242 +
2243 +/*
2244 + * SPI devices.
2245 + */
2246 +#if defined(CONFIG_MTD_DATAFLASH)
2247 +static struct mtd_partition __initdata cam60_spi_partitions[] = {
2248 +       {
2249 +               .name   = "BOOT1",
2250 +               .offset = 0,
2251 +               .size   = 4 * 1056,
2252 +       },
2253 +       {
2254 +               .name   = "BOOT2",
2255 +               .offset = MTDPART_OFS_NXTBLK,
2256 +               .size   = 256 * 1056,
2257 +       },
2258 +       {
2259 +               .name   = "kernel",
2260 +               .offset = MTDPART_OFS_NXTBLK,
2261 +               .size   = 2222 * 1056,
2262 +       },
2263 +       {
2264 +               .name   = "file system",
2265 +               .offset = MTDPART_OFS_NXTBLK,
2266 +               .size   = MTDPART_SIZ_FULL,
2267 +       },
2268 +};
2269 +
2270 +static struct flash_platform_data __initdata cam60_spi_flash_platform_data = {
2271 +       .name           = "spi_flash",
2272 +       .parts          = cam60_spi_partitions,
2273 +       .nr_parts       = ARRAY_SIZE(cam60_spi_partitions)
2274 +};
2275 +#endif
2276 +
2277 +static struct spi_board_info cam60_spi_devices[] = {
2278 +#if defined(CONFIG_MTD_DATAFLASH)
2279 +       {       /* DataFlash chip */
2280 +               .modalias       = "mtd_dataflash",
2281 +               .chip_select    = 0,
2282 +               .max_speed_hz   = 15 * 1000 * 1000,
2283 +               .bus_num        = 0,
2284 +               .platform_data  = &cam60_spi_flash_platform_data
2285 +       },
2286 +#endif
2287 +};
2288 +
2289 +
2290 +/*
2291 + * MACB Ethernet device
2292 + */
2293 +static struct __initdata at91_eth_data cam60_macb_data = {
2294 +       .phy_irq_pin    = AT91_PIN_PB5,
2295 +       .is_rmii        = 0,
2296 +};
2297 +
2298 +
2299 +static void __init cam60_board_init(void)
2300 +{
2301 +       /* Serial */
2302 +       at91_add_device_serial();
2303 +       /* SPI */
2304 +       at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
2305 +       /* Ethernet */
2306 +       at91_add_device_eth(&cam60_macb_data);
2307 +}
2308 +
2309 +MACHINE_START(CAM60, "KwikByte CAM60")
2310 +       /* Maintainer: KwikByte */
2311 +       .phys_io        = AT91_BASE_SYS,
2312 +       .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
2313 +       .boot_params    = AT91_SDRAM_BASE + 0x100,
2314 +       .timer          = &at91sam926x_timer,
2315 +       .map_io         = cam60_map_io,
2316 +       .init_irq       = cam60_init_irq,
2317 +       .init_machine   = cam60_board_init,
2318 +MACHINE_END
2319 Index: linux-2.6.21.7/arch/arm/mach-at91/board-chub.c
2320 ===================================================================
2321 --- /dev/null
2322 +++ linux-2.6.21.7/arch/arm/mach-at91/board-chub.c
2323 @@ -0,0 +1,132 @@
2324 +/*
2325 + * linux/arch/arm/mach-at91/board-chub.c
2326 + *
2327 + *  Copyright (C) 2005 SAN People, adapted for Promwad Chub board
2328 + *  by Kuten Ivan
2329 + *
2330 + * This program is free software; you can redistribute it and/or modify
2331 + * it under the terms of the GNU General Public License as published by
2332 + * the Free Software Foundation; either version 2 of the License, or
2333 + * (at your option) any later version.
2334 + *
2335 + * This program is distributed in the hope that it will be useful,
2336 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2337 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2338 + * GNU General Public License for more details.
2339 + *
2340 + * You should have received a copy of the GNU General Public License
2341 + * along with this program; if not, write to the Free Software
2342 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2343 + */
2344 +
2345 +#include <linux/types.h>
2346 +#include <linux/init.h>
2347 +#include <linux/mm.h>
2348 +#include <linux/module.h>
2349 +#include <linux/platform_device.h>
2350 +
2351 +#include <asm/hardware.h>
2352 +#include <asm/setup.h>
2353 +#include <asm/mach-types.h>
2354 +#include <asm/irq.h>
2355 +
2356 +#include <asm/mach/arch.h>
2357 +#include <asm/mach/map.h>
2358 +#include <asm/mach/irq.h>
2359 +
2360 +#include <asm/arch/board.h>
2361 +#include <asm/arch/gpio.h>
2362 +
2363 +#include "generic.h"
2364 +
2365 +/*
2366 + * Serial port configuration.
2367 + *    0 .. 3 = USART0 .. USART3
2368 + *    4      = DBGU
2369 + */
2370 +static struct at91_uart_config __initdata chub_uart_config = {
2371 +       .console_tty    = 0,                            /* ttyS0 */
2372 +       .nr_tty         = 5,
2373 +       .tty_map        = { 4, 0, 1, 2, 3 }             /* ttyS0, ..., ttyS4 */
2374 +};
2375 +
2376 +static void __init chub_init_irq(void)
2377 +{
2378 +       at91rm9200_init_interrupts(NULL);
2379 +}
2380 +
2381 +static void __init chub_map_io(void)
2382 +{
2383 +       /* Initialize clocks: 18.432 MHz crystal */
2384 +       at91rm9200_initialize(18432000, AT91RM9200_PQFP);
2385 +
2386 +       /* Setup the serial ports and console */
2387 +       at91_init_serial(&chub_uart_config);
2388 +}
2389 +
2390 +static struct at91_eth_data __initdata chub_eth_data = {
2391 +       .phy_irq_pin    = AT91_PIN_PB29,
2392 +       .is_rmii        = 0,
2393 +};
2394 +
2395 +static struct mtd_partition __initdata chub_nand_partition[] = {
2396 +       {
2397 +               .name   = "NAND Partition 1",
2398 +               .offset = 0,
2399 +               .size   = MTDPART_SIZ_FULL,
2400 +       },
2401 +};
2402 +
2403 +static struct mtd_partition *nand_partitions(int size, int *num_partitions)
2404 +{
2405 +       *num_partitions = ARRAY_SIZE(chub_nand_partition);
2406 +       return chub_nand_partition;
2407 +}
2408 +
2409 +static struct at91_nand_data __initdata chub_nand_data = {
2410 +       .ale            = 22,
2411 +       .cle            = 21,
2412 +       .enable_pin     = AT91_PIN_PA27,
2413 +       .partition_info = nand_partitions,
2414 +};
2415 +
2416 +static struct spi_board_info chub_spi_devices[] = {
2417 +       {       /* DataFlash chip */
2418 +               .modalias       = "mtd_dataflash",
2419 +               .chip_select    = 0,
2420 +               .max_speed_hz   = 15 * 1000 * 1000,
2421 +       },
2422 +};
2423 +
2424 +static void __init chub_board_init(void)
2425 +{
2426 +       /* Serial */
2427 +       at91_add_device_serial();
2428 +       /* I2C */
2429 +       at91_add_device_i2c();
2430 +       /* Ethernet */
2431 +       at91_add_device_eth(&chub_eth_data);
2432 +       /* SPI */
2433 +       at91_add_device_spi(chub_spi_devices, ARRAY_SIZE(chub_spi_devices));
2434 +       /* NAND Flash */
2435 +       at91_add_device_nand(&chub_nand_data);
2436 +       /* Disable write protect for NAND */
2437 +       at91_set_gpio_output(AT91_PIN_PB7, 1);
2438 +       /* Power enable for 3x RS-232 and 1x RS-485 */
2439 +       at91_set_gpio_output(AT91_PIN_PB9, 1);
2440 +       /* Disable write protect for FRAM */
2441 +       at91_set_gpio_output(AT91_PIN_PA21, 1);
2442 +       /* Disable write protect for Dataflash */
2443 +       at91_set_gpio_output(AT91_PIN_PA19, 1);
2444 +}
2445 +
2446 +MACHINE_START(CHUB, "Promwad Chub")
2447 +       /* Maintainer: Ivan Kuten AT Promwad DOT com */
2448 +       .phys_io        = AT91_BASE_SYS,
2449 +       .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
2450 +       .boot_params    = AT91_SDRAM_BASE + 0x100,
2451 +       .timer          = &at91rm9200_timer,
2452 +       .map_io         = chub_map_io,
2453 +       .init_irq       = chub_init_irq,
2454 +       .init_machine   = chub_board_init,
2455 +MACHINE_END
2456 Index: linux-2.6.21.7/arch/arm/mach-at91/board-csb337.c
2457 ===================================================================
2458 --- linux-2.6.21.7.orig/arch/arm/mach-at91/board-csb337.c
2459 +++ linux-2.6.21.7/arch/arm/mach-at91/board-csb337.c
2460 @@ -24,6 +24,7 @@
2461  #include <linux/module.h>
2462  #include <linux/platform_device.h>
2463  #include <linux/spi/spi.h>
2464 +#include <linux/interrupt.h>
2465  #include <linux/mtd/physmap.h>
2466
2467  #include <asm/hardware.h>
2468 @@ -59,6 +60,7 @@ static void __init csb337_map_io(void)
2469
2470         /* Setup the LEDs */
2471         at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
2472 +       at91_set_gpio_output(AT91_PIN_PB2, 1);          /* third (unused) LED */
2473
2474         /* Setup the serial ports and console */
2475         at91_init_serial(&csb337_uart_config);
2476 @@ -149,6 +151,55 @@ static struct platform_device csb_flash
2477         .num_resources  = ARRAY_SIZE(csb_flash_resources),
2478  };
2479
2480 +static struct at91_gpio_led csb337_leds[] = {
2481 +       {
2482 +               .name           = "led0",
2483 +               .gpio           = AT91_PIN_PB0,
2484 +               .trigger        = "heartbeat",
2485 +       },
2486 +       {
2487 +               .name           = "led1",
2488 +               .gpio           = AT91_PIN_PB1,
2489 +               .trigger        = "timer",
2490 +       },
2491 +       {
2492 +               .name           = "led2",
2493 +               .gpio           = AT91_PIN_PB2,
2494 +       }
2495 +};
2496 +
2497 +#if defined(CONFIG_CSB300_WAKE_SW0) || defined(CONFIG_CSB300_WAKE_SW1)
2498 +static irqreturn_t switch_irq_handler(int irq, void *context)
2499 +{
2500 +       return IRQ_HANDLED;
2501 +}
2502 +
2503 +static inline void __init switch_irq_setup(int irq, char *name, unsigned long mode)
2504 +{
2505 +       int res;
2506 +
2507 +       res = request_irq(irq, switch_irq_handler, IRQF_SAMPLE_RANDOM | mode, name, NULL);
2508 +       if (res == 0)
2509 +               enable_irq_wake(irq);
2510 +}
2511 +
2512 +static void __init csb300_switches(void)
2513 +{
2514 +#ifdef CONFIG_CSB300_WAKE_SW0
2515 +       at91_set_A_periph(AT91_PIN_PB29, 1);            /* IRQ0 */
2516 +       switch_irq_setup(AT91RM9200_ID_IRQ0, "csb300_sw0", IRQF_TRIGGER_FALLING);
2517 +#endif
2518 +#ifdef CONFIG_CSB300_WAKE_SW1
2519 +       at91_set_gpio_input(AT91_PIN_PB28, 1);
2520 +       at91_set_deglitch(AT91_PIN_PB28, 1);
2521 +       switch_irq_setup(AT91_PIN_PB28, "csb300_sw1", IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING);
2522 +#endif
2523 +       /* there's also SW2 at PA21, GPIO or TIOA2 */
2524 +}
2525 +#else
2526 +static void __init csb300_switches(void) {}
2527 +#endif
2528 +
2529  static void __init csb337_board_init(void)
2530  {
2531         /* Serial */
2532 @@ -168,8 +219,12 @@ static void __init csb337_board_init(voi
2533         at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
2534         /* MMC */
2535         at91_add_device_mmc(0, &csb337_mmc_data);
2536 +       /* LEDS */
2537 +       at91_gpio_leds(csb337_leds, ARRAY_SIZE(csb337_leds));
2538         /* NOR flash */
2539         platform_device_register(&csb_flash);
2540 +       /* Switches on CSB300 */
2541 +       csb300_switches();
2542  }
2543
2544  MACHINE_START(CSB337, "Cogent CSB337")
2545 Index: linux-2.6.21.7/arch/arm/mach-at91/board-dk.c
2546 ===================================================================
2547 --- linux-2.6.21.7.orig/arch/arm/mach-at91/board-dk.c
2548 +++ linux-2.6.21.7/arch/arm/mach-at91/board-dk.c
2549 @@ -73,6 +73,185 @@ static void __init dk_init_irq(void)
2550         at91rm9200_init_interrupts(NULL);
2551  }
2552
2553 +#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
2554 +#include <video/s1d13xxxfb.h>
2555 +#include <asm/arch/ics1523.h>
2556 +
2557 +/* EPSON S1D13806 FB */
2558 +#define AT91_FB_REG_BASE       0x30000000L
2559 +#define AT91_FB_REG_SIZE       0x200
2560 +#define AT91_FB_VMEM_BASE      0x30200000L
2561 +#define AT91_FB_VMEM_SIZE      0x140000L
2562 +
2563 +static void __init dk_init_video(void)
2564 +{
2565 +       /* NWAIT Signal */
2566 +       at91_set_A_periph(AT91_PIN_PC6, 0);
2567 +
2568 +       /* Initialization of the Static Memory Controller for Chip Select 2 */
2569 +       at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16                 /* 16 bit */
2570 +                               | AT91_SMC_WSEN | AT91_SMC_NWS_(4)      /* wait states */
2571 +                               | AT91_SMC_TDF_(1)                      /* float time */
2572 +       );
2573 +
2574 +       at91_ics1523_init();
2575 +}
2576 +
2577 +/* CRT:    (active)   640x480 60Hz (PCLK=CLKI=25.175MHz)
2578 +   Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */
2579 +static const struct s1d13xxxfb_regval dk_s1dfb_initregs[] = {
2580 +       {S1DREG_MISC,                   0x00},  /* Enable Memory/Register select bit */
2581 +       {S1DREG_COM_DISP_MODE,          0x00},  /* disable display output */
2582 +       {S1DREG_GPIO_CNF0,              0x00},
2583 +       {S1DREG_GPIO_CNF1,              0x00},
2584 +       {S1DREG_GPIO_CTL0,              0x08},
2585 +       {S1DREG_GPIO_CTL1,              0x00},
2586 +       {S1DREG_CLK_CNF,                0x01},  /* no divide, MCLK source is CLKI3 0x02*/
2587 +       {S1DREG_LCD_CLK_CNF,            0x00},
2588 +       {S1DREG_CRT_CLK_CNF,            0x00},
2589 +       {S1DREG_MPLUG_CLK_CNF,          0x00},
2590 +       {S1DREG_CPU2MEM_WST_SEL,        0x01},  /* 2*period(MCLK) - 4ns > period(BCLK) */
2591 +       {S1DREG_SDRAM_REF_RATE,         0x03},  /* 32768 <= MCLK <= 50000 (MHz) */
2592 +       {S1DREG_SDRAM_TC0,              0x00},  /* MCLK source freq (MHz): */
2593 +       {S1DREG_SDRAM_TC1,              0x01},  /* 42 <= MCLK <= 50 */
2594 +       {S1DREG_MEM_CNF,                0x80},  /* SDRAM Initialization - needed before mem access */
2595 +       {S1DREG_PANEL_TYPE,             0x25},  /* std TFT 16bit, 8bit SCP format 2, single passive LCD */
2596 +       {S1DREG_MOD_RATE,               0x00},  /* toggle every FPFRAME */
2597 +       {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* 680 pix */
2598 +       {S1DREG_LCD_NDISP_HPER,         0x12},  /* 152 pix */
2599 +       {S1DREG_TFT_FPLINE_START,       0x01},  /* 13 pix */
2600 +       {S1DREG_TFT_FPLINE_PWIDTH,      0x0B},  /* 96 pix */
2601 +       {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},
2602 +       {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* 480 lines */
2603 +       {S1DREG_LCD_NDISP_VPER,         0x2C},  /* 44 lines */
2604 +       {S1DREG_TFT_FPFRAME_START,      0x0A},  /* 10 lines */
2605 +       {S1DREG_TFT_FPFRAME_PWIDTH,     0x01},  /* 2 lines */
2606 +       {S1DREG_LCD_DISP_MODE,          0x05},  /* 16 bpp */
2607 +       {S1DREG_LCD_MISC,               0x00},  /* dithering enabled, dual panel buffer enabled */
2608 +       {S1DREG_LCD_DISP_START0,        0x00},
2609 +       {S1DREG_LCD_DISP_START1,        0xC8},
2610 +       {S1DREG_LCD_DISP_START2,        0x00},
2611 +       {S1DREG_LCD_MEM_OFF0,           0x80},
2612 +       {S1DREG_LCD_MEM_OFF1,           0x02},
2613 +       {S1DREG_LCD_PIX_PAN,            0x00},
2614 +       {S1DREG_LCD_DISP_FIFO_HTC,      0x3B},
2615 +       {S1DREG_LCD_DISP_FIFO_LTC,      0x3C},
2616 +       {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* 680 pix */
2617 +       {S1DREG_CRT_NDISP_HPER,         0x13},  /* 160 pix */
2618 +       {S1DREG_CRT_HRTC_START,         0x01},  /* 13 pix */
2619 +       {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* 96 pix */
2620 +       {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},
2621 +       {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* 480 lines */
2622 +       {S1DREG_CRT_NDISP_VPER,         0x2B},  /* 44 lines */
2623 +       {S1DREG_CRT_VRTC_START,         0x09},  /* 10 lines */
2624 +       {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* 2 lines */
2625 +       {S1DREG_TV_OUT_CTL,             0x10},
2626 +       {S1DREG_CRT_DISP_MODE,          0x05},  /* 16 bpp */
2627 +       {S1DREG_CRT_DISP_START0,        0x00},
2628 +       {S1DREG_CRT_DISP_START1,        0x00},
2629 +       {S1DREG_CRT_DISP_START2,        0x00},
2630 +       {S1DREG_CRT_MEM_OFF0,           0x80},
2631 +       {S1DREG_CRT_MEM_OFF1,           0x02},
2632 +       {S1DREG_CRT_PIX_PAN,            0x00},
2633 +       {S1DREG_CRT_DISP_FIFO_HTC,      0x3B},
2634 +       {S1DREG_CRT_DISP_FIFO_LTC,      0x3C},
2635 +       {S1DREG_LCD_CUR_CTL,            0x00},  /* inactive */
2636 +       {S1DREG_LCD_CUR_START,          0x01},
2637 +       {S1DREG_LCD_CUR_XPOS0,          0x00},
2638 +       {S1DREG_LCD_CUR_XPOS1,          0x00},
2639 +       {S1DREG_LCD_CUR_YPOS0,          0x00},
2640 +       {S1DREG_LCD_CUR_YPOS1,          0x00},
2641 +       {S1DREG_LCD_CUR_BCTL0,          0x00},
2642 +       {S1DREG_LCD_CUR_GCTL0,          0x00},
2643 +       {S1DREG_LCD_CUR_RCTL0,          0x00},
2644 +       {S1DREG_LCD_CUR_BCTL1,          0x1F},
2645 +       {S1DREG_LCD_CUR_GCTL1,          0x3F},
2646 +       {S1DREG_LCD_CUR_RCTL1,          0x1F},
2647 +       {S1DREG_LCD_CUR_FIFO_HTC,       0x00},
2648 +       {S1DREG_CRT_CUR_CTL,            0x00},  /* inactive */
2649 +       {S1DREG_CRT_CUR_START,          0x01},
2650 +       {S1DREG_CRT_CUR_XPOS0,          0x00},
2651 +       {S1DREG_CRT_CUR_XPOS1,          0x00},
2652 +       {S1DREG_CRT_CUR_YPOS0,          0x00},
2653 +       {S1DREG_CRT_CUR_YPOS1,          0x00},
2654 +       {S1DREG_CRT_CUR_BCTL0,          0x00},
2655 +       {S1DREG_CRT_CUR_GCTL0,          0x00},
2656 +       {S1DREG_CRT_CUR_RCTL0,          0x00},
2657 +       {S1DREG_CRT_CUR_BCTL1,          0x1F},
2658 +       {S1DREG_CRT_CUR_GCTL1,          0x3F},
2659 +       {S1DREG_CRT_CUR_RCTL1,          0x1F},
2660 +       {S1DREG_CRT_CUR_FIFO_HTC,       0x00},
2661 +       {S1DREG_BBLT_CTL0,              0x00},
2662 +       {S1DREG_BBLT_CTL0,              0x00},
2663 +       {S1DREG_BBLT_CC_EXP,            0x00},
2664 +       {S1DREG_BBLT_OP,                0x00},
2665 +       {S1DREG_BBLT_SRC_START0,        0x00},
2666 +       {S1DREG_BBLT_SRC_START1,        0x00},
2667 +       {S1DREG_BBLT_SRC_START2,        0x00},
2668 +       {S1DREG_BBLT_DST_START0,        0x00},
2669 +       {S1DREG_BBLT_DST_START1,        0x00},
2670 +       {S1DREG_BBLT_DST_START2,        0x00},
2671 +       {S1DREG_BBLT_MEM_OFF0,          0x00},
2672 +       {S1DREG_BBLT_MEM_OFF1,          0x00},
2673 +       {S1DREG_BBLT_WIDTH0,            0x00},
2674 +       {S1DREG_BBLT_WIDTH1,            0x00},
2675 +       {S1DREG_BBLT_HEIGHT0,           0x00},
2676 +       {S1DREG_BBLT_HEIGHT1,           0x00},
2677 +       {S1DREG_BBLT_BGC0,              0x00},
2678 +       {S1DREG_BBLT_BGC1,              0x00},
2679 +       {S1DREG_BBLT_FGC0,              0x00},
2680 +       {S1DREG_BBLT_FGC1,              0x00},
2681 +       {S1DREG_LKUP_MODE,              0x00},  /* LCD LUT r | LCD and CRT/TV LUT w */
2682 +       {S1DREG_LKUP_ADDR,              0x00},
2683 +       {S1DREG_PS_CNF,                 0x00},  /* Power Save disable */
2684 +       {S1DREG_PS_STATUS,              0x02},  /* LCD Panel down, mem up */
2685 +       {S1DREG_CPU2MEM_WDOGT,          0x00},
2686 +       {S1DREG_COM_DISP_MODE,          0x02},  /* enable CRT display output */
2687 +};
2688 +
2689 +static struct s1d13xxxfb_pdata dk_s1dfb_pdata = {
2690 +       .initregs               = dk_s1dfb_initregs,
2691 +       .initregssize           = ARRAY_SIZE(dk_s1dfb_initregs),
2692 +       .platform_init_video    = dk_init_video,
2693 +};
2694 +
2695 +static u64 s1dfb_dmamask = 0xffffffffUL;
2696 +
2697 +static struct resource dk_s1dfb_resource[] = {
2698 +       [0] = { /* video mem */
2699 +               .name   = "s1d13806 memory",
2700 +               .start  = AT91_FB_VMEM_BASE,
2701 +               .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
2702 +               .flags  = IORESOURCE_MEM,
2703 +       },
2704 +       [1] = { /* video registers */
2705 +               .name   = "s1d13806 registers",
2706 +               .start  = AT91_FB_REG_BASE,
2707 +               .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
2708 +               .flags  = IORESOURCE_MEM,
2709 +       },
2710 +};
2711 +
2712 +static struct platform_device dk_s1dfb_device = {
2713 +       .name           = "s1d13806fb",
2714 +       .id             = -1,
2715 +       .dev            = {
2716 +                       .dma_mask               = &s1dfb_dmamask,
2717 +                       .coherent_dma_mask      = 0xffffffff,
2718 +                       .platform_data          = &dk_s1dfb_pdata,
2719 +       },
2720 +       .resource       = dk_s1dfb_resource,
2721 +       .num_resources  = ARRAY_SIZE(dk_s1dfb_resource),
2722 +};
2723 +
2724 +static void __init dk_add_device_video(void)
2725 +{
2726 +       platform_device_register(&dk_s1dfb_device);
2727 +}
2728 +#else
2729 +static void __init dk_add_device_video(void) {}
2730 +#endif
2731 +
2732  static struct at91_eth_data __initdata dk_eth_data = {
2733         .phy_irq_pin    = AT91_PIN_PC4,
2734         .is_rmii        = 1,
2735 @@ -151,7 +330,7 @@ static struct at91_nand_data __initdata
2736  #define DK_FLASH_SIZE  0x200000
2737
2738  static struct physmap_flash_data dk_flash_data = {
2739 -       .width  = 2,
2740 +       .width          = 2,
2741  };
2742
2743  static struct resource dk_flash_resource = {
2744 @@ -170,6 +349,13 @@ static struct platform_device dk_flash =
2745         .num_resources  = 1,
2746  };
2747
2748 +static struct at91_gpio_led dk_leds[] = {
2749 +       {
2750 +               .name           = "led0",
2751 +               .gpio           = AT91_PIN_PB2,
2752 +               .trigger        = "timer",
2753 +       }
2754 +};
2755
2756  static void __init dk_board_init(void)
2757  {
2758 @@ -200,8 +386,10 @@ static void __init dk_board_init(void)
2759         at91_add_device_nand(&dk_nand_data);
2760         /* NOR Flash */
2761         platform_device_register(&dk_flash);
2762 +       /* LEDs */
2763 +       at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds));
2764         /* VGA */
2765 -//     dk_add_device_video();
2766 +       dk_add_device_video();
2767  }
2768
2769  MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
2770 Index: linux-2.6.21.7/arch/arm/mach-at91/board-ek.c
2771 ===================================================================
2772 --- linux-2.6.21.7.orig/arch/arm/mach-at91/board-ek.c
2773 +++ linux-2.6.21.7/arch/arm/mach-at91/board-ek.c
2774 @@ -73,6 +73,187 @@ static void __init ek_init_irq(void)
2775         at91rm9200_init_interrupts(NULL);
2776  }
2777
2778 +#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
2779 +#include <video/s1d13xxxfb.h>
2780 +#include <asm/arch/ics1523.h>
2781 +
2782 +/* EPSON S1D13806 FB */
2783 +#define AT91_FB_REG_BASE       0x40000000L
2784 +#define        AT91_FB_REG_SIZE        0x200
2785 +#define AT91_FB_VMEM_BASE      0x40200000L
2786 +#define AT91_FB_VMEM_SIZE      0x140000L
2787 +
2788 +static void __init ek_init_video(void)
2789 +{
2790 +       /* NWAIT Signal */
2791 +       at91_set_A_periph(AT91_PIN_PC6, 0);
2792 +
2793 +       /* Initialization of the Static Memory Controller for Chip Select 3 */
2794 +       at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_DBW_16                 /* 16 bit */
2795 +                               | AT91_SMC_WSEN | AT91_SMC_NWS_(5)      /* wait states */
2796 +                               | AT91_SMC_TDF_(1)                      /* float time */
2797 +       );
2798 +
2799 +       at91_ics1523_init();
2800 +}
2801 +
2802 +/* CRT:    (active)   640x480 60Hz (PCLK=CLKI=25.175MHz)
2803 +   Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz) */
2804 +static const struct s1d13xxxfb_regval ek_s1dfb_initregs[] = {
2805 +       {S1DREG_MISC,                   0x00},  /* Enable Memory/Register select bit */
2806 +       {S1DREG_COM_DISP_MODE,          0x00},  /* disable display output */
2807 +       {S1DREG_GPIO_CNF0,              0xFF},  // 0x00
2808 +       {S1DREG_GPIO_CNF1,              0x1F},  // 0x08
2809 +       {S1DREG_GPIO_CTL0,              0x00},
2810 +       {S1DREG_GPIO_CTL1,              0x00},
2811 +       {S1DREG_CLK_CNF,                0x01},  /* no divide, MCLK source is CLKI3 0x02*/
2812 +       {S1DREG_LCD_CLK_CNF,            0x00},
2813 +       {S1DREG_CRT_CLK_CNF,            0x00},
2814 +       {S1DREG_MPLUG_CLK_CNF,          0x00},
2815 +       {S1DREG_CPU2MEM_WST_SEL,        0x01},  /* 2*period(MCLK) - 4ns > period(BCLK) */
2816 +       {S1DREG_SDRAM_REF_RATE,         0x03},  /* 32768 <= MCLK <= 50000 (MHz) */
2817 +       {S1DREG_SDRAM_TC0,              0x00},  /* MCLK source freq (MHz): */
2818 +       {S1DREG_SDRAM_TC1,              0x01},  /* 42 <= MCLK <= 50 */
2819 +       {S1DREG_MEM_CNF,                0x80},  /* SDRAM Initialization - needed before mem access */
2820 +       {S1DREG_PANEL_TYPE,             0x25},  /* std TFT 16bit, 8bit SCP format 2, single passive LCD */
2821 +       {S1DREG_MOD_RATE,               0x00},  /* toggle every FPFRAME */
2822 +       {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* 680 pix */
2823 +       {S1DREG_LCD_NDISP_HPER,         0x12},  /* 152 pix */
2824 +       {S1DREG_TFT_FPLINE_START,       0x01},  /* 13 pix */
2825 +       {S1DREG_TFT_FPLINE_PWIDTH,      0x0B},  /* 96 pix */
2826 +       {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},
2827 +       {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* 480 lines */
2828 +       {S1DREG_LCD_NDISP_VPER,         0x2C},  /* 44 lines */
2829 +       {S1DREG_TFT_FPFRAME_START,      0x0A},  /* 10 lines */
2830 +       {S1DREG_TFT_FPFRAME_PWIDTH,     0x01},  /* 2 lines */
2831 +       {S1DREG_LCD_DISP_MODE,          0x05},  /* 16 bpp */
2832 +       {S1DREG_LCD_MISC,               0x00},  /* dithering enabled, dual panel buffer enabled */
2833 +       {S1DREG_LCD_DISP_START0,        0x00},
2834 +       {S1DREG_LCD_DISP_START1,        0xC8},
2835 +       {S1DREG_LCD_DISP_START2,        0x00},
2836 +       {S1DREG_LCD_MEM_OFF0,           0x80},
2837 +       {S1DREG_LCD_MEM_OFF1,           0x02},
2838 +       {S1DREG_LCD_PIX_PAN,            0x00},
2839 +       {S1DREG_LCD_DISP_FIFO_HTC,      0x3B},
2840 +       {S1DREG_LCD_DISP_FIFO_LTC,      0x3C},
2841 +       {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* 680 pix */
2842 +       {S1DREG_CRT_NDISP_HPER,         0x13},  /* 160 pix */
2843 +       {S1DREG_CRT_HRTC_START,         0x01},  /* 13 pix */
2844 +       {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* 96 pix */
2845 +       {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},
2846 +       {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* 480 lines */
2847 +       {S1DREG_CRT_NDISP_VPER,         0x2B},  /* 44 lines */
2848 +       {S1DREG_CRT_VRTC_START,         0x09},  /* 10 lines */
2849 +       {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* 2 lines */
2850 +       {S1DREG_TV_OUT_CTL,             0x10},
2851 +       {0x005E,                        0x9F},
2852 +       {0x005F,                        0x00},
2853 +       {S1DREG_CRT_DISP_MODE,          0x05},  /* 16 bpp */
2854 +       {S1DREG_CRT_DISP_START0,        0x00},
2855 +       {S1DREG_CRT_DISP_START1,        0x00},
2856 +       {S1DREG_CRT_DISP_START2,        0x00},
2857 +       {S1DREG_CRT_MEM_OFF0,           0x80},
2858 +       {S1DREG_CRT_MEM_OFF1,           0x02},
2859 +       {S1DREG_CRT_PIX_PAN,            0x00},
2860 +       {S1DREG_CRT_DISP_FIFO_HTC,      0x3B},
2861 +       {S1DREG_CRT_DISP_FIFO_LTC,      0x3C},
2862 +       {S1DREG_LCD_CUR_CTL,            0x00},  /* inactive */
2863 +       {S1DREG_LCD_CUR_START,          0x01},
2864 +       {S1DREG_LCD_CUR_XPOS0,          0x00},
2865 +       {S1DREG_LCD_CUR_XPOS1,          0x00},
2866 +       {S1DREG_LCD_CUR_YPOS0,          0x00},
2867 +       {S1DREG_LCD_CUR_YPOS1,          0x00},
2868 +       {S1DREG_LCD_CUR_BCTL0,          0x00},
2869 +       {S1DREG_LCD_CUR_GCTL0,          0x00},
2870 +       {S1DREG_LCD_CUR_RCTL0,          0x00},
2871 +       {S1DREG_LCD_CUR_BCTL1,          0x1F},
2872 +       {S1DREG_LCD_CUR_GCTL1,          0x3F},
2873 +       {S1DREG_LCD_CUR_RCTL1,          0x1F},
2874 +       {S1DREG_LCD_CUR_FIFO_HTC,       0x00},
2875 +       {S1DREG_CRT_CUR_CTL,            0x00},  /* inactive */
2876 +       {S1DREG_CRT_CUR_START,          0x01},
2877 +       {S1DREG_CRT_CUR_XPOS0,          0x00},
2878 +       {S1DREG_CRT_CUR_XPOS1,          0x00},
2879 +       {S1DREG_CRT_CUR_YPOS0,          0x00},
2880 +       {S1DREG_CRT_CUR_YPOS1,          0x00},
2881 +       {S1DREG_CRT_CUR_BCTL0,          0x00},
2882 +       {S1DREG_CRT_CUR_GCTL0,          0x00},
2883 +       {S1DREG_CRT_CUR_RCTL0,          0x00},
2884 +       {S1DREG_CRT_CUR_BCTL1,          0x1F},
2885 +       {S1DREG_CRT_CUR_GCTL1,          0x3F},
2886 +       {S1DREG_CRT_CUR_RCTL1,          0x1F},
2887 +       {S1DREG_CRT_CUR_FIFO_HTC,       0x00},
2888 +       {S1DREG_BBLT_CTL0,              0x00},
2889 +       {S1DREG_BBLT_CTL0,              0x00},
2890 +       {S1DREG_BBLT_CC_EXP,            0x00},
2891 +       {S1DREG_BBLT_OP,                0x00},
2892 +       {S1DREG_BBLT_SRC_START0,        0x00},
2893 +       {S1DREG_BBLT_SRC_START1,        0x00},
2894 +       {S1DREG_BBLT_SRC_START2,        0x00},
2895 +       {S1DREG_BBLT_DST_START0,        0x00},
2896 +       {S1DREG_BBLT_DST_START1,        0x00},
2897 +       {S1DREG_BBLT_DST_START2,        0x00},
2898 +       {S1DREG_BBLT_MEM_OFF0,          0x00},
2899 +       {S1DREG_BBLT_MEM_OFF1,          0x00},
2900 +       {S1DREG_BBLT_WIDTH0,            0x00},
2901 +       {S1DREG_BBLT_WIDTH1,            0x00},
2902 +       {S1DREG_BBLT_HEIGHT0,           0x00},
2903 +       {S1DREG_BBLT_HEIGHT1,           0x00},
2904 +       {S1DREG_BBLT_BGC0,              0x00},
2905 +       {S1DREG_BBLT_BGC1,              0x00},
2906 +       {S1DREG_BBLT_FGC0,              0x00},
2907 +       {S1DREG_BBLT_FGC1,              0x00},
2908 +       {S1DREG_LKUP_MODE,              0x00},  /* LCD LUT r | LCD and CRT/TV LUT w */
2909 +       {S1DREG_LKUP_ADDR,              0x00},
2910 +       {S1DREG_PS_CNF,                 0x10},  /* Power Save disable */
2911 +       {S1DREG_PS_STATUS,              0x02},  /* LCD Panel down, mem up */
2912 +       {S1DREG_CPU2MEM_WDOGT,          0x00},
2913 +       {S1DREG_COM_DISP_MODE,          0x02},  /* enable CRT display output */
2914 +};
2915 +
2916 +static struct s1d13xxxfb_pdata ek_s1dfb_pdata = {
2917 +       .initregs               = ek_s1dfb_initregs,
2918 +       .initregssize           = ARRAY_SIZE(ek_s1dfb_initregs),
2919 +       .platform_init_video    = ek_init_video,
2920 +};
2921 +
2922 +static u64 s1dfb_dmamask = 0xffffffffUL;
2923 +
2924 +static struct resource ek_s1dfb_resource[] = {
2925 +       [0] = { /* video mem */
2926 +               .name   = "s1d13806 memory",
2927 +               .start  = AT91_FB_VMEM_BASE,
2928 +               .end    = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
2929 +               .flags  = IORESOURCE_MEM,
2930 +       },
2931 +       [1] = { /* video registers */
2932 +               .name   = "s1d13806 registers",
2933 +               .start  = AT91_FB_REG_BASE,
2934 +               .end    = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
2935 +               .flags  = IORESOURCE_MEM,
2936 +       },
2937 +};
2938 +
2939 +static struct platform_device ek_s1dfb_device = {
2940 +       .name           = "s1d13806fb",
2941 +       .id             = -1,
2942 +       .dev            = {
2943 +                       .dma_mask               = &s1dfb_dmamask,
2944 +                       .coherent_dma_mask      = 0xffffffff,
2945 +                       .platform_data          = &ek_s1dfb_pdata,
2946 +       },
2947 +       .resource       = ek_s1dfb_resource,
2948 +       .num_resources  = ARRAY_SIZE(ek_s1dfb_resource),
2949 +};
2950 +
2951 +static void __init ek_add_device_video(void)
2952 +{
2953 +       platform_device_register(&ek_s1dfb_device);
2954 +}
2955 +#else
2956 +static void __init ek_add_device_video(void) {}
2957 +#endif
2958 +
2959  static struct at91_eth_data __initdata ek_eth_data = {
2960         .phy_irq_pin    = AT91_PIN_PC4,
2961         .is_rmii        = 1,
2962 @@ -113,7 +294,7 @@ static struct spi_board_info ek_spi_devi
2963  #define EK_FLASH_SIZE  0x200000
2964
2965  static struct physmap_flash_data ek_flash_data = {
2966 -       .width  = 2,
2967 +       .width          = 2,
2968  };
2969
2970  static struct resource ek_flash_resource = {
2971 @@ -132,6 +313,18 @@ static struct platform_device ek_flash =
2972         .num_resources  = 1,
2973  };
2974
2975 +static struct at91_gpio_led ek_leds[] = {
2976 +       {
2977 +               .name           = "led0",
2978 +               .gpio           = AT91_PIN_PB1,
2979 +               .trigger        = "heartbeat",
2980 +       },
2981 +       {
2982 +               .name           = "led1",
2983 +               .gpio           = AT91_PIN_PB2,
2984 +               .trigger        = "timer",
2985 +       }
2986 +};
2987
2988  static void __init ek_board_init(void)
2989  {
2990 @@ -158,8 +351,10 @@ static void __init ek_board_init(void)
2991  #endif
2992         /* NOR Flash */
2993         platform_device_register(&ek_flash);
2994 +       /* LEDs */
2995 +       at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
2996         /* VGA */
2997 -//     ek_add_device_video();
2998 +       ek_add_device_video();
2999  }
3000
3001  MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
3002 Index: linux-2.6.21.7/arch/arm/mach-at91/board-kb9202.c
3003 ===================================================================
3004 --- linux-2.6.21.7.orig/arch/arm/mach-at91/board-kb9202.c
3005 +++ linux-2.6.21.7/arch/arm/mach-at91/board-kb9202.c
3006 @@ -37,6 +37,8 @@
3007  #include <asm/arch/board.h>
3008  #include <asm/arch/gpio.h>
3009
3010 +#include <asm/arch/at91rm9200_mc.h>
3011 +
3012  #include "generic.h"
3013
3014
3015 @@ -111,6 +113,48 @@ static struct at91_nand_data __initdata
3016         .partition_info = nand_partitions,
3017  };
3018
3019 +
3020 +#if defined(CONFIG_FB_S1D15605)
3021 +#warning "Rather pass reset pin via platform_data"
3022 +static struct resource kb9202_lcd_resources[] = {
3023 +       [0] = {
3024 +               .start  = AT91_CHIPSELECT_2,
3025 +               .end    = AT91_CHIPSELECT_2 + 0x200FF,
3026 +               .flags  = IORESOURCE_MEM
3027 +       },
3028 +       [1] = { /* reset pin */
3029 +               .start  = AT91_PIN_PC22,
3030 +               .end    = AT91_PIN_PC22,
3031 +               .flags  = IORESOURCE_MEM
3032 +       },
3033 +};
3034 +
3035 +static struct platform_device kb9202_lcd_device = {
3036 +       .name           = "s1d15605fb",
3037 +       .id             = 0,
3038 +       .num_resources  = ARRAY_SIZE(kb9202_lcd_resources),
3039 +       .resource       = kb9202_lcd_resources,
3040 +};
3041 +
3042 +static void __init kb9202_add_device_lcd(void)
3043 +{
3044 +       /* In case the boot loader did not set the chip select mode and timing */
3045 +       at91_sys_write(AT91_SMC_CSR(2),
3046 +               AT91_SMC_WSEN | AT91_SMC_NWS_(18) | AT91_SMC_TDF_(1) | AT91_SMC_DBW_8 |
3047 +               AT91_SMC_RWSETUP_(1) | AT91_SMC_RWHOLD_(1));
3048 +
3049 +       /* Backlight pin = output, off */
3050 +       at91_set_gpio_output(AT91_PIN_PC23, 0);
3051 +
3052 +       /* Reset pin = output, in reset */
3053 +       at91_set_gpio_output(AT91_PIN_PC22, 0);
3054 +
3055 +       platform_device_register(&kb9202_lcd_device);
3056 +}
3057 +#else
3058 +static void __init kb9202_add_device_lcd(void) {}
3059 +#endif
3060 +
3061  static void __init kb9202_board_init(void)
3062  {
3063         /* Serial */
3064 @@ -129,6 +173,8 @@ static void __init kb9202_board_init(voi
3065         at91_add_device_spi(NULL, 0);
3066         /* NAND */
3067         at91_add_device_nand(&kb9202_nand_data);
3068 +       /* LCD  */
3069 +       kb9202_add_device_lcd();
3070  }
3071
3072  MACHINE_START(KB9200, "KB920x")
3073 Index: linux-2.6.21.7/arch/arm/mach-at91/board-sam9260ek.c
3074 ===================================================================
3075 --- linux-2.6.21.7.orig/arch/arm/mach-at91/board-sam9260ek.c
3076 +++ linux-2.6.21.7/arch/arm/mach-at91/board-sam9260ek.c
3077 @@ -104,9 +104,9 @@ static struct spi_board_info ek_spi_devi
3078         },
3079  #endif
3080  #endif
3081 -#if defined(CONFIG_SND_AT73C213)
3082 +#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
3083         {       /* AT73C213 DAC */
3084 -               .modalias       = "snd_at73c213",
3085 +               .modalias       = "at73c213",
3086                 .chip_select    = 0,
3087                 .max_speed_hz   = 10 * 1000 * 1000,
3088                 .bus_num        = 1,
3089 @@ -118,7 +118,7 @@ static struct spi_board_info ek_spi_devi
3090  /*
3091   * MACB Ethernet device
3092   */
3093 -static struct __initdata at91_eth_data ek_macb_data = {
3094 +static struct at91_eth_data __initdata ek_macb_data = {
3095         .phy_irq_pin    = AT91_PIN_PA7,
3096         .is_rmii        = 1,
3097  };
3098 @@ -188,6 +188,8 @@ static void __init ek_board_init(void)
3099         at91_add_device_eth(&ek_macb_data);
3100         /* MMC */
3101         at91_add_device_mmc(0, &ek_mmc_data);
3102 +       /* I2C */
3103 +       at91_add_device_i2c();
3104  }
3105
3106  MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
3107 Index: linux-2.6.21.7/arch/arm/mach-at91/board-sam9261ek.c
3108 ===================================================================
3109 --- linux-2.6.21.7.orig/arch/arm/mach-at91/board-sam9261ek.c
3110 +++ linux-2.6.21.7/arch/arm/mach-at91/board-sam9261ek.c
3111 @@ -25,7 +25,11 @@
3112  #include <linux/module.h>
3113  #include <linux/platform_device.h>
3114  #include <linux/spi/spi.h>
3115 +#include <linux/spi/ads7846.h>
3116  #include <linux/dm9000.h>
3117 +#include <linux/fb.h>
3118 +
3119 +#include <video/atmel_lcdc.h>
3120
3121  #include <asm/hardware.h>
3122  #include <asm/setup.h>
3123 @@ -59,6 +63,9 @@ static void __init ek_map_io(void)
3124         /* Initialize processor: 18.432 MHz crystal */
3125         at91sam9261_initialize(18432000);
3126
3127 +       /* Setup the LEDs */
3128 +       at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
3129 +
3130         /* Setup the serial ports and console */
3131         at91_init_serial(&ek_uart_config);
3132  }
3133 @@ -195,6 +202,41 @@ static struct at91_nand_data __initdata
3134  };
3135
3136  /*
3137 + * ADS7846 Touchscreen
3138 + */
3139 +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
3140 +
3141 +static int ads7843_pendown_state(void)
3142 +{
3143 +       return !at91_get_gpio_value(AT91_PIN_PC2);      /* Touchscreen PENIRQ */
3144 +}
3145 +
3146 +static struct ads7846_platform_data ads_info = {
3147 +       .model                  = 7843,
3148 +       .x_min                  = 150,
3149 +       .x_max                  = 3830,
3150 +       .y_min                  = 190,
3151 +       .y_max                  = 3830,
3152 +       .vref_delay_usecs       = 100,
3153 +       .x_plate_ohms           = 450,
3154 +       .y_plate_ohms           = 250,
3155 +       .pressure_max           = 15000,
3156 +       .debounce_max           = 1,
3157 +       .debounce_rep           = 0,
3158 +       .debounce_tol           = (~0),
3159 +       .get_pendown_state      = ads7843_pendown_state,
3160 +};
3161 +
3162 +static void __init ek_add_device_ts(void)
3163 +{
3164 +       at91_set_B_periph(AT91_PIN_PC2, 1);     /* External IRQ0, with pullup */
3165 +       at91_set_gpio_input(AT91_PIN_PA11, 1);  /* Touchscreen BUSY signal */
3166 +}
3167 +#else
3168 +static void __init ek_add_device_ts(void) {}
3169 +#endif
3170 +
3171 +/*
3172   * SPI devices
3173   */
3174  static struct spi_board_info ek_spi_devices[] = {
3175 @@ -204,6 +246,17 @@ static struct spi_board_info ek_spi_devi
3176                 .max_speed_hz   = 15 * 1000 * 1000,
3177                 .bus_num        = 0,
3178         },
3179 +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
3180 +       {
3181 +               .modalias       = "ads7846",
3182 +               .chip_select    = 2,
3183 +               .max_speed_hz   = 125000 * 26,  /* (max sample rate @ 3V) * (cmd + data + overhead) */
3184 +               .bus_num        = 0,
3185 +               .platform_data  = &ads_info,
3186 +               .irq            = AT91SAM9261_ID_IRQ0,
3187 +               .controller_data = AT91_PIN_PA28,       /* CS pin */
3188 +       },
3189 +#endif
3190  #if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
3191         {       /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
3192                 .modalias       = "mtd_dataflash",
3193 @@ -211,9 +264,9 @@ static struct spi_board_info ek_spi_devi
3194                 .max_speed_hz   = 15 * 1000 * 1000,
3195                 .bus_num        = 0,
3196         },
3197 -#elif defined(CONFIG_SND_AT73C213)
3198 +#elif defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
3199         {       /* AT73C213 DAC */
3200 -               .modalias       = "snd_at73c213",
3201 +               .modalias       = "at73c213",
3202                 .chip_select    = 3,
3203                 .max_speed_hz   = 10 * 1000 * 1000,
3204                 .bus_num        = 0,
3205 @@ -222,6 +275,65 @@ static struct spi_board_info ek_spi_devi
3206  };
3207
3208
3209 +/*
3210 + * LCD Controller
3211 + */
3212 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
3213 +static struct fb_videomode at91_tft_vga_modes[] = {
3214 +       {
3215 +               .name           = "TX09D50VM1CCA @ 60",
3216 +               .refresh        = 60,
3217 +               .xres           = 240,          .yres           = 320,
3218 +               .pixclock       = KHZ2PICOS(4965),
3219 +
3220 +               .left_margin    = 1,            .right_margin   = 33,
3221 +               .upper_margin   = 1,            .lower_margin   = 0,
3222 +               .hsync_len      = 5,            .vsync_len      = 1,
3223 +
3224 +               .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
3225 +               .vmode          = FB_VMODE_NONINTERLACED,
3226 +       },
3227 +};
3228 +
3229 +static struct fb_monspecs at91fb_default_monspecs = {
3230 +       .manufacturer   = "HIT",
3231 +       .monitor        = "TX09D50VM1CCA",
3232 +
3233 +       .modedb         = at91_tft_vga_modes,
3234 +       .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
3235 +       .hfmin          = 15000,
3236 +       .hfmax          = 64000,
3237 +       .vfmin          = 50,
3238 +       .vfmax          = 150,
3239 +};
3240 +
3241 +#define AT91SAM9261_DEFAULT_LCDCON2    (ATMEL_LCDC_MEMOR_LITTLE \
3242 +                                       | ATMEL_LCDC_DISTYPE_TFT    \
3243 +                                       | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
3244 +
3245 +static void at91_lcdc_power_control(int on)
3246 +{
3247 +       if (on)
3248 +               at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
3249 +       else
3250 +               at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
3251 +}
3252 +
3253 +/* Driver datas */
3254 +static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
3255 +       .default_bpp                    = 16,
3256 +       .default_dmacon                 = ATMEL_LCDC_DMAEN,
3257 +       .default_lcdcon2                = AT91SAM9261_DEFAULT_LCDCON2,
3258 +       .default_monspecs               = &at91fb_default_monspecs,
3259 +       .atmel_lcdfb_power_control      = at91_lcdc_power_control,
3260 +       .guard_time                     = 1,
3261 +};
3262 +
3263 +#else
3264 +static struct atmel_lcdfb_info __initdata ek_lcdc_data;
3265 +#endif
3266 +
3267 +
3268  static void __init ek_board_init(void)
3269  {
3270         /* Serial */
3271 @@ -241,10 +353,14 @@ static void __init ek_board_init(void)
3272  #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
3273         /* SPI */
3274         at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
3275 +       /* Touchscreen */
3276 +       ek_add_device_ts();
3277  #else
3278         /* MMC */
3279         at91_add_device_mmc(0, &ek_mmc_data);
3280  #endif
3281 +       /* LCD Controller */
3282 +       at91_add_device_lcdc(&ek_lcdc_data);
3283  }
3284
3285  MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
3286 Index: linux-2.6.21.7/arch/arm/mach-at91/board-sam9263ek.c
3287 ===================================================================
3288 --- linux-2.6.21.7.orig/arch/arm/mach-at91/board-sam9263ek.c
3289 +++ linux-2.6.21.7/arch/arm/mach-at91/board-sam9263ek.c
3290 @@ -25,6 +25,10 @@
3291  #include <linux/module.h>
3292  #include <linux/platform_device.h>
3293  #include <linux/spi/spi.h>
3294 +#include <linux/spi/ads7846.h>
3295 +#include <linux/fb.h>
3296 +
3297 +#include <video/atmel_lcdc.h>
3298
3299  #include <asm/hardware.h>
3300  #include <asm/setup.h>
3301 @@ -86,6 +90,40 @@ static struct at91_udc_data __initdata e
3302
3303
3304  /*
3305 + * ADS7846 Touchscreen
3306 + */
3307 +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
3308 +static int ads7843_pendown_state(void)
3309 +{
3310 +       return !at91_get_gpio_value(AT91_PIN_PA15);     /* Touchscreen PENIRQ */
3311 +}
3312 +
3313 +static struct ads7846_platform_data ads_info = {
3314 +       .model                  = 7843,
3315 +       .x_min                  = 150,
3316 +       .x_max                  = 3830,
3317 +       .y_min                  = 190,
3318 +       .y_max                  = 3830,
3319 +       .vref_delay_usecs       = 100,
3320 +       .x_plate_ohms           = 450,
3321 +       .y_plate_ohms           = 250,
3322 +       .pressure_max           = 15000,
3323 +       .debounce_max           = 1,
3324 +       .debounce_rep           = 0,
3325 +       .debounce_tol           = (~0),
3326 +       .get_pendown_state      = ads7843_pendown_state,
3327 +};
3328 +
3329 +static void __init ek_add_device_ts(void)
3330 +{
3331 +       at91_set_B_periph(AT91_PIN_PA15, 1);    /* External IRQ1, with pullup */
3332 +       at91_set_gpio_input(AT91_PIN_PA31, 1);  /* Touchscreen BUSY signal */
3333 +}
3334 +#else
3335 +static void __init ek_add_device_ts(void) {}
3336 +#endif
3337 +
3338 +/*
3339   * SPI devices.
3340   */
3341  static struct spi_board_info ek_spi_devices[] = {
3342 @@ -97,6 +135,16 @@ static struct spi_board_info ek_spi_devi
3343                 .bus_num        = 0,
3344         },
3345  #endif
3346 +#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
3347 +       {
3348 +               .modalias       = "ads7846",
3349 +               .chip_select    = 3,
3350 +               .max_speed_hz   = 125000 * 26,  /* (max sample rate @ 3V) * (cmd + data + overhead) */
3351 +               .bus_num        = 0,
3352 +               .platform_data  = &ads_info,
3353 +               .irq            = AT91SAM9263_ID_IRQ1,
3354 +       },
3355 +#endif
3356  };
3357
3358
3359 @@ -112,6 +160,14 @@ static struct at91_mmc_data __initdata e
3360
3361
3362  /*
3363 + * MACB Ethernet device
3364 + */
3365 +static struct at91_eth_data __initdata ek_macb_data = {
3366 +       .is_rmii        = 1,
3367 +};
3368 +
3369 +
3370 +/*
3371   * NAND flash
3372   */
3373  static struct mtd_partition __initdata ek_nand_partition[] = {
3374 @@ -148,6 +204,73 @@ static struct at91_nand_data __initdata
3375  };
3376
3377
3378 +/*
3379 + * LCD Controller
3380 + */
3381 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
3382 +static struct fb_videomode at91_tft_vga_modes[] = {
3383 +       {
3384 +               .name           = "TX09D50VM1CCA @ 60",
3385 +               .refresh        = 60,
3386 +               .xres           = 240,          .yres           = 320,
3387 +               .pixclock       = KHZ2PICOS(4965),
3388 +
3389 +               .left_margin    = 1,            .right_margin   = 33,
3390 +               .upper_margin   = 1,            .lower_margin   = 0,
3391 +               .hsync_len      = 5,            .vsync_len      = 1,
3392 +
3393 +               .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
3394 +               .vmode          = FB_VMODE_NONINTERLACED,
3395 +       },
3396 +};
3397 +
3398 +static struct fb_monspecs at91fb_default_monspecs = {
3399 +       .manufacturer   = "HIT",
3400 +       .monitor        = "TX09D70VM1CCA",
3401 +
3402 +       .modedb         = at91_tft_vga_modes,
3403 +       .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
3404 +       .hfmin          = 15000,
3405 +       .hfmax          = 64000,
3406 +       .vfmin          = 50,
3407 +       .vfmax          = 150,
3408 +};
3409 +
3410 +#define AT91SAM9263_DEFAULT_LCDCON2    (ATMEL_LCDC_MEMOR_LITTLE \
3411 +                                       | ATMEL_LCDC_DISTYPE_TFT    \
3412 +                                       | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
3413 +
3414 +static void at91_lcdc_power_control(int on)
3415 +{
3416 +       if (on)
3417 +               at91_set_gpio_value(AT91_PIN_PD12, 0);  /* power up */
3418 +       else
3419 +               at91_set_gpio_value(AT91_PIN_PD12, 1);  /* power down */
3420 +}
3421 +
3422 +/* Driver datas */
3423 +static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
3424 +       .default_bpp                    = 16,
3425 +       .default_dmacon                 = ATMEL_LCDC_DMAEN,
3426 +       .default_lcdcon2                = AT91SAM9263_DEFAULT_LCDCON2,
3427 +       .default_monspecs               = &at91fb_default_monspecs,
3428 +       .atmel_lcdfb_power_control      = at91_lcdc_power_control,
3429 +       .guard_time                     = 1,
3430 +};
3431 +
3432 +#else
3433 +static struct atmel_lcdfb_info __initdata ek_lcdc_data;
3434 +#endif
3435 +
3436 +
3437 +/*
3438 + * AC97
3439 + */
3440 +static struct atmel_ac97_data ek_ac97_data = {
3441 +       .reset_pin      = AT91_PIN_PA13,
3442 +};
3443 +
3444 +
3445  static void __init ek_board_init(void)
3446  {
3447         /* Serial */
3448 @@ -157,11 +280,22 @@ static void __init ek_board_init(void)
3449         /* USB Device */
3450         at91_add_device_udc(&ek_udc_data);
3451         /* SPI */
3452 +       at91_set_gpio_output(AT91_PIN_PE20, 1);         /* select spi0 clock */
3453         at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
3454 +       /* Touchscreen */
3455 +       ek_add_device_ts();
3456         /* MMC */
3457         at91_add_device_mmc(1, &ek_mmc_data);
3458 +       /* Ethernet */
3459 +       at91_add_device_eth(&ek_macb_data);
3460         /* NAND */
3461         at91_add_device_nand(&ek_nand_data);
3462 +       /* I2C */
3463 +       at91_add_device_i2c();
3464 +       /* LCD Controller */
3465 +       at91_add_device_lcdc(&ek_lcdc_data);
3466 +       /* AC97 */
3467 +       at91_add_device_ac97(&ek_ac97_data);
3468  }
3469
3470  MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
3471 Index: linux-2.6.21.7/arch/arm/mach-at91/board-sam9rlek.c
3472 ===================================================================
3473 --- /dev/null
3474 +++ linux-2.6.21.7/arch/arm/mach-at91/board-sam9rlek.c
3475 @@ -0,0 +1,204 @@
3476 +/*
3477 + *  Copyright (C) 2005 SAN People
3478 + *  Copyright (C) 2007 Atmel Corporation
3479 + *
3480 + * This file is subject to the terms and conditions of the GNU General Public
3481 + * License.  See the file COPYING in the main directory of this archive for
3482 + * more details.
3483 + */
3484 +
3485 +#include <linux/types.h>
3486 +#include <linux/init.h>
3487 +#include <linux/mm.h>
3488 +#include <linux/module.h>
3489 +#include <linux/platform_device.h>
3490 +#include <linux/spi/spi.h>
3491 +#include <linux/fb.h>
3492 +#include <linux/clk.h>
3493 +
3494 +#include <video/atmel_lcdc.h>
3495 +
3496 +#include <asm/hardware.h>
3497 +#include <asm/setup.h>
3498 +#include <asm/mach-types.h>
3499 +#include <asm/irq.h>
3500 +
3501 +#include <asm/mach/arch.h>
3502 +#include <asm/mach/map.h>
3503 +#include <asm/mach/irq.h>
3504 +
3505 +#include <asm/arch/board.h>
3506 +#include <asm/arch/gpio.h>
3507 +#include <asm/arch/at91sam926x_mc.h>
3508 +
3509 +#include "generic.h"
3510 +
3511 +
3512 +/*
3513 + * Serial port configuration.
3514 + *    0 .. 3 = USART0 .. USART3
3515 + *    4      = DBGU
3516 + */
3517 +static struct at91_uart_config __initdata ek_uart_config = {
3518 +       .console_tty    = 0,                            /* ttyS0 */
3519 +       .nr_tty         = 2,
3520 +       .tty_map        = { 4, 0, -1, -1, -1 }          /* ttyS0, ..., ttyS4 */
3521 +};
3522 +
3523 +static void __init ek_map_io(void)
3524 +{
3525 +       /* Initialize processor: 12.000 MHz crystal */
3526 +       at91sam9rl_initialize(12000000);
3527 +
3528 +       /* Setup the serial ports and console */
3529 +       at91_init_serial(&ek_uart_config);
3530 +}
3531 +
3532 +static void __init ek_init_irq(void)
3533 +{
3534 +       at91sam9rl_init_interrupts(NULL);
3535 +}
3536 +
3537 +
3538 +/*
3539 + * MCI (SD/MMC)
3540 + */
3541 +static struct at91_mmc_data __initdata ek_mmc_data = {
3542 +       .wire4          = 1,
3543 +       .det_pin        = AT91_PIN_PA15,
3544 +//     .wp_pin         = ... not connected
3545 +//     .vcc_pin        = ... not connected
3546 +};
3547 +
3548 +
3549 +/*
3550 + * NAND flash
3551 + */
3552 +static struct mtd_partition __initdata ek_nand_partition[] = {
3553 +       {
3554 +               .name   = "Partition 1",
3555 +               .offset = 0,
3556 +               .size   = 256 * 1024,
3557 +       },
3558 +       {
3559 +               .name   = "Partition 2",
3560 +               .offset = 256 * 1024 ,
3561 +               .size   = MTDPART_SIZ_FULL,
3562 +       },
3563 +};
3564 +
3565 +static struct mtd_partition *nand_partitions(int size, int *num_partitions)
3566 +{
3567 +       *num_partitions = ARRAY_SIZE(ek_nand_partition);
3568 +       return ek_nand_partition;
3569 +}
3570 +
3571 +static struct at91_nand_data __initdata ek_nand_data = {
3572 +       .ale            = 21,
3573 +       .cle            = 22,
3574 +//     .det_pin        = ... not connected
3575 +       .rdy_pin        = AT91_PIN_PD17,
3576 +       .enable_pin     = AT91_PIN_PB6,
3577 +       .partition_info = nand_partitions,
3578 +       .bus_width_16   = 0,
3579 +};
3580 +
3581 +
3582 +/*
3583 + * SPI devices
3584 + */
3585 +static struct spi_board_info ek_spi_devices[] = {
3586 +       {       /* DataFlash chip */
3587 +               .modalias       = "mtd_dataflash",
3588 +               .chip_select    = 0,
3589 +               .max_speed_hz   = 15 * 1000 * 1000,
3590 +               .bus_num        = 0,
3591 +       },
3592 +};
3593 +
3594 +
3595 +/*
3596 + * LCD Controller
3597 + */
3598 +#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
3599 +static struct fb_videomode at91_tft_vga_modes[] = {
3600 +       {
3601 +               .name           = "TX09D50VM1CCA @ 60",
3602 +               .refresh        = 60,
3603 +               .xres           = 240,          .yres           = 320,
3604 +               .pixclock       = KHZ2PICOS(4965),
3605 +
3606 +               .left_margin    = 1,            .right_margin   = 33,
3607 +               .upper_margin   = 1,            .lower_margin   = 0,
3608 +               .hsync_len      = 5,            .vsync_len      = 1,
3609 +
3610 +               .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
3611 +               .vmode          = FB_VMODE_NONINTERLACED,
3612 +       },
3613 +};
3614 +
3615 +static struct fb_monspecs at91fb_default_monspecs = {
3616 +       .manufacturer   = "HIT",
3617 +       .monitor        = "TX09D50VM1CCA",
3618 +
3619 +       .modedb         = at91_tft_vga_modes,
3620 +       .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
3621 +       .hfmin          = 15000,
3622 +       .hfmax          = 64000,
3623 +       .vfmin          = 50,
3624 +       .vfmax          = 150,
3625 +};
3626 +
3627 +#define AT91SAM9RL_DEFAULT_LCDCON2     (ATMEL_LCDC_MEMOR_LITTLE \
3628 +                                       | ATMEL_LCDC_DISTYPE_TFT \
3629 +                                       | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
3630 +
3631 +static void at91_lcdc_power_control(int on)
3632 +{
3633 +       if (on)
3634 +               at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
3635 +       else
3636 +               at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
3637 +}
3638 +
3639 +/* Driver datas */
3640 +static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
3641 +       .default_bpp                    = 16,
3642 +       .default_dmacon                 = ATMEL_LCDC_DMAEN,
3643 +       .default_lcdcon2                = AT91SAM9RL_DEFAULT_LCDCON2,
3644 +       .default_monspecs               = &at91fb_default_monspecs,
3645 +       .atmel_lcdfb_power_control      = at91_lcdc_power_control,
3646 +       .guard_time                     = 1,
3647 +};
3648 +
3649 +#else
3650 +static struct atmel_lcdfb_info __initdata ek_lcdc_data;
3651 +#endif
3652 +
3653 +
3654 +static void __init ek_board_init(void)
3655 +{
3656 +       /* Serial */
3657 +       at91_add_device_serial();
3658 +       /* I2C */
3659 +       at91_add_device_i2c();
3660 +       /* NAND */
3661 +       at91_add_device_nand(&ek_nand_data);
3662 +       /* SPI */
3663 +       at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
3664 +       /* MMC */
3665 +       at91_add_device_mmc(0, &ek_mmc_data);
3666 +       /* LCD Controller */
3667 +       at91_add_device_lcdc(&ek_lcdc_data);
3668 +}
3669 +
3670 +MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
3671 +       /* Maintainer: Atmel */
3672 +       .phys_io        = AT91_BASE_SYS,
3673 +       .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
3674 +       .boot_params    = AT91_SDRAM_BASE + 0x100,
3675 +       .timer          = &at91sam926x_timer,
3676 +       .map_io         = ek_map_io,
3677 +       .init_irq       = ek_init_irq,
3678 +       .init_machine   = ek_board_init,
3679 +MACHINE_END
3680 Index: linux-2.6.21.7/arch/arm/mach-at91/clock.c
3681 ===================================================================
3682 --- linux-2.6.21.7.orig/arch/arm/mach-at91/clock.c
3683 +++ linux-2.6.21.7/arch/arm/mach-at91/clock.c
3684 @@ -32,6 +32,7 @@
3685  #include <asm/arch/cpu.h>
3686
3687  #include "clock.h"
3688 +#include "generic.h"
3689
3690
3691  /*
3692 @@ -254,6 +255,23 @@ EXPORT_SYMBOL(clk_get_rate);
3693
3694  /*------------------------------------------------------------------------*/
3695
3696 +#ifdef CONFIG_PM
3697 +
3698 +int clk_must_disable(struct clk *clk)
3699 +{
3700 +       if (!at91_suspend_entering_slow_clock())
3701 +               return 0;
3702 +
3703 +       while (clk->parent)
3704 +               clk = clk->parent;
3705 +       return clk != &clk32k;
3706 +}
3707 +EXPORT_SYMBOL(clk_must_disable);
3708 +
3709 +#endif
3710 +
3711 +/*------------------------------------------------------------------------*/
3712 +
3713  #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
3714
3715  /*
3716 @@ -375,6 +393,7 @@ static int at91_clk_show(struct seq_file
3717         seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
3718
3719         seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
3720 +#warning "Hard-coded PCK"
3721         for (i = 0; i < 4; i++)
3722                 seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
3723         seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
3724 Index: linux-2.6.21.7/arch/arm/mach-at91/generic.h
3725 ===================================================================
3726 --- linux-2.6.21.7.orig/arch/arm/mach-at91/generic.h
3727 +++ linux-2.6.21.7/arch/arm/mach-at91/generic.h
3728 @@ -13,12 +13,14 @@ extern void __init at91rm9200_initialize
3729  extern void __init at91sam9260_initialize(unsigned long main_clock);
3730  extern void __init at91sam9261_initialize(unsigned long main_clock);
3731  extern void __init at91sam9263_initialize(unsigned long main_clock);
3732 +extern void __init at91sam9rl_initialize(unsigned long main_clock);
3733
3734   /* Interrupts */
3735  extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
3736  extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
3737  extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
3738  extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
3739 +extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
3740  extern void __init at91_aic_init(unsigned int priority[]);
3741
3742   /* Timer */
3743 @@ -34,6 +36,7 @@ extern void __init at91_clock_associate(
3744   /* Power Management */
3745  extern void at91_irq_suspend(void);
3746  extern void at91_irq_resume(void);
3747 +extern int at91_suspend_entering_slow_clock(void);
3748
3749   /* GPIO */
3750  #define AT91RM9200_PQFP                3       /* AT91RM9200 PQFP package has 3 banks */
3751 Index: linux-2.6.21.7/arch/arm/mach-at91/ics1523.c
3752 ===================================================================
3753 --- /dev/null
3754 +++ linux-2.6.21.7/arch/arm/mach-at91/ics1523.c
3755 @@ -0,0 +1,207 @@
3756 +/*
3757 + * arch/arm/mach-at91rm9200/ics1523.c
3758 + *
3759 + *  Copyright (C) 2003 ATMEL Rousset
3760 + *
3761 + * This program is free software; you can redistribute it and/or modify
3762 + * it under the terms of the GNU General Public License as published by
3763 + * the Free Software Foundation; either version 2 of the License, or
3764 + * (at your option) any later version.
3765 + *
3766 + * This program is distributed in the hope that it will be useful,
3767 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3768 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3769 + * GNU General Public License for more details.
3770 + *
3771 + * You should have received a copy of the GNU General Public License
3772 + * along with this program; if not, write to the Free Software
3773 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3774 + */
3775 +
3776 +#include <asm/hardware.h>
3777 +#include <asm/io.h>
3778 +
3779 +#include <linux/clk.h>
3780 +#include <linux/delay.h>
3781 +#include <linux/err.h>
3782 +#include <linux/init.h>
3783 +
3784 +#include <asm/arch/ics1523.h>
3785 +#include <asm/arch/at91_twi.h>
3786 +#include <asm/arch/gpio.h>
3787 +
3788 +/* TWI Errors */
3789 +#define        AT91_TWI_ERROR  (AT91_TWI_NACK | AT91_TWI_UNRE | AT91_TWI_OVRE)
3790 +
3791 +
3792 +static void __iomem *twi_base;
3793 +
3794 +#define at91_twi_read(reg)             __raw_readl(twi_base + (reg))
3795 +#define at91_twi_write(reg, val)       __raw_writel((val), twi_base + (reg))
3796 +
3797 +
3798 +/* -----------------------------------------------------------------------------
3799 + * Initialization of TWI CLOCK
3800 + * ----------------------------------------------------------------------------- */
3801 +
3802 +static void at91_ics1523_SetTwiClock(unsigned int mck_khz)
3803 +{
3804 +       int sclock;
3805 +
3806 +       /* Here, CKDIV = 1 and CHDIV = CLDIV  ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
3807 +       sclock = (10*mck_khz / ICS_TRANSFER_RATE);
3808 +       if (sclock % 10 >= 5)
3809 +               sclock = (sclock /10) - 5;
3810 +       else
3811 +               sclock = (sclock /10)- 6;
3812 +       sclock = (sclock + (4 - sclock %4)) >> 2;       /* div 4 */
3813 +
3814 +       at91_twi_write(AT91_TWI_CWGR, 0x00010000 | sclock | (sclock << 8));
3815 +}
3816 +
3817 +/* -----------------------------------------------------------------------------
3818 + * Read a byte with TWI Interface from the Clock Generator ICS1523
3819 + * ----------------------------------------------------------------------------- */
3820 +
3821 +static int at91_ics1523_ReadByte(unsigned char reg_address, unsigned char *data_in)
3822 +{
3823 +       int Status, nb_trial;
3824 +
3825 +       at91_twi_write(AT91_TWI_MMR, AT91_TWI_MREAD | AT91_TWI_IADRSZ_1 | ((ICS_ADDR << 16) & AT91_TWI_DADR));
3826 +       at91_twi_write(AT91_TWI_IADR, reg_address);
3827 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
3828 +
3829 +       /* Program temporizing period (300us) */
3830 +       udelay(300);
3831 +
3832 +       /* Wait TXcomplete ... */
3833 +       nb_trial = 0;
3834 +       Status = at91_twi_read(AT91_TWI_SR);
3835 +       while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) {
3836 +               nb_trial++;
3837 +               Status = at91_twi_read(AT91_TWI_SR);
3838 +       }
3839 +
3840 +       if (Status & AT91_TWI_TXCOMP) {
3841 +               *data_in = (unsigned char) at91_twi_read(AT91_TWI_RHR);
3842 +               return ICS1523_ACCESS_OK;
3843 +       }
3844 +       else
3845 +               return ICS1523_ACCESS_ERROR;
3846 +}
3847 +
3848 +/* -----------------------------------------------------------------------------
3849 + * Write a byte with TWI Interface to the Clock Generator ICS1523
3850 + * ----------------------------------------------------------------------------- */
3851 +
3852 +static int at91_ics1523_WriteByte(unsigned char reg_address, unsigned char data_out)
3853 +{
3854 +       int Status, nb_trial;
3855 +
3856 +       at91_twi_write(AT91_TWI_MMR, AT91_TWI_IADRSZ_1 | ((ICS_ADDR << 16) & AT91_TWI_DADR));
3857 +       at91_twi_write(AT91_TWI_IADR, reg_address);
3858 +       at91_twi_write(AT91_TWI_THR, data_out);
3859 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
3860 +
3861 +       /* Program temporizing period (300us) */
3862 +       udelay(300);
3863 +
3864 +       nb_trial = 0;
3865 +       Status = at91_twi_read(AT91_TWI_SR);
3866 +       while (!(Status & AT91_TWI_TXCOMP) && (nb_trial < 10)) {
3867 +               nb_trial++;
3868 +               if (Status & AT91_TWI_ERROR) {
3869 +                       /* If Underrun OR NACK - Start again */
3870 +                       at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
3871 +
3872 +                       /*  Program temporizing period (300us) */
3873 +                       udelay(300);
3874 +               }
3875 +               Status = at91_twi_read(AT91_TWI_SR);
3876 +       };
3877 +
3878 +       if (Status & AT91_TWI_TXCOMP)
3879 +               return ICS1523_ACCESS_OK;
3880 +       else
3881 +               return ICS1523_ACCESS_ERROR;
3882 +}
3883 +
3884 +/* -----------------------------------------------------------------------------
3885 + * Initialization of the Clock Generator ICS1523
3886 + * ----------------------------------------------------------------------------- */
3887 +
3888 +int at91_ics1523_init(void)
3889 +{
3890 +       int             nb_trial;
3891 +       int             ack = ICS1523_ACCESS_OK;
3892 +       unsigned int    status = 0xffffffff;
3893 +       struct clk      *twi_clk;
3894 +
3895 +       /* Map in TWI peripheral */
3896 +       twi_base = ioremap(AT91RM9200_BASE_TWI, SZ_16K);
3897 +       if (!twi_base)
3898 +               return -ENOMEM;
3899 +
3900 +       /* pins used for TWI interface */
3901 +       at91_set_A_periph(AT91_PIN_PA25, 0);            /* TWD */
3902 +       at91_set_multi_drive(AT91_PIN_PA25, 1);
3903 +       at91_set_A_periph(AT91_PIN_PA26, 0);            /* TWCK */
3904 +       at91_set_multi_drive(AT91_PIN_PA26, 1);
3905 +
3906 +       /* Enable the TWI clock */
3907 +       twi_clk = clk_get(NULL, "twi_clk");
3908 +       if (IS_ERR(twi_clk))
3909 +               return ICS1523_ACCESS_ERROR;
3910 +       clk_enable(twi_clk);
3911 +
3912 +       /* Disable interrupts */
3913 +       at91_twi_write(AT91_TWI_IDR, -1);
3914 +
3915 +       /* Reset peripheral */
3916 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST);
3917 +
3918 +       /* Set Master mode */
3919 +       at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN);
3920 +
3921 +       /* Set TWI Clock Waveform Generator Register */
3922 +       at91_ics1523_SetTwiClock(60000);     /* MCK in KHz = 60000 KHz */
3923 +
3924 +       /* ICS1523 Initialisation */
3925 +       ack |= at91_ics1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) 0);
3926 +       ack |= at91_ics1523_WriteByte ((unsigned char) ICS_OE, (unsigned char) (ICS_OEF | ICS_OET2 | ICS_OETCK));
3927 +       ack |= at91_ics1523_WriteByte ((unsigned char) ICS_OD, (unsigned char) (ICS_INSEL | 0x7F));
3928 +       ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0);
3929 +
3930 +       nb_trial = 0;
3931 +       do {
3932 +               nb_trial++;
3933 +               ack |= at91_ics1523_WriteByte ((unsigned char) ICS_ICR, (unsigned char) (ICS_ENDLS | ICS_ENPLS | ICS_PDEN /*| ICS_FUNCSEL*/));
3934 +               ack |= at91_ics1523_WriteByte ((unsigned char) ICS_LCR, (unsigned char) (ICS_PSD | ICS_PFD));
3935 +               ack |= at91_ics1523_WriteByte ((unsigned char) ICS_FD0, (unsigned char) 0x39) ; /* 0x7A */
3936 +               ack |= at91_ics1523_WriteByte ((unsigned char) ICS_FD1, (unsigned char) 0x00);
3937 +               ack |= at91_ics1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_PLLR));
3938 +
3939 +               /* Program 1ms temporizing period */
3940 +               mdelay(1);
3941 +
3942 +               at91_ics1523_ReadByte ((unsigned char) ICS_SR, (char *)&status);
3943 +       } while (!((unsigned int) status & (unsigned int) ICS_PLLLOCK) && (nb_trial < 10));
3944 +
3945 +       ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAC, (unsigned char) 0x03) ; /* 0x01 */
3946 +       ack |= at91_ics1523_WriteByte ((unsigned char) ICS_SWRST, (unsigned char) (ICS_DPAR));
3947 +
3948 +       /* Program 1ms temporizing period */
3949 +       mdelay(1);
3950 +
3951 +       ack |= at91_ics1523_WriteByte ((unsigned char) ICS_DPAO, (unsigned char) 0x00);
3952 +
3953 +       /* Program 1ms temporizing period */
3954 +       mdelay(1);
3955 +
3956 +       /* All done - cleanup */
3957 +       iounmap(twi_base);
3958 +       clk_disable(twi_clk);
3959 +       clk_put(twi_clk);
3960 +
3961 +       return ack;
3962 +}
3963 Index: linux-2.6.21.7/arch/arm/mach-at91/pm.c
3964 ===================================================================
3965 --- linux-2.6.21.7.orig/arch/arm/mach-at91/pm.c
3966 +++ linux-2.6.21.7/arch/arm/mach-at91/pm.c
3967 @@ -63,6 +63,7 @@ static int at91_pm_prepare(suspend_state
3968   * Verify that all the clocks are correct before entering
3969   * slow-clock mode.
3970   */
3971 +#warning "SAM9260 only has 3 programmable clocks."
3972  static int at91_pm_verify_clocks(void)
3973  {
3974         unsigned long scsr;
3975 @@ -104,20 +105,15 @@ static int at91_pm_verify_clocks(void)
3976  }
3977
3978  /*
3979 - * Call this from platform driver suspend() to see how deeply to suspend.
3980 + * This is called from clk_must_disable(), to see how deeply to suspend.
3981   * For example, some controllers (like OHCI) need one of the PLL clocks
3982   * in order to act as a wakeup source, and those are not available when
3983   * going into slow clock mode.
3984 - *
3985 - * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
3986 - * the very same problem (but not using at91 main_clk), and it'd be better
3987 - * to add one generic API rather than lots of platform-specific ones.
3988   */
3989  int at91_suspend_entering_slow_clock(void)
3990  {
3991         return (target_state == PM_SUSPEND_MEM);
3992  }
3993 -EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
3994
3995
3996  static void (*slow_clock)(void);
3997 @@ -207,16 +203,23 @@ static struct pm_ops at91_pm_ops ={
3998         .enter          = at91_pm_enter,
3999  };
4000
4001 +#ifdef CONFIG_AT91_SLOW_CLOCK
4002 +extern void at91rm9200_slow_clock(void);
4003 +extern u32 at91rm9200_slow_clock_sz;
4004 +#endif
4005 +
4006  static int __init at91_pm_init(void)
4007  {
4008 -       printk("AT91: Power Management\n");
4009 -
4010 -#ifdef CONFIG_AT91_PM_SLOW_CLOCK
4011 -       /* REVISIT allocations of SRAM should be dynamically managed.
4012 +#ifdef CONFIG_AT91_SLOW_CLOCK
4013 +       /*
4014 +        * REVISIT allocations of SRAM should be dynamically managed.
4015          * FIQ handlers and other components will want SRAM/TCM too...
4016          */
4017 -       slow_clock = (void *) (AT91_VA_BASE_SRAM + (3 * SZ_4K));
4018 +       slow_clock = (void *) (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE + (3 * SZ_4K));
4019         memcpy(slow_clock, at91rm9200_slow_clock, at91rm9200_slow_clock_sz);
4020 +       printk("AT91: Power Management (with slow clock mode)\n");
4021 +#else
4022 +       printk("AT91: Power Management\n");
4023  #endif
4024
4025         /* Disable SDRAM low-power mode.  Cannot be used with self-refresh. */
4026 Index: linux-2.6.21.7/arch/arm/mach-at91/pm_slowclock.S
4027 ===================================================================
4028 --- /dev/null
4029 +++ linux-2.6.21.7/arch/arm/mach-at91/pm_slowclock.S
4030 @@ -0,0 +1,172 @@
4031 +/*
4032 + * arch/arm/mach-at91/pm_slow_clock.S
4033 + *
4034 + *  Copyright (C) 2006 Savin Zlobec
4035 + *
4036 + * This program is free software; you can redistribute it and/or modify
4037 + * it under the terms of the GNU General Public License version 2 as
4038 + * published by the Free Software Foundation.
4039 + *
4040 + */
4041 +
4042 +#include <linux/linkage.h>
4043 +#include <asm/hardware.h>
4044 +#include <asm/arch/at91_pmc.h>
4045 +#include <asm/arch/at91rm9200_mc.h>
4046 +
4047 +#define MCKRDY_TIMEOUT         1000
4048 +#define MOSCRDY_TIMEOUT        1000
4049 +#define PLLALOCK_TIMEOUT       1000
4050 +
4051 +       .macro wait_mckrdy
4052 +       mov     r2, #MCKRDY_TIMEOUT
4053 +1:     sub     r2, r2, #1
4054 +       cmp     r2, #0
4055 +       beq     2f
4056 +       ldr     r3, [r1, #AT91_PMC_SR]
4057 +       tst     r3, #AT91_PMC_MCKRDY
4058 +       beq     1b
4059 +2:
4060 +       .endm
4061 +
4062 +       .macro wait_moscrdy
4063 +       mov     r2, #MOSCRDY_TIMEOUT
4064 +1:     sub     r2, r2, #1
4065 +       cmp     r2, #0
4066 +       beq     2f
4067 +       ldr     r3, [r1, #AT91_PMC_SR]
4068 +       tst     r3, #AT91_PMC_MOSCS
4069 +       beq     1b
4070 +2:
4071 +       .endm
4072 +
4073 +       .macro wait_pllalock
4074 +       mov     r2, #PLLALOCK_TIMEOUT
4075 +1:     sub     r2, r2, #1
4076 +       cmp     r2, #0
4077 +       beq     2f
4078 +       ldr     r3, [r1, #AT91_PMC_SR]
4079 +       tst     r3, #AT91_PMC_LOCKA
4080 +       beq     1b
4081 +2:
4082 +       .endm
4083 +
4084 +       .macro wait_plladis
4085 +       mov     r2, #PLLALOCK_TIMEOUT
4086 +1:     sub     r2, r2, #1
4087 +       cmp     r2, #0
4088 +       beq     2f
4089 +       ldr     r3, [r1, #AT91_PMC_SR]
4090 +       tst     r3, #AT91_PMC_LOCKA
4091 +       bne     1b
4092 +2:
4093 +       .endm
4094 +
4095 +       .text
4096 +
4097 +ENTRY(at91rm9200_slow_clock)
4098 +
4099 +       ldr     r1, .at91_va_base_sys
4100 +
4101 +       /* Put SDRAM in self refresh mode */
4102 +
4103 +       b       1f
4104 +       .align  5
4105 +1:     mcr     p15, 0, r0, c7, c10, 4
4106 +       mov     r2, #1
4107 +       str     r2, [r1, #AT91_SDRAMC_SRR]
4108 +
4109 +       /* Save Master clock setting */
4110 +
4111 +       ldr     r2, [r1, #AT91_PMC_MCKR]
4112 +       str     r2, .saved_mckr
4113 +
4114 +       /*
4115 +        * Set the Master clock source to slow clock
4116 +        *
4117 +        * First set the CSS field, wait for MCKRDY
4118 +        * and than set the PRES and MDIV fields.
4119 +        *
4120 +        * See eratta #2[78] for details.
4121 +        */
4122 +
4123 +       bic     r2, r2, #3
4124 +       str     r2, [r1, #AT91_PMC_MCKR]
4125 +
4126 +       wait_mckrdy
4127 +
4128 +       mov     r2, #0
4129 +       str     r2, [r1, #AT91_PMC_MCKR]
4130 +
4131 +       /* Save PLLA setting and disable it */
4132 +
4133 +       ldr     r2, [r1, #AT91_CKGR_PLLAR]
4134 +       str     r2, .saved_pllar
4135 +
4136 +       mov     r2, #0
4137 +       str     r2, [r1, #AT91_CKGR_PLLAR]
4138 +
4139 +       wait_plladis
4140 +
4141 +       /* Turn off the main oscillator */
4142 +
4143 +       ldr     r2, [r1, #AT91_CKGR_MOR]
4144 +       bic     r2, r2, #AT91_PMC_MOSCEN
4145 +       str     r2, [r1, #AT91_CKGR_MOR]
4146 +
4147 +       /* Wait for interrupt */
4148 +
4149 +       mcr     p15, 0, r0, c7, c0, 4
4150 +
4151 +       /* Turn on the main oscillator */
4152 +
4153 +       ldr     r2, [r1, #AT91_CKGR_MOR]
4154 +       orr     r2, r2, #AT91_PMC_MOSCEN
4155 +       str     r2, [r1, #AT91_CKGR_MOR]
4156 +
4157 +       wait_moscrdy
4158 +
4159 +       /* Restore PLLA setting */
4160 +
4161 +       ldr     r2, .saved_pllar
4162 +       str     r2, [r1, #AT91_CKGR_PLLAR]
4163 +
4164 +       wait_pllalock
4165 +
4166 +       /*
4167 +        * Restore master clock setting
4168 +        *
4169 +        * First set PRES if it was not 0,
4170 +        * than set CSS and MDIV fields.
4171 +        * After every change wait for
4172 +        * MCKRDY.
4173 +        *
4174 +        * See eratta #2[78] for details.
4175 +        */
4176 +
4177 +       ldr     r2, .saved_mckr
4178 +       tst     r2, #0x1C
4179 +       beq     2f
4180 +       and     r2, r2, #0x1C
4181 +       str     r2, [r1, #AT91_PMC_MCKR]
4182 +
4183 +       wait_mckrdy
4184 +
4185 +2:     ldr     r2, .saved_mckr
4186 +       str     r2, [r1, #AT91_PMC_MCKR]
4187 +
4188 +       wait_mckrdy
4189 +
4190 +       mov     pc, lr
4191 +
4192 +.saved_mckr:
4193 +       .word 0
4194 +
4195 +.saved_pllar:
4196 +       .word 0
4197 +
4198 +.at91_va_base_sys:
4199 +       .word AT91_VA_BASE_SYS
4200 +
4201 +ENTRY(at91rm9200_slow_clock_sz)
4202 +       .word .-at91rm9200_slow_clock
4203 Index: linux-2.6.21.7/arch/arm/mach-at91/tclib.c
4204 ===================================================================
4205 --- /dev/null
4206 +++ linux-2.6.21.7/arch/arm/mach-at91/tclib.c
4207 @@ -0,0 +1,17 @@
4208 +#include <linux/clk.h>
4209 +#include <linux/kernel.h>
4210 +#include <linux/module.h>
4211 +
4212 +#include "tclib.h"
4213 +
4214 +static struct atmel_tcblock *blocks;
4215 +static int nblocks;
4216 +
4217 +/*
4218 + * Called from the processor-specific init to register the TC Blocks.
4219 + */
4220 +void __init atmel_tc_init(struct atmel_tcblock *tcblocks, int n)
4221 +{
4222 +       blocks = tcblocks;
4223 +       nblocks = n;
4224 +}
4225 Index: linux-2.6.21.7/arch/arm/mach-at91/tclib.h
4226 ===================================================================
4227 --- /dev/null
4228 +++ linux-2.6.21.7/arch/arm/mach-at91/tclib.h
4229 @@ -0,0 +1,11 @@
4230 +
4231 +#define TC_PER_TCB     3
4232 +
4233 +struct atmel_tcblock {
4234 +       u32             physaddr;
4235 +       void __iomem    *ioaddr;
4236 +       struct clk      *clk[TC_PER_TCB];
4237 +       int             irq[TC_PER_TCB];
4238 +};
4239 +
4240 +extern void __init atmel_tc_init(struct atmel_tcblock *tcblocks, int n);
4241 Index: linux-2.6.21.7/arch/arm/mm/Kconfig
4242 ===================================================================
4243 --- linux-2.6.21.7.orig/arch/arm/mm/Kconfig
4244 +++ linux-2.6.21.7/arch/arm/mm/Kconfig
4245 @@ -171,8 +171,8 @@ config CPU_ARM925T
4246  # ARM926T
4247  config CPU_ARM926T
4248         bool "Support ARM926T processor"
4249 -       depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX
4250 -       default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX
4251 +       depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX
4252 +       default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX
4253         select CPU_32v5
4254         select CPU_ABRT_EV5TJ
4255         select CPU_CACHE_VIVT
4256 Index: linux-2.6.21.7/arch/arm/tools/mach-types
4257 ===================================================================
4258 --- linux-2.6.21.7.orig/arch/arm/tools/mach-types
4259 +++ linux-2.6.21.7/arch/arm/tools/mach-types
4260 @@ -1335,3 +1335,32 @@ at91sam9rlek             MACH_AT91SAM9RLEK       AT91SAM9
4261  comtech_router         MACH_COMTECH_ROUTER     COMTECH_ROUTER          1327
4262  sbc2410x               MACH_SBC2410X           SBC2410X                1328
4263  at4x0bd                        MACH_AT4X0BD            AT4X0BD                 1329
4264 +cbifr                  MACH_CBIFR              CBIFR                   1330
4265 +arcom_quantum          MACH_ARCOM_QUANTUM      ARCOM_QUANTUM           1331
4266 +matrix520              MACH_MATRIX520          MATRIX520               1332
4267 +matrix510              MACH_MATRIX510          MATRIX510               1333
4268 +matrix500              MACH_MATRIX500          MATRIX500               1334
4269 +m501                   MACH_M501               M501                    1335
4270 +aaeon1270              MACH_AAEON1270          AAEON1270               1336
4271 +matrix500ev            MACH_MATRIX500EV        MATRIX500EV             1337
4272 +pac500                 MACH_PAC500             PAC500                  1338
4273 +pnx8181                        MACH_PNX8181            PNX8181                 1339
4274 +colibri320             MACH_COLIBRI320         COLIBRI320              1340
4275 +aztoolbb               MACH_AZTOOLBB           AZTOOLBB                1341
4276 +aztoolg2               MACH_AZTOOLG2           AZTOOLG2                1342
4277 +dvlhost                        MACH_DVLHOST            DVLHOST                 1343
4278 +zir9200                        MACH_ZIR9200            ZIR9200                 1344
4279 +zir9260                        MACH_ZIR9260            ZIR9260                 1345
4280 +cocopah                        MACH_COCOPAH            COCOPAH                 1346
4281 +nds                    MACH_NDS                NDS                     1347
4282 +rosencrantz            MACH_ROSENCRANTZ        ROSENCRANTZ             1348
4283 +fttx_odsc              MACH_FTTX_ODSC          FTTX_ODSC               1349
4284 +classe_r6904           MACH_CLASSE_R6904       CLASSE_R6904            1350
4285 +cam60                  MACH_CAM60              CAM60                   1351
4286 +mxc30031ads            MACH_MXC30031ADS        MXC30031ADS             1352
4287 +datacall               MACH_DATACALL           DATACALL                1353
4288 +at91eb01               MACH_AT91EB01           AT91EB01                1354
4289 +rty                    MACH_RTY                RTY                     1355
4290 +dwl2100                        MACH_DWL2100            DWL2100                 1356
4291 +vinsi                  MACH_VINSI              VINSI                   1357
4292 +db88f5281              MACH_DB88F5281          DB88F5281               1358
4293 Index: linux-2.6.21.7/drivers/char/Kconfig
4294 ===================================================================
4295 --- linux-2.6.21.7.orig/drivers/char/Kconfig
4296 +++ linux-2.6.21.7/drivers/char/Kconfig
4297 @@ -1071,5 +1071,21 @@ config TELCLOCK
4298           /sys/devices/platform/telco_clock, with a number of files for
4299           controlling the behavior of this hardware.
4300
4301 +config AT91_SPI
4302 +       bool "SPI driver (legacy) for AT91RM9200 processors"
4303 +       depends on ARCH_AT91RM9200
4304 +       default y
4305 +       help
4306 +         The SPI driver gives access to this serial bus on the AT91RM9200
4307 +         processor.
4308 +
4309 +config AT91_SPIDEV
4310 +       bool "SPI device interface (legacy) for AT91RM9200 processors"
4311 +       depends on ARCH_AT91RM9200 && AT91_SPI
4312 +       default n
4313 +       help
4314 +         The SPI driver gives user mode access to this serial
4315 +         bus on the AT91RM9200 processor.
4316 +
4317  endmenu
4318
4319 Index: linux-2.6.21.7/drivers/char/Makefile
4320 ===================================================================
4321 --- linux-2.6.21.7.orig/drivers/char/Makefile
4322 +++ linux-2.6.21.7/drivers/char/Makefile
4323 @@ -93,6 +93,8 @@ obj-$(CONFIG_CS5535_GPIO)     += cs5535_gpio
4324  obj-$(CONFIG_GPIO_VR41XX)      += vr41xx_giu.o
4325  obj-$(CONFIG_TANBAC_TB0219)    += tb0219.o
4326  obj-$(CONFIG_TELCLOCK)         += tlclk.o
4327 +obj-$(CONFIG_AT91_SPI)         += at91_spi.o
4328 +obj-$(CONFIG_AT91_SPIDEV)      += at91_spidev.o
4329
4330  obj-$(CONFIG_WATCHDOG)         += watchdog/
4331  obj-$(CONFIG_MWAVE)            += mwave/
4332 Index: linux-2.6.21.7/drivers/char/at91_spi.c
4333 ===================================================================
4334 --- /dev/null
4335 +++ linux-2.6.21.7/drivers/char/at91_spi.c
4336 @@ -0,0 +1,336 @@
4337 +/*
4338 + * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 (Thunder)
4339 + *
4340 + *  Copyright (C) SAN People (Pty) Ltd
4341 + *
4342 + * This program is free software; you can redistribute it and/or
4343 + * modify it under the terms of the GNU General Public License
4344 + * as published by the Free Software Foundation; either version
4345 + * 2 of the License, or (at your option) any later version.
4346 + */
4347 +
4348 +#include <linux/init.h>
4349 +#include <linux/dma-mapping.h>
4350 +#include <linux/module.h>
4351 +#include <linux/sched.h>
4352 +#include <linux/completion.h>
4353 +#include <linux/interrupt.h>
4354 +#include <linux/clk.h>
4355 +#include <linux/platform_device.h>
4356 +#include <linux/atmel_pdc.h>
4357 +#include <asm/io.h>
4358 +#include <asm/semaphore.h>
4359 +
4360 +#include <asm/arch/at91_spi.h>
4361 +#include <asm/arch/board.h>
4362 +#include <asm/arch/spi.h>
4363 +
4364 +#undef DEBUG_SPI
4365 +
4366 +static struct spi_local spi_dev[NR_SPI_DEVICES];       /* state of the SPI devices */
4367 +static int spi_enabled = 0;
4368 +static struct semaphore spi_lock;                      /* protect access to SPI bus */
4369 +static int current_device = -1;                                /* currently selected SPI device */
4370 +static struct clk *spi_clk;                            /* SPI clock */
4371 +static void __iomem *spi_base;                         /* SPI peripheral base-address */
4372 +
4373 +DECLARE_COMPLETION(transfer_complete);
4374 +
4375 +
4376 +#define at91_spi_read(reg)             __raw_readl(spi_base + (reg))
4377 +#define at91_spi_write(reg, val)       __raw_writel((val), spi_base + (reg))
4378 +
4379 +
4380 +/* ......................................................................... */
4381 +
4382 +/*
4383 + * Access and enable the SPI bus.
4384 + * This MUST be called before any transfers are performed.
4385 + */
4386 +void spi_access_bus(short device)
4387 +{
4388 +       /* Ensure that requested device is valid */
4389 +       if ((device < 0) || (device >= NR_SPI_DEVICES))
4390 +               panic("at91_spi: spi_access_bus called with invalid device");
4391 +
4392 +       if (spi_enabled == 0) {
4393 +               clk_enable(spi_clk);                            /* Enable Peripheral clock */
4394 +               at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN);    /* Enable SPI */
4395 +#ifdef DEBUG_SPI
4396 +               printk("SPI on\n");
4397 +#endif
4398 +       }
4399 +       spi_enabled++;
4400 +
4401 +       /* Lock the SPI bus */
4402 +       down(&spi_lock);
4403 +       current_device = device;
4404 +
4405 +       /* Configure SPI bus for device */
4406 +       at91_spi_write(AT91_SPI_MR, AT91_SPI_MSTR | AT91_SPI_MODFDIS | (spi_dev[device].pcs << 16));
4407 +}
4408 +
4409 +/*
4410 + * Relinquish control of the SPI bus.
4411 + */
4412 +void spi_release_bus(short device)
4413 +{
4414 +       if (device != current_device)
4415 +               panic("at91_spi: spi_release called with invalid device");
4416 +
4417 +       /* Release the SPI bus */
4418 +       current_device = -1;
4419 +       up(&spi_lock);
4420 +
4421 +       spi_enabled--;
4422 +       if (spi_enabled == 0) {
4423 +               at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS);   /* Disable SPI */
4424 +               clk_disable(spi_clk);                           /* Disable Peripheral clock */
4425 +#ifdef DEBUG_SPI
4426 +               printk("SPI off\n");
4427 +#endif
4428 +       }
4429 +}
4430 +
4431 +/*
4432 + * Perform a data transfer over the SPI bus
4433 + */
4434 +int spi_transfer(struct spi_transfer_list* list)
4435 +{
4436 +       struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
4437 +       int tx_size;
4438 +
4439 +       if (!list)
4440 +               panic("at91_spi: spi_transfer called with NULL transfer list");
4441 +       if (current_device == -1)
4442 +               panic("at91_spi: spi_transfer called without acquiring bus");
4443 +
4444 +#ifdef DEBUG_SPI
4445 +       printk("SPI transfer start [%i]\n", list->nr_transfers);
4446 +#endif
4447 +
4448 +       /* If we are in 16-bit mode, we need to modify what we pass to the PDC */
4449 +       tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1;
4450 +
4451 +       /* Store transfer list */
4452 +       device->xfers = list;
4453 +       list->curr = 0;
4454 +
4455 +       /* Assume there must be at least one transfer */
4456 +       device->tx = dma_map_single(NULL, list->tx[0], list->txlen[0], DMA_TO_DEVICE);
4457 +       device->rx = dma_map_single(NULL, list->rx[0], list->rxlen[0], DMA_FROM_DEVICE);
4458 +
4459 +       /* Program PDC registers */
4460 +       at91_spi_write(ATMEL_PDC_TPR, device->tx);
4461 +       at91_spi_write(ATMEL_PDC_RPR, device->rx);
4462 +       at91_spi_write(ATMEL_PDC_TCR, list->txlen[0] / tx_size);
4463 +       at91_spi_write(ATMEL_PDC_RCR, list->rxlen[0] / tx_size);
4464 +
4465 +       /* Is there a second transfer? */
4466 +       if (list->nr_transfers > 1) {
4467 +               device->txnext = dma_map_single(NULL, list->tx[1], list->txlen[1], DMA_TO_DEVICE);
4468 +               device->rxnext = dma_map_single(NULL, list->rx[1], list->rxlen[1], DMA_FROM_DEVICE);
4469 +
4470 +               /* Program Next PDC registers */
4471 +               at91_spi_write(ATMEL_PDC_TNPR, device->txnext);
4472 +               at91_spi_write(ATMEL_PDC_RNPR, device->rxnext);
4473 +               at91_spi_write(ATMEL_PDC_TNCR, list->txlen[1] / tx_size);
4474 +               at91_spi_write(ATMEL_PDC_RNCR, list->rxlen[1] / tx_size);
4475 +       }
4476 +       else {
4477 +               device->txnext = 0;
4478 +               device->rxnext = 0;
4479 +               at91_spi_write(ATMEL_PDC_TNCR, 0);
4480 +               at91_spi_write(ATMEL_PDC_RNCR, 0);
4481 +       }
4482 +
4483 +       // TODO: If we are doing consecutive transfers (at high speed, or
4484 +       //   small buffers), then it might be worth modifying the 'Delay between
4485 +       //   Consecutive Transfers' in the CSR registers.
4486 +       //   This is an issue if we cannot chain the next buffer fast enough
4487 +       //   in the interrupt handler.
4488 +
4489 +       /* Enable transmitter and receiver */
4490 +       at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN | ATMEL_PDC_TXTEN);
4491 +
4492 +       at91_spi_write(AT91_SPI_IER, AT91_SPI_ENDRX);           /* enable buffer complete interrupt */
4493 +       wait_for_completion(&transfer_complete);
4494 +
4495 +#ifdef DEBUG_SPI
4496 +       printk("SPI transfer end\n");
4497 +#endif
4498 +
4499 +       return 0;
4500 +}
4501 +
4502 +/* ......................................................................... */
4503 +
4504 +/*
4505 + * Handle interrupts from the SPI controller.
4506 + */
4507 +static irqreturn_t at91spi_interrupt(int irq, void *dev_id)
4508 +{
4509 +       unsigned int status;
4510 +       struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
4511 +       struct spi_transfer_list *list = device->xfers;
4512 +
4513 +#ifdef DEBUG_SPI
4514 +       printk("SPI interrupt %i\n", current_device);
4515 +#endif
4516 +
4517 +       if (!list)
4518 +               panic("at91_spi: spi_interrupt with a NULL transfer list");
4519 +
4520 +               status = at91_spi_read(AT91_SPI_SR) & at91_spi_read(AT91_SPI_IMR);      /* read status */
4521 +
4522 +       dma_unmap_single(NULL, device->tx, list->txlen[list->curr], DMA_TO_DEVICE);
4523 +       dma_unmap_single(NULL, device->rx, list->rxlen[list->curr], DMA_FROM_DEVICE);
4524 +
4525 +       device->tx = device->txnext;    /* move next transfer to current transfer */
4526 +       device->rx = device->rxnext;
4527 +
4528 +       list->curr = list->curr + 1;
4529 +       if (list->curr == list->nr_transfers) {         /* all transfers complete */
4530 +               at91_spi_write(AT91_SPI_IDR, AT91_SPI_ENDRX);           /* disable interrupt */
4531 +
4532 +               /* Disable transmitter and receiver */
4533 +               at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
4534 +
4535 +               device->xfers = NULL;
4536 +               complete(&transfer_complete);
4537 +       }
4538 +       else if (list->curr+1 == list->nr_transfers) {  /* no more next transfers */
4539 +               device->txnext = 0;
4540 +               device->rxnext = 0;
4541 +               at91_spi_write(ATMEL_PDC_TNCR, 0);
4542 +               at91_spi_write(ATMEL_PDC_RNCR, 0);
4543 +       }
4544 +       else {
4545 +               int i = (list->curr)+1;
4546 +
4547 +               /* If we are in 16-bit mode, we need to modify what we pass to the PDC */
4548 +               int tx_size = (at91_spi_read(AT91_SPI_CSR(current_device)) & AT91_SPI_BITS_16) ? 2 : 1;
4549 +
4550 +               device->txnext = dma_map_single(NULL, list->tx[i], list->txlen[i], DMA_TO_DEVICE);
4551 +               device->rxnext = dma_map_single(NULL, list->rx[i], list->rxlen[i], DMA_FROM_DEVICE);
4552 +               at91_spi_write(ATMEL_PDC_TNPR, device->txnext);
4553 +               at91_spi_write(ATMEL_PDC_RNPR, device->rxnext);
4554 +               at91_spi_write(ATMEL_PDC_TNCR, list->txlen[i] / tx_size);
4555 +               at91_spi_write(ATMEL_PDC_RNCR, list->rxlen[i] / tx_size);
4556 +       }
4557 +       return IRQ_HANDLED;
4558 +}
4559 +
4560 +/* ......................................................................... */
4561 +
4562 +/*
4563 + * Initialize the SPI controller
4564 + */
4565 +static int __init at91spi_probe(struct platform_device *pdev)
4566 +{
4567 +       int i;
4568 +       unsigned long scbr;
4569 +       struct resource *res;
4570 +
4571 +       init_MUTEX(&spi_lock);
4572 +
4573 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4574 +       if (!res)
4575 +               return -ENXIO;
4576 +
4577 +       if (!request_mem_region(res->start, res->end - res->start + 1, "at91_spi"))
4578 +               return -EBUSY;
4579 +
4580 +       spi_base = ioremap(res->start, res->end - res->start + 1);
4581 +       if (!spi_base) {
4582 +               release_mem_region(res->start, res->end - res->start + 1);
4583 +               return -ENOMEM;
4584 +       }
4585 +
4586 +       spi_clk = clk_get(NULL, "spi_clk");
4587 +       if (IS_ERR(spi_clk)) {
4588 +               printk(KERN_ERR "at91_spi: no clock defined\n");
4589 +               iounmap(spi_base);
4590 +               release_mem_region(res->start, res->end - res->start + 1);
4591 +               return -ENODEV;
4592 +       }
4593 +
4594 +       at91_spi_write(AT91_SPI_CR, AT91_SPI_SWRST);    /* software reset of SPI controller */
4595 +
4596 +       /*
4597 +        * Calculate the correct SPI baud-rate divisor.
4598 +        */
4599 +       scbr = clk_get_rate(spi_clk) / (2 * DEFAULT_SPI_CLK);
4600 +       scbr = scbr + 1;                /* round up */
4601 +
4602 +       printk(KERN_INFO "at91_spi: Baud rate set to %ld\n", clk_get_rate(spi_clk) / (2 * scbr));
4603 +
4604 +       /* Set Chip Select registers to good defaults */
4605 +       for (i = 0; i < 4; i++) {
4606 +               at91_spi_write(AT91_SPI_CSR(i), AT91_SPI_CPOL | AT91_SPI_BITS_8 | (16 << 16) | (scbr << 8));
4607 +       }
4608 +
4609 +       at91_spi_write(ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
4610 +
4611 +       memset(&spi_dev, 0, sizeof(spi_dev));
4612 +       spi_dev[0].pcs = 0xE;
4613 +       spi_dev[1].pcs = 0xD;
4614 +       spi_dev[2].pcs = 0xB;
4615 +       spi_dev[3].pcs = 0x7;
4616 +
4617 +       if (request_irq(AT91RM9200_ID_SPI, at91spi_interrupt, 0, "spi", NULL)) {
4618 +               clk_put(spi_clk);
4619 +               iounmap(spi_base);
4620 +               release_mem_region(res->start, res->end - res->start + 1);
4621 +               return -EBUSY;
4622 +       }
4623 +
4624 +       at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIEN);            /* Enable SPI */
4625 +
4626 +       return 0;
4627 +}
4628 +
4629 +static int __devexit at91spi_remove(struct platform_device *pdev)
4630 +{
4631 +       struct resource *res;
4632 +
4633 +       at91_spi_write(AT91_SPI_CR, AT91_SPI_SPIDIS);           /* Disable SPI */
4634 +       clk_put(spi_clk);
4635 +
4636 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4637 +       iounmap(spi_base);
4638 +       release_mem_region(res->start, res->end - res->start + 1);
4639 +
4640 +       free_irq(AT91RM9200_ID_SPI, 0);
4641 +       return 0;
4642 +}
4643 +
4644 +static struct platform_driver at91spi_driver = {
4645 +       .probe          = at91spi_probe,
4646 +       .remove         = __devexit_p(at91spi_remove),
4647 +       .driver         = {
4648 +               .name   = "at91_spi",
4649 +               .owner  = THIS_MODULE,
4650 +       },
4651 +};
4652 +
4653 +static int __init at91spi_init(void)
4654 +{
4655 +       return platform_driver_register(&at91spi_driver);
4656 +}
4657 +
4658 +static void __exit at91spi_exit(void)
4659 +{
4660 +       platform_driver_unregister(&at91spi_driver);
4661 +}
4662 +
4663 +EXPORT_SYMBOL(spi_access_bus);
4664 +EXPORT_SYMBOL(spi_release_bus);
4665 +EXPORT_SYMBOL(spi_transfer);
4666 +
4667 +module_init(at91spi_init);
4668 +module_exit(at91spi_exit);
4669 +
4670 +MODULE_LICENSE("GPL")
4671 +MODULE_AUTHOR("Andrew Victor")
4672 +MODULE_DESCRIPTION("SPI driver for Atmel AT91RM9200")
4673 Index: linux-2.6.21.7/drivers/char/at91_spidev.c
4674 ===================================================================
4675 --- /dev/null
4676 +++ linux-2.6.21.7/drivers/char/at91_spidev.c
4677 @@ -0,0 +1,236 @@
4678 +/*
4679 + * User-space interface to the SPI bus on Atmel AT91RM9200
4680 + *
4681 + *  Copyright (C) 2003 SAN People (Pty) Ltd
4682 + *
4683 + * Based on SPI driver by Rick Bronson
4684 + *
4685 + * This program is free software; you can redistribute it and/or
4686 + * modify it under the terms of the GNU General Public License
4687 + * as published by the Free Software Foundation; either version
4688 + * 2 of the License, or (at your option) any later version.
4689 + */
4690 +
4691 +#include <linux/module.h>
4692 +#include <linux/init.h>
4693 +#include <linux/slab.h>
4694 +#include <linux/highmem.h>
4695 +#include <linux/pagemap.h>
4696 +#include <asm/arch/spi.h>
4697 +
4698 +#ifdef CONFIG_DEVFS_FS
4699 +#include <linux/devfs_fs_kernel.h>
4700 +#endif
4701 +
4702 +
4703 +#undef DEBUG_SPIDEV
4704 +
4705 +/* ......................................................................... */
4706 +
4707 +/*
4708 + * Read or Write to SPI bus.
4709 + */
4710 +static ssize_t spidev_rd_wr(struct file *file, char *buf, size_t count, loff_t *offset)
4711 +{
4712 +       unsigned int spi_device = (unsigned int) file->private_data;
4713 +
4714 +       struct mm_struct * mm;
4715 +       struct page ** maplist;
4716 +       struct spi_transfer_list* list;
4717 +       int    pgcount;
4718 +
4719 +       unsigned int ofs, pagelen;
4720 +       int res, i, err;
4721 +
4722 +       if (!count) {
4723 +               return 0;
4724 +       }
4725 +
4726 +       list = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
4727 +       if (!list) {
4728 +               return -ENOMEM;
4729 +       }
4730 +
4731 +       mm = current->mm;
4732 +
4733 +       pgcount = ((unsigned long)buf+count+PAGE_SIZE-1)/PAGE_SIZE - (unsigned long)buf/PAGE_SIZE;
4734 +
4735 +       if (pgcount >= MAX_SPI_TRANSFERS) {
4736 +               kfree(list);
4737 +               return -EFBIG;
4738 +       }
4739 +
4740 +       maplist = kmalloc (pgcount * sizeof (struct page *), GFP_KERNEL);
4741 +
4742 +       if (!maplist) {
4743 +               kfree(list);
4744 +               return -ENOMEM;
4745 +       }
4746 +       flush_cache_all();
4747 +       down_read(&mm->mmap_sem);
4748 +       err= get_user_pages(current, mm, (unsigned long)buf, pgcount, 1, 0, maplist, NULL);
4749 +       up_read(&mm->mmap_sem);
4750 +
4751 +       if (err < 0) {
4752 +               kfree(list);
4753 +               kfree(maplist);
4754 +               return err;
4755 +       }
4756 +       pgcount = err;
4757 +
4758 +#ifdef DEBUG_SPIDEV
4759 +       printk("spidev_rd_rw: %i %i\n", count, pgcount);
4760 +#endif
4761 +
4762 +       /* Set default return value = transfer length */
4763 +       res = count;
4764 +
4765 +       /*
4766 +        * At this point, the virtual area buf[0] .. buf[count-1] will have
4767 +        * corresponding pages mapped in the physical memory and locked until
4768 +        * we unmap the kiobuf.  The pages cannot be swapped out or moved
4769 +        * around.
4770 +        */
4771 +       ofs = (unsigned long) buf & (PAGE_SIZE -1);
4772 +       pagelen = PAGE_SIZE - ofs;
4773 +       if (count < pagelen)
4774 +               pagelen = count;
4775 +
4776 +       for (i = 0; i < pgcount; i++) {
4777 +               flush_dcache_page(maplist[i]);
4778 +
4779 +               list->tx[i] = list->rx[i] = page_address(maplist[i]) + ofs;
4780 +               list->txlen[i] = list->rxlen[i] = pagelen;
4781 +
4782 +#ifdef DEBUG_SPIDEV
4783 +               printk("  %i: %x  (%i)\n", i, list->tx[i], list->txlen[i]);
4784 +#endif
4785 +
4786 +               ofs = 0;        /* all subsequent transfers start at beginning of a page */
4787 +               count = count - pagelen;
4788 +               pagelen = (count < PAGE_SIZE) ? count : PAGE_SIZE;
4789 +       }
4790 +       list->nr_transfers = pgcount;
4791 +
4792 +       /* Perform transfer on SPI bus */
4793 +       spi_access_bus(spi_device);
4794 +       spi_transfer(list);
4795 +       spi_release_bus(spi_device);
4796 +
4797 +       while (pgcount--) {
4798 +               page_cache_release (maplist[pgcount]);
4799 +       }
4800 +       flush_cache_all();
4801 +
4802 +       kfree(maplist);
4803 +       kfree(list);
4804 +
4805 +       return res;
4806 +}
4807 +
4808 +static int spidev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
4809 +{
4810 +       int spi_device = MINOR(inode->i_rdev);
4811 +
4812 +       if (spi_device >= NR_SPI_DEVICES)
4813 +               return -ENODEV;
4814 +
4815 +       // TODO: This interface can be used to configure the SPI bus.
4816 +       // Configurable options could include: Speed, Clock Polarity, Clock Phase
4817 +
4818 +       switch(cmd) {
4819 +               default:
4820 +                       return -ENOIOCTLCMD;
4821 +       }
4822 +}
4823 +
4824 +/*
4825 + * Open the SPI device
4826 + */
4827 +static int spidev_open(struct inode *inode, struct file *file)
4828 +{
4829 +       unsigned int spi_device = MINOR(inode->i_rdev);
4830 +
4831 +       if (spi_device >= NR_SPI_DEVICES)
4832 +               return -ENODEV;
4833 +
4834 +       /*
4835 +        * 'private_data' is actually a pointer, but we overload it with the
4836 +        * value we want to store.
4837 +        */
4838 +       file->private_data = (void *)spi_device;
4839 +
4840 +       return 0;
4841 +}
4842 +
4843 +/*
4844 + * Close the SPI device
4845 + */
4846 +static int spidev_close(struct inode *inode, struct file *file)
4847 +{
4848 +       return 0;
4849 +}
4850 +
4851 +/* ......................................................................... */
4852 +
4853 +static struct file_operations spidev_fops = {
4854 +       .owner          = THIS_MODULE,
4855 +       .llseek         = no_llseek,
4856 +       .read           = spidev_rd_wr,
4857 +       .write          = (int (*) (struct file *file, const char *buf, size_t count, loff_t *offset))spidev_rd_wr,
4858 +       .ioctl          = spidev_ioctl,
4859 +       .open           = spidev_open,
4860 +       .release        = spidev_close,
4861 +};
4862 +
4863 +/*
4864 + * Install the SPI /dev interface driver
4865 + */
4866 +static int __init at91_spidev_init(void)
4867 +{
4868 +#ifdef CONFIG_DEVFS_FS
4869 +       int i;
4870 +#endif
4871 +
4872 +       if (register_chrdev(SPI_MAJOR, "spi", &spidev_fops)) {
4873 +               printk(KERN_ERR "at91_spidev: Unable to get major %d for SPI bus\n", SPI_MAJOR);
4874 +               return -EIO;
4875 +       }
4876 +
4877 +#ifdef CONFIG_DEVFS_FS
4878 +       devfs_mk_dir("spi");
4879 +       for (i = 0; i < NR_SPI_DEVICES; i++) {
4880 +               devfs_mk_cdev(MKDEV(SPI_MAJOR, i), S_IFCHR | S_IRUSR | S_IWUSR, "spi/%d",i);
4881 +       }
4882 +#endif
4883 +       printk(KERN_INFO "AT91 SPI driver loaded\n");
4884 +
4885 +       return 0;
4886 +}
4887 +
4888 +/*
4889 + * Remove the SPI /dev interface driver
4890 + */
4891 +static void __exit at91_spidev_exit(void)
4892 +{
4893 +#ifdef CONFIG_DEVFS_FS
4894 +       int i;
4895 +       for (i = 0; i < NR_SPI_DEVICES; i++) {
4896 +               devfs_remove("spi/%d", i);
4897 +       }
4898 +
4899 +       devfs_remove("spi");
4900 +#endif
4901 +
4902 +       if (unregister_chrdev(SPI_MAJOR, "spi")) {
4903 +               printk(KERN_ERR "at91_spidev: Unable to release major %d for SPI bus\n", SPI_MAJOR);
4904 +               return;
4905 +       }
4906 +}
4907 +
4908 +module_init(at91_spidev_init);
4909 +module_exit(at91_spidev_exit);
4910 +
4911 +MODULE_LICENSE("GPL")
4912 +MODULE_AUTHOR("Andrew Victor")
4913 +MODULE_DESCRIPTION("SPI /dev interface for Atmel AT91RM9200")
4914 Index: linux-2.6.21.7/drivers/i2c/busses/Kconfig
4915 ===================================================================
4916 --- linux-2.6.21.7.orig/drivers/i2c/busses/Kconfig
4917 +++ linux-2.6.21.7/drivers/i2c/busses/Kconfig
4918 @@ -81,6 +81,14 @@ config I2C_AT91
4919           This supports the use of the I2C interface on Atmel AT91
4920           processors.
4921
4922 +config I2C_AT91_CLOCKRATE
4923 +       prompt "Atmel AT91 I2C/TWI clock-rate"
4924 +       depends on I2C_AT91
4925 +       int
4926 +       default 100000
4927 +       help
4928 +         Set the AT91 I2C/TWI clock-rate.
4929 +
4930  config I2C_AU1550
4931         tristate "Au1550/Au1200 SMBus interface"
4932         depends on I2C && (SOC_AU1550 || SOC_AU1200)
4933 @@ -545,6 +553,14 @@ config I2C_VOODOO3
4934           This driver can also be built as a module.  If so, the module
4935           will be called i2c-voodoo3.
4936
4937 +config I2C_PCA
4938 +       tristate "PCA9564"
4939 +       depends on I2C
4940 +       select I2C_ALGOPCA
4941 +       help
4942 +         This driver support the Philips PCA 9564 Parallel bus to I2C
4943 +         bus controller.
4944 +
4945  config I2C_PCA_ISA
4946         tristate "PCA9564 on an ISA bus"
4947         depends on I2C
4948 Index: linux-2.6.21.7/drivers/i2c/busses/Makefile
4949 ===================================================================
4950 --- linux-2.6.21.7.orig/drivers/i2c/busses/Makefile
4951 +++ linux-2.6.21.7/drivers/i2c/busses/Makefile
4952 @@ -28,6 +28,7 @@ obj-$(CONFIG_I2C_OMAP)                += i2c-omap.o
4953  obj-$(CONFIG_I2C_PARPORT)      += i2c-parport.o
4954  obj-$(CONFIG_I2C_PARPORT_LIGHT)        += i2c-parport-light.o
4955  obj-$(CONFIG_I2C_PASEMI)       += i2c-pasemi.o
4956 +obj-$(CONFIG_I2C_PCA)          += i2c-pca.o
4957  obj-$(CONFIG_I2C_PCA_ISA)      += i2c-pca-isa.o
4958  obj-$(CONFIG_I2C_PIIX4)                += i2c-piix4.o
4959  obj-$(CONFIG_I2C_PNX)          += i2c-pnx.o
4960 Index: linux-2.6.21.7/drivers/i2c/busses/i2c-at91.c
4961 ===================================================================
4962 --- linux-2.6.21.7.orig/drivers/i2c/busses/i2c-at91.c
4963 +++ linux-2.6.21.7/drivers/i2c/busses/i2c-at91.c
4964 @@ -31,8 +31,11 @@
4965  #include <asm/arch/board.h>
4966  #include <asm/arch/cpu.h>
4967
4968 -#define TWI_CLOCK              100000          /* Hz. max 400 Kbits/sec */
4969
4970 +/* Clockrate is configurable - max 400 Kbits/sec */
4971 +static unsigned int clockrate = CONFIG_I2C_AT91_CLOCKRATE;
4972 +module_param(clockrate, uint, 0);
4973 +MODULE_PARM_DESC(clockrate, "The TWI clockrate");
4974
4975  static struct clk *twi_clk;
4976  static void __iomem *twi_base;
4977 @@ -53,7 +56,7 @@ static void __devinit at91_twi_hwinit(vo
4978         at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN);     /* Set Master mode */
4979
4980         /* Calcuate clock dividers */
4981 -       cdiv = (clk_get_rate(twi_clk) / (2 * TWI_CLOCK)) - 3;
4982 +       cdiv = (clk_get_rate(twi_clk) / (2 * clockrate)) - 3;
4983         cdiv = cdiv + 1;        /* round up */
4984         ckdiv = 0;
4985         while (cdiv > 255) {
4986 @@ -61,11 +64,12 @@ static void __devinit at91_twi_hwinit(vo
4987                 cdiv = cdiv >> 1;
4988         }
4989
4990 -       if (cpu_is_at91rm9200()) {                      /* AT91RM9200 Errata #22 */
4991 -               if (ckdiv > 5) {
4992 -                       printk(KERN_ERR "AT91 I2C: Invalid TWI_CLOCK value!\n");
4993 -                       ckdiv = 5;
4994 -               }
4995 +       if (cpu_is_at91rm9200() && (ckdiv > 5)) {       /* AT91RM9200 Errata #22 */
4996 +               printk(KERN_ERR "AT91 I2C: Invalid TWI clockrate!\n");
4997 +               ckdiv = 5;
4998 +       } else if (ckdiv > 7) {
4999 +               printk(KERN_ERR "AT91 I2C: Invalid TWI clockrate!\n");
5000 +               ckdiv = 7;
5001         }
5002
5003         at91_twi_write(AT91_TWI_CWGR, (ckdiv << 16) | (cdiv << 8) | cdiv);
5004 Index: linux-2.6.21.7/drivers/i2c/busses/i2c-pca.c
5005 ===================================================================
5006 --- /dev/null
5007 +++ linux-2.6.21.7/drivers/i2c/busses/i2c-pca.c
5008 @@ -0,0 +1,213 @@
5009 +/*
5010 + *  Platform driver for PCA9564 I2C bus controller.
5011 + *
5012 + *  (C) 2006 Andrew Victor
5013 + *
5014 + *  Based on i2c-pca-isa.c driver for PCA9564 on ISA boards
5015 + *    Copyright (C) 2004 Arcom Control Systems
5016 + *
5017 + *  This program is free software; you can redistribute it and/or modify
5018 + *  it under the terms of the GNU General Public License as published by
5019 + *  the Free Software Foundation; either version 2 of the License, or
5020 + *  (at your option) any later version.
5021 + *
5022 + *  This program is distributed in the hope that it will be useful,
5023 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
5024 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5025 + *  GNU General Public License for more details.
5026 + *
5027 + *  You should have received a copy of the GNU General Public License
5028 + *  along with this program; if not, write to the Free Software
5029 + *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
5030 + */
5031 +
5032 +#include <linux/kernel.h>
5033 +#include <linux/module.h>
5034 +#include <linux/moduleparam.h>
5035 +#include <linux/delay.h>
5036 +#include <linux/init.h>
5037 +#include <linux/interrupt.h>
5038 +#include <linux/wait.h>
5039 +#include <linux/platform_device.h>
5040 +
5041 +#include <linux/i2c.h>
5042 +#include <linux/i2c-algo-pca.h>
5043 +
5044 +#include <asm/io.h>
5045 +
5046 +#include "../algos/i2c-algo-pca.h"
5047 +
5048 +#define PCA_OWN_ADDRESS                0x55    /* our address for slave mode */
5049 +#define PCA_CLOCK              I2C_PCA_CON_59kHz
5050 +
5051 +//#define REG_SHIFT            2
5052 +#define REG_SHIFT              0
5053 +
5054 +//#define DEBUG_IO
5055 +
5056 +#define PCA_IO_SIZE 4
5057 +
5058 +static void __iomem *base_addr;
5059 +static int irq;
5060 +static wait_queue_head_t pca_wait;
5061 +
5062 +static int pca_getown(struct i2c_algo_pca_data *adap)
5063 +{
5064 +       return PCA_OWN_ADDRESS;
5065 +}
5066 +
5067 +static int pca_getclock(struct i2c_algo_pca_data *adap)
5068 +{
5069 +       return PCA_CLOCK;
5070 +}
5071 +
5072 +static void pca_writebyte(struct i2c_algo_pca_data *adap, int reg, int val)
5073 +{
5074 +#ifdef DEBUG_IO
5075 +       static char *names[] = { "T/O", "DAT", "ADR", "CON" };
5076 +       printk("*** write %s at %#lx <= %#04x\n", names[reg], (unsigned long) base_addr+reg, val);
5077 +#endif
5078 +       udelay(1);
5079 +       outb(val, base_addr + (reg << REG_SHIFT));
5080 +}
5081 +
5082 +static int pca_readbyte(struct i2c_algo_pca_data *adap, int reg)
5083 +{
5084 +       int res;
5085 +
5086 +       udelay(1);
5087 +       res = inb(base_addr + (reg << REG_SHIFT));
5088 +#ifdef DEBUG_IO
5089 +       {
5090 +               static char *names[] = { "STA", "DAT", "ADR", "CON" };
5091 +               printk("*** read  %s => %#04x\n", names[reg], res);
5092 +       }
5093 +#endif
5094 +       return res;
5095 +}
5096 +
5097 +static int pca_waitforinterrupt(struct i2c_algo_pca_data *adap)
5098 +{
5099 +       int ret = 0;
5100 +
5101 +       if (irq > -1) {
5102 +               ret = wait_event_interruptible(pca_wait,
5103 +                               pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI);
5104 +       } else {
5105 +               while ((pca_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0)
5106 +                       udelay(100);
5107 +       }
5108 +       return ret;
5109 +}
5110 +
5111 +static irqreturn_t pca_handler(int this_irq, void *dev_id)
5112 +{
5113 +       wake_up_interruptible(&pca_wait);
5114 +       return IRQ_HANDLED;
5115 +}
5116 +
5117 +static struct i2c_algo_pca_data pca_i2c_data = {
5118 +       .get_own                = pca_getown,
5119 +       .get_clock              = pca_getclock,
5120 +       .write_byte             = pca_writebyte,
5121 +       .read_byte              = pca_readbyte,
5122 +       .wait_for_interrupt     = pca_waitforinterrupt,
5123 +};
5124 +
5125 +static struct i2c_adapter pca_i2c_ops = {
5126 +       .owner          = THIS_MODULE,
5127 +       .id             = I2C_HW_A_PLAT,
5128 +       .algo_data      = &pca_i2c_data,
5129 +       .name           = "PCA9564",
5130 +       .class          = I2C_CLASS_HWMON,
5131 +};
5132 +
5133 +static int __devinit pca_i2c_probe(struct platform_device *pdev)
5134 +{
5135 +       struct resource *res;
5136 +
5137 +       init_waitqueue_head(&pca_wait);
5138 +
5139 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5140 +       if (!res)
5141 +               return -ENODEV;
5142 +
5143 +       if (!request_mem_region(res->start, PCA_IO_SIZE, "PCA9564"))
5144 +               return -ENXIO;
5145 +
5146 +       base_addr = ioremap(res->start, PCA_IO_SIZE);
5147 +       if (base_addr == NULL)
5148 +               goto out_region;
5149 +
5150 +       irq = platform_get_irq(pdev, 0);
5151 +       if (irq > -1) {
5152 +               if (request_irq(irq, pca_handler, 0, "pca9564", NULL) < 0) {
5153 +                       printk(KERN_ERR "i2c-pca: Request irq%d failed\n", irq);
5154 +                       goto out_remap;
5155 +               }
5156 +       }
5157 +
5158 +       /* set up the driverfs linkage to our parent device */
5159 +       pca_i2c_ops.dev.parent = &pdev->dev;
5160 +
5161 +       if (i2c_pca_add_bus(&pca_i2c_ops) < 0) {
5162 +               printk(KERN_ERR "i2c-pca: Failed to add i2c bus\n");
5163 +               goto out_irq;
5164 +       }
5165 +
5166 +       return 0;
5167 +
5168 + out_irq:
5169 +       if (irq > -1)
5170 +               free_irq(irq, &pca_i2c_ops);
5171 +
5172 + out_remap:
5173 +       iounmap(base_addr);
5174 +
5175 + out_region:
5176 +       release_mem_region(res->start, PCA_IO_SIZE);
5177 +       return -ENODEV;
5178 +}
5179 +
5180 +static int __devexit pca_i2c_remove(struct platform_device *pdev)
5181 +{
5182 +       struct resource *res;
5183 +
5184 +       i2c_del_adapter(&pca_i2c_ops);
5185 +
5186 +       if (irq > 0)
5187 +               free_irq(irq, NULL);
5188 +
5189 +       iounmap(base_addr);
5190 +
5191 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5192 +       release_mem_region(res->start, PCA_IO_SIZE);
5193 +
5194 +       return 0;
5195 +}
5196 +
5197 +static struct platform_driver pca_i2c_driver = {
5198 +       .probe          = pca_i2c_probe,
5199 +       .remove         = __devexit_p(pca_i2c_remove),
5200 +       .driver         = {
5201 +               .name   = "pca9564",
5202 +               .owner  = THIS_MODULE,
5203 +       },
5204 +};
5205 +
5206 +static int __init pca_i2c_init(void)
5207 +{
5208 +       return platform_driver_register(&pca_i2c_driver);
5209 +}
5210 +
5211 +static void __exit pca_i2c_exit(void)
5212 +{
5213 +       platform_driver_unregister(&pca_i2c_driver);
5214 +}
5215 +
5216 +module_init(pca_i2c_init);
5217 +module_exit(pca_i2c_exit);
5218 +
5219 +MODULE_AUTHOR("Andrew Victor");
5220 +MODULE_DESCRIPTION("PCA9564 platform driver");
5221 +MODULE_LICENSE("GPL");
5222 Index: linux-2.6.21.7/drivers/input/touchscreen/ads7846.c
5223 ===================================================================
5224 --- linux-2.6.21.7.orig/drivers/input/touchscreen/ads7846.c
5225 +++ linux-2.6.21.7/drivers/input/touchscreen/ads7846.c
5226 @@ -39,7 +39,8 @@
5227  /*
5228   * This code has been heavily tested on a Nokia 770, and lightly
5229   * tested on other ads7846 devices (OSK/Mistral, Lubbock).
5230 - * Support for ads7843 and ads7845 has only been stubbed in.
5231 + * Support for ads7843 tested on Atmel at91sam926x-EK.
5232 + * Support for ads7845 has only been stubbed in.
5233   *
5234   * IRQ handling needs a workaround because of a shortcoming in handling
5235   * edge triggered IRQs on some platforms like the OMAP1/2. These
5236 @@ -246,18 +247,16 @@ static int ads7846_read12_ser(struct dev
5237
5238         /* REVISIT:  take a few more samples, and compare ... */
5239
5240 -       /* maybe off internal vREF */
5241 -       if (use_internal) {
5242 -               req->ref_off = REF_OFF;
5243 -               req->xfer[4].tx_buf = &req->ref_off;
5244 -               req->xfer[4].len = 1;
5245 -               spi_message_add_tail(&req->xfer[4], &req->msg);
5246 -
5247 -               req->xfer[5].rx_buf = &req->scratch;
5248 -               req->xfer[5].len = 2;
5249 -               CS_CHANGE(req->xfer[5]);
5250 -               spi_message_add_tail(&req->xfer[5], &req->msg);
5251 -       }
5252 +       /* converter in low power mode & enable PENIRQ */
5253 +       req->ref_off = PWRDOWN;
5254 +       req->xfer[4].tx_buf = &req->ref_off;
5255 +       req->xfer[4].len = 1;
5256 +       spi_message_add_tail(&req->xfer[4], &req->msg);
5257 +
5258 +       req->xfer[5].rx_buf = &req->scratch;
5259 +       req->xfer[5].len = 2;
5260 +       CS_CHANGE(req->xfer[5]);
5261 +       spi_message_add_tail(&req->xfer[5], &req->msg);
5262
5263         ts->irq_disabled = 1;
5264         disable_irq(spi->irq);
5265 @@ -536,6 +535,9 @@ static void ads7846_rx(void *ads)
5266         } else
5267                 Rt = 0;
5268
5269 +       if (ts->model == 7843)
5270 +               Rt = ts->pressure_max / 2;
5271 +
5272         /* Sample found inconsistent by debouncing or pressure is beyond
5273          * the maximum. Don't report it to user space, repeat at least
5274          * once more the measurement
5275 Index: linux-2.6.21.7/drivers/leds/Kconfig
5276 ===================================================================
5277 --- linux-2.6.21.7.orig/drivers/leds/Kconfig
5278 +++ linux-2.6.21.7/drivers/leds/Kconfig
5279 @@ -76,6 +76,13 @@ config LEDS_NET48XX
5280           This option enables support for the Soekris net4801 and net4826 error
5281           LED.
5282
5283 +config LEDS_AT91
5284 +       tristate "LED support using AT91 GPIOs"
5285 +       depends on LEDS_CLASS && ARCH_AT91 && !LEDS
5286 +       help
5287 +         This option enables support for LEDs connected to GPIO lines
5288 +         on AT91-based boards.
5289 +
5290  config LEDS_WRAP
5291         tristate "LED Support for the WRAP series LEDs"
5292         depends on LEDS_CLASS && SCx200_GPIO
5293 Index: linux-2.6.21.7/drivers/leds/Makefile
5294 ===================================================================
5295 --- linux-2.6.21.7.orig/drivers/leds/Makefile
5296 +++ linux-2.6.21.7/drivers/leds/Makefile
5297 @@ -16,6 +16,7 @@ obj-$(CONFIG_LEDS_NET48XX)            += leds-net4
5298  obj-$(CONFIG_LEDS_WRAP)                        += leds-wrap.o
5299  obj-$(CONFIG_LEDS_H1940)               += leds-h1940.o
5300  obj-$(CONFIG_LEDS_COBALT)              += leds-cobalt.o
5301 +obj-$(CONFIG_LEDS_AT91)                        += leds-at91.o
5302
5303  # LED Triggers
5304  obj-$(CONFIG_LEDS_TRIGGER_TIMER)       += ledtrig-timer.o
5305 Index: linux-2.6.21.7/drivers/leds/leds-at91.c
5306 ===================================================================
5307 --- /dev/null
5308 +++ linux-2.6.21.7/drivers/leds/leds-at91.c
5309 @@ -0,0 +1,140 @@
5310 +/*
5311 + * AT91 GPIO based LED driver
5312 + *
5313 + * Copyright (C) 2006 David Brownell
5314 + *
5315 + * This program is free software; you can redistribute it and/or modify
5316 + * it under the terms of the GNU General Public License version 2 as
5317 + * published by the Free Software Foundation.
5318 + */
5319 +
5320 +#include <linux/kernel.h>
5321 +#include <linux/init.h>
5322 +#include <linux/platform_device.h>
5323 +#include <linux/leds.h>
5324 +
5325 +#include <asm/arch/board.h>
5326 +#include <asm/arch/gpio.h>
5327 +
5328 +static LIST_HEAD(at91_led_list);       /* list of AT91 LEDs */
5329 +
5330 +struct at91_led {
5331 +       struct led_classdev     cdev;
5332 +       struct list_head        list;
5333 +       struct at91_gpio_led    *led_data;
5334 +};
5335 +
5336 +/*
5337 + * Change the state of the LED.
5338 + */
5339 +static void at91_led_set(struct led_classdev *cdev, enum led_brightness value)
5340 +{
5341 +       struct at91_led *led = container_of(cdev, struct at91_led, cdev);
5342 +       short           active = (value == LED_OFF);
5343 +
5344 +       if (led->led_data->flags & 1)   /* active high/low? */
5345 +               active = !active;
5346 +       at91_set_gpio_value(led->led_data->gpio, active);
5347 +}
5348 +
5349 +static int __devexit at91_led_remove(struct platform_device *pdev)
5350 +{
5351 +       struct at91_led         *led;
5352 +
5353 +       list_for_each_entry (led, &at91_led_list, list)
5354 +               led_classdev_unregister(&led->cdev);
5355 +
5356 +#warning "Free allocated memory"
5357 +       // TODO: Free memory.   kfree(led);
5358 +
5359 +       return 0;
5360 +}
5361 +
5362 +static int __init at91_led_probe(struct platform_device *pdev)
5363 +{
5364 +       int                     status = 0;
5365 +       struct at91_gpio_led    *pdata = pdev->dev.platform_data;
5366 +       unsigned                nr_leds;
5367 +       struct at91_led         *led;
5368 +
5369 +       if (!pdata)
5370 +               return -ENODEV;
5371 +
5372 +       nr_leds = pdata->index;         /* first index stores number of LEDs */
5373 +
5374 +       while (nr_leds--) {
5375 +               led = kzalloc(sizeof(struct at91_led), GFP_KERNEL);
5376 +               if (!led) {
5377 +                       dev_err(&pdev->dev, "No memory for device\n");
5378 +                       status = -ENOMEM;
5379 +                       goto cleanup;
5380 +               }
5381 +               led->led_data = pdata;
5382 +               led->cdev.name = pdata->name;
5383 +               led->cdev.brightness_set = at91_led_set,
5384 +               led->cdev.default_trigger = pdata->trigger;
5385 +
5386 +               status = led_classdev_register(&pdev->dev, &led->cdev);
5387 +               if (status < 0) {
5388 +                       dev_err(&pdev->dev, "led_classdev_register failed - %d\n", status);
5389 +cleanup:
5390 +                       at91_led_remove(pdev);
5391 +                       break;
5392 +               }
5393 +               list_add(&led->list, &at91_led_list);
5394 +               pdata++;
5395 +       }
5396 +       return status;
5397 +}
5398 +
5399 +#ifdef CONFIG_PM
5400 +static int at91_led_suspend(struct platform_device *dev, pm_message_t state)
5401 +{
5402 +       struct at91_led *led;
5403 +
5404 +       list_for_each_entry (led, &at91_led_list, list)
5405 +               led_classdev_suspend(&led->cdev);
5406 +
5407 +       return 0;
5408 +}
5409 +
5410 +static int at91_led_resume(struct platform_device *dev)
5411 +{
5412 +       struct at91_led *led;
5413 +
5414 +       list_for_each_entry (led, &at91_led_list, list)
5415 +               led_classdev_resume(&led->cdev);
5416 +
5417 +       return 0;
5418 +}
5419 +#else
5420 +#define        at91_led_suspend        NULL
5421 +#define        at91_led_resume         NULL
5422 +#endif
5423 +
5424 +static struct platform_driver at91_led_driver = {
5425 +       .probe          = at91_led_probe,
5426 +       .remove         = __devexit_p(at91_led_remove),
5427 +       .suspend        = at91_led_suspend,
5428 +       .resume         = at91_led_resume,
5429 +       .driver         = {
5430 +               .name   = "at91_leds",
5431 +               .owner  = THIS_MODULE,
5432 +       },
5433 +};
5434 +
5435 +static int __init at91_led_init(void)
5436 +{
5437 +       return platform_driver_register(&at91_led_driver);
5438 +}
5439 +module_init(at91_led_init);
5440 +
5441 +static void __exit at91_led_exit(void)
5442 +{
5443 +       platform_driver_unregister(&at91_led_driver);
5444 +}
5445 +module_exit(at91_led_exit);
5446 +
5447 +MODULE_DESCRIPTION("AT91 GPIO LED driver");
5448 +MODULE_AUTHOR("David Brownell");
5449 +MODULE_LICENSE("GPL");
5450 Index: linux-2.6.21.7/drivers/mmc/at91_mci.c
5451 ===================================================================
5452 --- linux-2.6.21.7.orig/drivers/mmc/at91_mci.c
5453 +++ linux-2.6.21.7/drivers/mmc/at91_mci.c
5454 @@ -86,7 +86,7 @@
5455
5456  #define AT91_MCI_ERRORS        (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE       \
5457                 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE               \
5458 -               | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
5459 +               | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
5460
5461  #define at91_mci_read(host, reg)       __raw_readl((host)->baseaddr + (reg))
5462  #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
5463 @@ -561,9 +561,7 @@ static void at91mci_completed_command(st
5464         pr_debug("Status = %08X [%08X %08X %08X %08X]\n",
5465                  status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
5466
5467 -       if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE |
5468 -                       AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE |
5469 -                       AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) {
5470 +       if (status & AT91_MCI_ERRORS) {
5471                 if ((status & AT91_MCI_RCRCE) &&
5472                         ((cmd->opcode == MMC_SEND_OP_COND) || (cmd->opcode == SD_APP_OP_COND))) {
5473                         cmd->error = MMC_ERR_NONE;
5474 @@ -665,15 +663,15 @@ static irqreturn_t at91_mci_irq(int irq,
5475
5476         int_status = at91_mci_read(host, AT91_MCI_SR);
5477         int_mask = at91_mci_read(host, AT91_MCI_IMR);
5478 -
5479 +
5480         pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
5481                 int_status & int_mask);
5482 -
5483 +
5484         int_status = int_status & int_mask;
5485
5486         if (int_status & AT91_MCI_ERRORS) {
5487                 completed = 1;
5488 -
5489 +
5490                 if (int_status & AT91_MCI_UNRE)
5491                         pr_debug("MMC: Underrun error\n");
5492                 if (int_status & AT91_MCI_OVRE)
5493 @@ -821,7 +819,7 @@ static int __init at91_mci_probe(struct
5494         mmc->f_min = 375000;
5495         mmc->f_max = 25000000;
5496         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
5497 -       mmc->caps = MMC_CAP_BYTEBLOCK;
5498 +       mmc->caps = MMC_CAP_BYTEBLOCK | MMC_CAP_MULTIWRITE;
5499
5500         mmc->max_blk_size = 4095;
5501         mmc->max_blk_count = mmc->max_req_size;
5502 @@ -895,6 +893,8 @@ static int __init at91_mci_probe(struct
5503
5504         mmc_add_host(mmc);
5505
5506 +       device_init_wakeup(&pdev->dev, 1);
5507 +
5508         /*
5509          * monitor card insertion/removal if we can
5510          */
5511 @@ -924,6 +924,8 @@ static int __exit at91_mci_remove(struct
5512
5513         host = mmc_priv(mmc);
5514
5515 +       device_init_wakeup(&pdev->dev, 0);
5516 +
5517         if (host->present != -1) {
5518                 free_irq(host->board->det_pin, host);
5519                 cancel_delayed_work(&host->mmc->detect);
5520 @@ -951,8 +953,12 @@ static int __exit at91_mci_remove(struct
5521  static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
5522  {
5523         struct mmc_host *mmc = platform_get_drvdata(pdev);
5524 +       struct at91mci_host *host = mmc_priv(mmc);
5525         int ret = 0;
5526
5527 +       if (device_may_wakeup(&pdev->dev))
5528 +               enable_irq_wake(host->board->det_pin);
5529 +
5530         if (mmc)
5531                 ret = mmc_suspend_host(mmc, state);
5532
5533 @@ -962,8 +968,12 @@ static int at91_mci_suspend(struct platf
5534  static int at91_mci_resume(struct platform_device *pdev)
5535  {
5536         struct mmc_host *mmc = platform_get_drvdata(pdev);
5537 +       struct at91mci_host *host = mmc_priv(mmc);
5538         int ret = 0;
5539
5540 +       if (device_may_wakeup(&pdev->dev))
5541 +               disable_irq_wake(host->board->det_pin);
5542 +
5543         if (mmc)
5544                 ret = mmc_resume_host(mmc);
5545
5546 Index: linux-2.6.21.7/drivers/mtd/devices/Kconfig
5547 ===================================================================
5548 --- linux-2.6.21.7.orig/drivers/mtd/devices/Kconfig
5549 +++ linux-2.6.21.7/drivers/mtd/devices/Kconfig
5550 @@ -267,5 +267,11 @@ config MTD_DOCPROBE_55AA
5551           LinuxBIOS or if you need to recover a DiskOnChip Millennium on which
5552           you have managed to wipe the first block.
5553
5554 -endmenu
5555 +config MTD_AT91_DATAFLASH
5556 +       tristate "AT91RM9200 DataFlash AT45DBxxx (legacy driver)"
5557 +       depends on MTD && ARCH_AT91RM9200 && AT91_SPI
5558 +       help
5559 +         This enables access to the DataFlash (AT45DBxxx) on the AT91RM9200.
5560 +         If you have such a board, say 'Y'.
5561
5562 +endmenu
5563 Index: linux-2.6.21.7/drivers/mtd/devices/Makefile
5564 ===================================================================
5565 --- linux-2.6.21.7.orig/drivers/mtd/devices/Makefile
5566 +++ linux-2.6.21.7/drivers/mtd/devices/Makefile
5567 @@ -17,3 +17,4 @@ obj-$(CONFIG_MTD_LART)                += lart.o
5568  obj-$(CONFIG_MTD_BLOCK2MTD)    += block2mtd.o
5569  obj-$(CONFIG_MTD_DATAFLASH)    += mtd_dataflash.o
5570  obj-$(CONFIG_MTD_M25P80)       += m25p80.o
5571 +obj-$(CONFIG_MTD_AT91_DATAFLASH)+= at91_dataflash.o
5572 Index: linux-2.6.21.7/drivers/mtd/devices/at91_dataflash.c
5573 ===================================================================
5574 --- /dev/null
5575 +++ linux-2.6.21.7/drivers/mtd/devices/at91_dataflash.c
5576 @@ -0,0 +1,667 @@
5577 +/*
5578 + * Atmel DataFlash driver for Atmel AT91RM9200 (Thunder)
5579 + *
5580 + *  Copyright (C) SAN People (Pty) Ltd
5581 + *
5582 + * This program is free software; you can redistribute it and/or
5583 + * modify it under the terms of the GNU General Public License
5584 + * as published by the Free Software Foundation; either version
5585 + * 2 of the License, or (at your option) any later version.
5586 +*/
5587 +
5588 +#include <linux/module.h>
5589 +#include <linux/init.h>
5590 +#include <linux/slab.h>
5591 +#include <linux/pci.h>
5592 +#include <linux/mtd/mtd.h>
5593 +#include <linux/mtd/partitions.h>
5594 +
5595 +#include <asm/arch/spi.h>
5596 +
5597 +#undef DEBUG_DATAFLASH
5598 +
5599 +#define DATAFLASH_MAX_DEVICES  4       /* max number of dataflash devices */
5600 +#undef DATAFLASH_ALWAYS_ADD_DEVICE     /* always add whole device when using partitions? */
5601 +
5602 +#define OP_READ_CONTINUOUS     0xE8
5603 +#define OP_READ_PAGE           0xD2
5604 +#define OP_READ_BUFFER1                0xD4
5605 +#define OP_READ_BUFFER2                0xD6
5606 +#define OP_READ_STATUS         0xD7
5607 +
5608 +#define OP_ERASE_PAGE          0x81
5609 +#define OP_ERASE_BLOCK         0x50
5610 +
5611 +#define OP_TRANSFER_BUF1       0x53
5612 +#define OP_TRANSFER_BUF2       0x55
5613 +#define OP_COMPARE_BUF1                0x60
5614 +#define OP_COMPARE_BUF2                0x61
5615 +
5616 +#define OP_PROGRAM_VIA_BUF1    0x82
5617 +#define OP_PROGRAM_VIA_BUF2    0x85
5618 +
5619 +struct dataflash_local
5620 +{
5621 +       int spi;                        /* SPI chip-select number */
5622 +
5623 +       unsigned int page_size;         /* number of bytes per page */
5624 +       unsigned short page_offset;     /* page offset in flash address */
5625 +};
5626 +
5627 +
5628 +/* Detected DataFlash devices */
5629 +static struct mtd_info* mtd_devices[DATAFLASH_MAX_DEVICES];
5630 +static int nr_devices = 0;
5631 +
5632 +/* ......................................................................... */
5633 +
5634 +#ifdef CONFIG_MTD_PARTITIONS
5635 +
5636 +static struct mtd_partition static_partitions_2M[] =
5637 +{
5638 +       {
5639 +               .name           = "bootloader",
5640 +               .offset         = 0,
5641 +               .size           = 1 * 32 * 8 * 528,     /* 1st sector = 32 blocks * 8 pages * 528 bytes */
5642 +               .mask_flags     = MTD_WRITEABLE,        /* read-only */
5643 +       },
5644 +       {
5645 +               .name           = "kernel",
5646 +               .offset         = MTDPART_OFS_NXTBLK,
5647 +               .size           = 6 * 32 * 8 * 528,     /* 6 sectors */
5648 +       },
5649 +       {
5650 +               .name           = "filesystem",
5651 +               .offset         = MTDPART_OFS_NXTBLK,
5652 +               .size           = MTDPART_SIZ_FULL,     /* rest = 9 sectors */
5653 +       }
5654 +};
5655 +
5656 +static struct mtd_partition static_partitions_4M[] =
5657 +{
5658 +       {
5659 +               .name           = "bootloader",
5660 +               .offset         = 0,
5661 +               .size           = 1 * 64 * 8 * 528,     /* 1st sector = 64 blocks * 8 pages * 528 bytes */
5662 +               .mask_flags     = MTD_WRITEABLE,        /* read-only */
5663 +       },
5664 +       {
5665 +               .name           = "kernel",
5666 +               .offset         = MTDPART_OFS_NXTBLK,
5667 +               .size           = 4 * 64 * 8 * 528,     /* 4 sectors */
5668 +       },
5669 +       {
5670 +               .name           = "filesystem",
5671 +               .offset         = MTDPART_OFS_NXTBLK,
5672 +               .size           = MTDPART_SIZ_FULL,     /* rest = 11 sectors */
5673 +       }
5674 +};
5675 +
5676 +#if defined(CONFIG_MACH_KAFA)
5677 +static struct mtd_partition static_partitions_8M[] =
5678 +{
5679 +       {
5680 +               name:           "romboot",
5681 +               offset:         0,
5682 +               size:           16 * 1056,      /* 160 Kb */
5683 +               mask_flags:     MTD_WRITEABLE,          /* read-only */
5684 +       },
5685 +       {
5686 +               name:           "uboot",
5687 +               offset:         MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
5688 +               size:           128 * 1056,             /* 1 MB */
5689 +       },
5690 +       {
5691 +               name:           "kernel",
5692 +               offset:         MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
5693 +               size:           1024 * 1056,            /* 1 MB */
5694 +       },
5695 +       {
5696 +               name:           "filesystem",
5697 +               offset:         MTDPART_OFS_APPEND, /* Sperry, NXTBLK is broken */
5698 +               size:           MTDPART_SIZ_FULL,
5699 +       }
5700 +};
5701 +
5702 +#elif defined(CONFIG_MACH_MULTMDP)
5703 +
5704 +static struct mtd_partition static_partitions_8M[] =
5705 +{
5706 +       {
5707 +               .name           = "bootloader",
5708 +               .offset         = 0,
5709 +               .size           = 12 * 1056,            /* 1st sector = 32 blocks * 8 pages * 1056 bytes */
5710 +               .mask_flags     = MTD_WRITEABLE,        /* read-only */
5711 +       },
5712 +       {
5713 +               .name           = "configuration",
5714 +               .offset         = MTDPART_OFS_NXTBLK,
5715 +               .size           = 20 * 1056,
5716 +       },
5717 +       {
5718 +               .name           = "kernel",
5719 +               .offset         = MTDPART_OFS_NXTBLK,
5720 +               .size           = 1520 * 1056,
5721 +       },
5722 +       {
5723 +               .name           = "filesystem",
5724 +               .offset         = MTDPART_OFS_NXTBLK,
5725 +               .size           = MTDPART_SIZ_FULL,
5726 +       }
5727 +};
5728 +
5729 +#else
5730 +
5731 +static struct mtd_partition static_partitions_8M[] =
5732 +{
5733 +       {
5734 +               .name           = "bootloader",
5735 +               .offset         = 0,
5736 +               .size           = 1 * 32 * 8 * 1056,    /* 1st sector = 32 blocks * 8 pages * 1056 bytes */
5737 +               .mask_flags     = MTD_WRITEABLE,        /* read-only */
5738 +       },
5739 +       {
5740 +               .name           = "kernel",
5741 +               .offset         = MTDPART_OFS_NXTBLK,
5742 +               .size           = 5 * 32 * 8 * 1056,    /* 5 sectors */
5743 +       },
5744 +       {
5745 +               .name           = "filesystem",
5746 +               .offset         = MTDPART_OFS_NXTBLK,
5747 +               .size           = MTDPART_SIZ_FULL,     /* rest = 26 sectors */
5748 +       }
5749 +};
5750 +#endif
5751 +
5752 +static const char *part_probes[] = { "cmdlinepart", NULL, };
5753 +
5754 +#endif
5755 +
5756 +/* ......................................................................... */
5757 +
5758 +/* Allocate a single SPI transfer descriptor.  We're assuming that if multiple
5759 +   SPI transfers occur at the same time, spi_access_bus() will serialize them.
5760 +   If this is not valid, then either (i) each dataflash 'priv' structure
5761 +   needs it's own transfer descriptor, (ii) we lock this one, or (iii) use
5762 +   another mechanism.   */
5763 +static struct spi_transfer_list* spi_transfer_desc;
5764 +
5765 +/*
5766 + * Perform a SPI transfer to access the DataFlash device.
5767 + */
5768 +static int do_spi_transfer(int nr, char* tx, int tx_len, char* rx, int rx_len,
5769 +               char* txnext, int txnext_len, char* rxnext, int rxnext_len)
5770 +{
5771 +       struct spi_transfer_list* list = spi_transfer_desc;
5772 +
5773 +       list->tx[0] = tx;       list->txlen[0] = tx_len;
5774 +       list->rx[0] = rx;       list->rxlen[0] = rx_len;
5775 +
5776 +       list->tx[1] = txnext;   list->txlen[1] = txnext_len;
5777 +       list->rx[1] = rxnext;   list->rxlen[1] = rxnext_len;
5778 +
5779 +       list->nr_transfers = nr;
5780 +
5781 +       return spi_transfer(list);
5782 +}
5783 +
5784 +/* ......................................................................... */
5785 +
5786 +/*
5787 + * Poll the DataFlash device until it is READY.
5788 + */
5789 +static void at91_dataflash_waitready(void)
5790 +{
5791 +       char* command = kmalloc(2, GFP_KERNEL);
5792 +
5793 +       if (!command)
5794 +               return;
5795 +
5796 +       do {
5797 +               command[0] = OP_READ_STATUS;
5798 +               command[1] = 0;
5799 +
5800 +               do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
5801 +       } while ((command[1] & 0x80) == 0);
5802 +
5803 +       kfree(command);
5804 +}
5805 +
5806 +/*
5807 + * Return the status of the DataFlash device.
5808 + */
5809 +static unsigned short at91_dataflash_status(void)
5810 +{
5811 +       unsigned short status;
5812 +       char* command = kmalloc(2, GFP_KERNEL);
5813 +
5814 +       if (!command)
5815 +               return 0;
5816 +
5817 +       command[0] = OP_READ_STATUS;
5818 +       command[1] = 0;
5819 +
5820 +       do_spi_transfer(1, command, 2, command, 2, NULL, 0, NULL, 0);
5821 +       status = command[1];
5822 +
5823 +       kfree(command);
5824 +       return status;
5825 +}
5826 +
5827 +/* ......................................................................... */
5828 +
5829 +/*
5830 + * Erase blocks of flash.
5831 + */
5832 +static int at91_dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
5833 +{
5834 +       struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
5835 +       unsigned int pageaddr;
5836 +       char* command;
5837 +
5838 +#ifdef DEBUG_DATAFLASH
5839 +       printk("dataflash_erase: addr=%i len=%i\n", instr->addr, instr->len);
5840 +#endif
5841 +
5842 +       /* Sanity checks */
5843 +       if (instr->addr + instr->len > mtd->size)
5844 +               return -EINVAL;
5845 +       if ((instr->len % mtd->erasesize != 0) || (instr->len % priv->page_size != 0))
5846 +               return -EINVAL;
5847 +       if ((instr->addr % priv->page_size) != 0)
5848 +               return -EINVAL;
5849 +
5850 +       command = kmalloc(4, GFP_KERNEL);
5851 +       if (!command)
5852 +               return -ENOMEM;
5853 +
5854 +       while (instr->len > 0) {
5855 +               /* Calculate flash page address */
5856 +               pageaddr = (instr->addr / priv->page_size) << priv->page_offset;
5857 +
5858 +               command[0] = OP_ERASE_PAGE;
5859 +               command[1] = (pageaddr & 0x00FF0000) >> 16;
5860 +               command[2] = (pageaddr & 0x0000FF00) >> 8;
5861 +               command[3] = 0;
5862 +#ifdef DEBUG_DATAFLASH
5863 +               printk("ERASE: (%x) %x %x %x [%i]\n", command[0], command[1], command[2], command[3], pageaddr);
5864 +#endif
5865 +
5866 +               /* Send command to SPI device */
5867 +               spi_access_bus(priv->spi);
5868 +               do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
5869 +
5870 +               at91_dataflash_waitready();             /* poll status until ready */
5871 +               spi_release_bus(priv->spi);
5872 +
5873 +               instr->addr += priv->page_size;         /* next page */
5874 +               instr->len -= priv->page_size;
5875 +       }
5876 +
5877 +       kfree(command);
5878 +
5879 +       /* Inform MTD subsystem that erase is complete */
5880 +       instr->state = MTD_ERASE_DONE;
5881 +       if (instr->callback)
5882 +               instr->callback(instr);
5883 +
5884 +       return 0;
5885 +}
5886 +
5887 +/*
5888 + * Read from the DataFlash device.
5889 + *   from   : Start offset in flash device
5890 + *   len    : Amount to read
5891 + *   retlen : About of data actually read
5892 + *   buf    : Buffer containing the data
5893 + */
5894 +static int at91_dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
5895 +{
5896 +       struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
5897 +       unsigned int addr;
5898 +       char* command;
5899 +
5900 +#ifdef DEBUG_DATAFLASH
5901 +       printk("dataflash_read: %lli .. %lli\n", from, from+len);
5902 +#endif
5903 +
5904 +       *retlen = 0;
5905 +
5906 +       /* Sanity checks */
5907 +       if (!len)
5908 +               return 0;
5909 +       if (from + len > mtd->size)
5910 +               return -EINVAL;
5911 +
5912 +       /* Calculate flash page/byte address */
5913 +       addr = (((unsigned)from / priv->page_size) << priv->page_offset) + ((unsigned)from % priv->page_size);
5914 +
5915 +       command = kmalloc(8, GFP_KERNEL);
5916 +       if (!command)
5917 +               return -ENOMEM;
5918 +
5919 +       command[0] = OP_READ_CONTINUOUS;
5920 +       command[1] = (addr & 0x00FF0000) >> 16;
5921 +       command[2] = (addr & 0x0000FF00) >> 8;
5922 +       command[3] = (addr & 0x000000FF);
5923 +#ifdef DEBUG_DATAFLASH
5924 +       printk("READ: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
5925 +#endif
5926 +
5927 +       /* Send command to SPI device */
5928 +       spi_access_bus(priv->spi);
5929 +       do_spi_transfer(2, command, 8, command, 8, buf, len, buf, len);
5930 +       spi_release_bus(priv->spi);
5931 +
5932 +       *retlen = len;
5933 +       kfree(command);
5934 +       return 0;
5935 +}
5936 +
5937 +/*
5938 + * Write to the DataFlash device.
5939 + *   to     : Start offset in flash device
5940 + *   len    : Amount to write
5941 + *   retlen : Amount of data actually written
5942 + *   buf    : Buffer containing the data
5943 + */
5944 +static int at91_dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
5945 +{
5946 +       struct dataflash_local *priv = (struct dataflash_local *) mtd->priv;
5947 +       unsigned int pageaddr, addr, offset, writelen;
5948 +       size_t remaining;
5949 +       u_char *writebuf;
5950 +       unsigned short status;
5951 +       int res = 0;
5952 +       char* command;
5953 +       char* tmpbuf = NULL;
5954 +
5955 +#ifdef DEBUG_DATAFLASH
5956 +       printk("dataflash_write: %lli .. %lli\n", to, to+len);
5957 +#endif
5958 +
5959 +       *retlen = 0;
5960 +
5961 +       /* Sanity checks */
5962 +       if (!len)
5963 +               return 0;
5964 +       if (to + len > mtd->size)
5965 +               return -EINVAL;
5966 +
5967 +       command = kmalloc(4, GFP_KERNEL);
5968 +       if (!command)
5969 +               return -ENOMEM;
5970 +
5971 +       pageaddr = ((unsigned)to / priv->page_size);
5972 +       offset = ((unsigned)to % priv->page_size);
5973 +       if (offset + len > priv->page_size)
5974 +               writelen = priv->page_size - offset;
5975 +       else
5976 +               writelen = len;
5977 +       writebuf = (u_char *)buf;
5978 +       remaining = len;
5979 +
5980 +       /* Allocate temporary buffer */
5981 +       tmpbuf = kmalloc(priv->page_size, GFP_KERNEL);
5982 +       if (!tmpbuf) {
5983 +               kfree(command);
5984 +               return -ENOMEM;
5985 +       }
5986 +
5987 +       /* Gain access to the SPI bus */
5988 +       spi_access_bus(priv->spi);
5989 +
5990 +       while (remaining > 0) {
5991 +#ifdef DEBUG_DATAFLASH
5992 +               printk("write @ %i:%i len=%i\n", pageaddr, offset, writelen);
5993 +#endif
5994 +
5995 +               /* (1) Transfer to Buffer1 */
5996 +               if (writelen != priv->page_size) {
5997 +                       addr = pageaddr << priv->page_offset;
5998 +                       command[0] = OP_TRANSFER_BUF1;
5999 +                       command[1] = (addr & 0x00FF0000) >> 16;
6000 +                       command[2] = (addr & 0x0000FF00) >> 8;
6001 +                       command[3] = 0;
6002 +#ifdef DEBUG_DATAFLASH
6003 +                       printk("TRANSFER: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
6004 +#endif
6005 +                       do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
6006 +                       at91_dataflash_waitready();
6007 +               }
6008 +
6009 +               /* (2) Program via Buffer1 */
6010 +               addr = (pageaddr << priv->page_offset) + offset;
6011 +               command[0] = OP_PROGRAM_VIA_BUF1;
6012 +               command[1] = (addr & 0x00FF0000) >> 16;
6013 +               command[2] = (addr & 0x0000FF00) >> 8;
6014 +               command[3] = (addr & 0x000000FF);
6015 +#ifdef DEBUG_DATAFLASH
6016 +               printk("PROGRAM: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
6017 +#endif
6018 +               do_spi_transfer(2, command, 4, command, 4, writebuf, writelen, tmpbuf, writelen);
6019 +               at91_dataflash_waitready();
6020 +
6021 +               /* (3) Compare to Buffer1 */
6022 +               addr = pageaddr << priv->page_offset;
6023 +               command[0] = OP_COMPARE_BUF1;
6024 +               command[1] = (addr & 0x00FF0000) >> 16;
6025 +               command[2] = (addr & 0x0000FF00) >> 8;
6026 +               command[3] = 0;
6027 +#ifdef DEBUG_DATAFLASH
6028 +               printk("COMPARE: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]);
6029 +#endif
6030 +               do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0);
6031 +               at91_dataflash_waitready();
6032 +
6033 +               /* Get result of the compare operation */
6034 +               status = at91_dataflash_status();
6035 +               if ((status & 0x40) == 1) {
6036 +                       printk("at91_dataflash: Write error on page %i\n", pageaddr);
6037 +                       remaining = 0;
6038 +                       res = -EIO;
6039 +               }
6040 +
6041 +               remaining = remaining - writelen;
6042 +               pageaddr++;
6043 +               offset = 0;
6044 +               writebuf += writelen;
6045 +               *retlen += writelen;
6046 +
6047 +               if (remaining > priv->page_size)
6048 +                       writelen = priv->page_size;
6049 +               else
6050 +                       writelen = remaining;
6051 +       }
6052 +
6053 +       /* Release SPI bus */
6054 +       spi_release_bus(priv->spi);
6055 +
6056 +       kfree(tmpbuf);
6057 +       kfree(command);
6058 +       return res;
6059 +}
6060 +
6061 +/* ......................................................................... */
6062 +
6063 +/*
6064 + * Initialize and register DataFlash device with MTD subsystem.
6065 + */
6066 +static int __init add_dataflash(int channel, char *name, int IDsize,
6067 +               int nr_pages, int pagesize, int pageoffset)
6068 +{
6069 +       struct mtd_info *device;
6070 +       struct dataflash_local *priv;
6071 +#ifdef CONFIG_MTD_PARTITIONS
6072 +       struct mtd_partition *mtd_parts = 0;
6073 +       int mtd_parts_nr = 0;
6074 +#endif
6075 +
6076 +       if (nr_devices >= DATAFLASH_MAX_DEVICES) {
6077 +               printk(KERN_ERR "at91_dataflash: Too many devices detected\n");
6078 +               return 0;
6079 +       }
6080 +
6081 +       device = kmalloc(sizeof(struct mtd_info) + strlen(name) + 8, GFP_KERNEL);
6082 +       if (!device)
6083 +               return -ENOMEM;
6084 +       memset(device, 0, sizeof(struct mtd_info));
6085 +
6086 +       device->name = (char *)&device[1];
6087 +       sprintf(device->name, "%s.spi%d", name, channel);
6088 +       device->size = nr_pages * pagesize;
6089 +       device->erasesize = pagesize;
6090 +       device->writesize = pagesize;
6091 +       device->owner = THIS_MODULE;
6092 +       device->type = MTD_DATAFLASH;
6093 +       device->flags = MTD_WRITEABLE;
6094 +       device->erase = at91_dataflash_erase;
6095 +       device->read = at91_dataflash_read;
6096 +       device->write = at91_dataflash_write;
6097 +
6098 +       priv = (struct dataflash_local *) kmalloc(sizeof(struct dataflash_local), GFP_KERNEL);
6099 +       if (!priv) {
6100 +               kfree(device);
6101 +               return -ENOMEM;
6102 +       }
6103 +       memset(priv, 0, sizeof(struct dataflash_local));
6104 +
6105 +       priv->spi = channel;
6106 +       priv->page_size = pagesize;
6107 +       priv->page_offset = pageoffset;
6108 +       device->priv = priv;
6109 +
6110 +       mtd_devices[nr_devices] = device;
6111 +       nr_devices++;
6112 +       printk("at91_dataflash: %s detected [spi%i] (%i bytes)\n", name, channel, device->size);
6113 +
6114 +#ifdef CONFIG_MTD_PARTITIONS
6115 +#ifdef CONFIG_MTD_CMDLINE_PARTS
6116 +       mtd_parts_nr = parse_mtd_partitions(device, part_probes, &mtd_parts, 0);
6117 +#endif
6118 +       if (mtd_parts_nr <= 0) {
6119 +               switch (IDsize) {
6120 +                       case SZ_2M:
6121 +                               mtd_parts = static_partitions_2M;
6122 +                               mtd_parts_nr = ARRAY_SIZE(static_partitions_2M);
6123 +                               break;
6124 +                       case SZ_4M:
6125 +                               mtd_parts = static_partitions_4M;
6126 +                               mtd_parts_nr = ARRAY_SIZE(static_partitions_4M);
6127 +                               break;
6128 +                       case SZ_8M:
6129 +                               mtd_parts = static_partitions_8M;
6130 +                               mtd_parts_nr = ARRAY_SIZE(static_partitions_8M);
6131 +                               break;
6132 +               }
6133 +       }
6134 +
6135 +       if (mtd_parts_nr > 0) {
6136 +#ifdef DATAFLASH_ALWAYS_ADD_DEVICE
6137 +               add_mtd_device(device);
6138 +#endif
6139 +               return add_mtd_partitions(device, mtd_parts, mtd_parts_nr);
6140 +       }
6141 +#endif
6142 +       return add_mtd_device(device);          /* add whole device */
6143 +}
6144 +
6145 +/*
6146 + * Detect and initialize DataFlash device connected to specified SPI channel.
6147 + *
6148 + *   Device            Density         ID code                 Nr Pages        Page Size       Page offset
6149 + *   AT45DB011B        1Mbit   (128K)  xx0011xx (0x0c)         512             264             9
6150 + *   AT45DB021B        2Mbit   (256K)  xx0101xx (0x14)         1025            264             9
6151 + *   AT45DB041B        4Mbit   (512K)  xx0111xx (0x1c)         2048            264             9
6152 + *   AT45DB081B        8Mbit   (1M)    xx1001xx (0x24)         4096            264             9
6153 + *   AT45DB0161B       16Mbit  (2M)    xx1011xx (0x2c)         4096            528             10
6154 + *   AT45DB0321B       32Mbit  (4M)    xx1101xx (0x34)         8192            528             10
6155 + *   AT45DB0642        64Mbit  (8M)    xx1111xx (0x3c)         8192            1056            11
6156 + *   AT45DB1282        128Mbit (16M)   xx0100xx (0x10)         16384           1056            11
6157 + */
6158 +static int __init at91_dataflash_detect(int channel)
6159 +{
6160 +       int res = 0;
6161 +       unsigned short status;
6162 +
6163 +       spi_access_bus(channel);
6164 +       status = at91_dataflash_status();
6165 +       spi_release_bus(channel);
6166 +       if (status != 0xff) {                   /* no dataflash device there */
6167 +               switch (status & 0x3c) {
6168 +                       case 0x0c:      /* 0 0 1 1 */
6169 +                               res = add_dataflash(channel, "AT45DB011B", SZ_128K, 512, 264, 9);
6170 +                               break;
6171 +                       case 0x14:      /* 0 1 0 1 */
6172 +                               res = add_dataflash(channel, "AT45DB021B", SZ_256K, 1025, 264, 9);
6173 +                               break;
6174 +                       case 0x1c:      /* 0 1 1 1 */
6175 +                               res = add_dataflash(channel, "AT45DB041B", SZ_512K, 2048, 264, 9);
6176 +                               break;
6177 +                       case 0x24:      /* 1 0 0 1 */
6178 +                               res = add_dataflash(channel, "AT45DB081B", SZ_1M, 4096, 264, 9);
6179 +                               break;
6180 +                       case 0x2c:      /* 1 0 1 1 */
6181 +                               res = add_dataflash(channel, "AT45DB161B", SZ_2M, 4096, 528, 10);
6182 +                               break;
6183 +                       case 0x34:      /* 1 1 0 1 */
6184 +                               res = add_dataflash(channel, "AT45DB321B", SZ_4M, 8192, 528, 10);
6185 +                               break;
6186 +                       case 0x3c:      /* 1 1 1 1 */
6187 +                               res = add_dataflash(channel, "AT45DB642", SZ_8M, 8192, 1056, 11);
6188 +                               break;
6189 +// Currently unsupported since Atmel removed the "Main Memory Program via Buffer" commands.
6190 +//                     case 0x10:      /* 0 1 0 0 */
6191 +//                             res = add_dataflash(channel, "AT45DB1282", SZ_16M, 16384, 1056, 11);
6192 +//                             break;
6193 +                       default:
6194 +                               printk(KERN_ERR "at91_dataflash: Unknown device (%x)\n", status & 0x3c);
6195 +               }
6196 +       }
6197 +
6198 +       return res;
6199 +}
6200 +
6201 +static int __init at91_dataflash_init(void)
6202 +{
6203 +       spi_transfer_desc = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL);
6204 +       if (!spi_transfer_desc)
6205 +               return -ENOMEM;
6206 +
6207 +       /* DataFlash (SPI chip select 0) */
6208 +       at91_dataflash_detect(0);
6209 +
6210 +#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
6211 +       /* DataFlash card (SPI chip select 3) */
6212 +       at91_dataflash_detect(3);
6213 +#endif
6214 +
6215 +       return 0;
6216 +}
6217 +
6218 +static void __exit at91_dataflash_exit(void)
6219 +{
6220 +       int i;
6221 +
6222 +       for (i = 0; i < DATAFLASH_MAX_DEVICES; i++) {
6223 +               if (mtd_devices[i]) {
6224 +#ifdef CONFIG_MTD_PARTITIONS
6225 +                       del_mtd_partitions(mtd_devices[i]);
6226 +#else
6227 +                       del_mtd_device(mtd_devices[i]);
6228 +#endif
6229 +                       kfree(mtd_devices[i]->priv);
6230 +                       kfree(mtd_devices[i]);
6231 +               }
6232 +       }
6233 +       nr_devices = 0;
6234 +       kfree(spi_transfer_desc);
6235 +}
6236 +
6237 +
6238 +module_init(at91_dataflash_init);
6239 +module_exit(at91_dataflash_exit);
6240 +
6241 +MODULE_LICENSE("GPL");
6242 +MODULE_AUTHOR("Andrew Victor");
6243 +MODULE_DESCRIPTION("DataFlash driver for Atmel AT91RM9200");
6244 Index: linux-2.6.21.7/drivers/mtd/nand/at91_nand.c
6245 ===================================================================
6246 --- linux-2.6.21.7.orig/drivers/mtd/nand/at91_nand.c
6247 +++ linux-2.6.21.7/drivers/mtd/nand/at91_nand.c
6248 @@ -82,6 +82,10 @@ static void at91_nand_disable(struct at9
6249                 at91_set_gpio_value(host->board->enable_pin, 1);
6250  }
6251
6252 +#ifdef CONFIG_MTD_PARTITIONS
6253 +const char *part_probes[] = { "cmdlinepart", NULL };
6254 +#endif
6255 +
6256  /*
6257   * Probe for the NAND device.
6258   */
6259 @@ -151,6 +155,12 @@ static int __init at91_nand_probe(struct
6260  #ifdef CONFIG_MTD_PARTITIONS
6261         if (host->board->partition_info)
6262                 partitions = host->board->partition_info(mtd->size, &num_partitions);
6263 +#ifdef CONFIG_MTD_CMDLINE_PARTS
6264 +       else {
6265 +               mtd->name = "at91_nand";
6266 +               num_partitions = parse_mtd_partitions(mtd, part_probes, &partitions, 0);
6267 +       }
6268 +#endif
6269
6270         if ((!partitions) || (num_partitions == 0)) {
6271                 printk(KERN_ERR "at91_nand: No parititions defined, or unsupported device.\n");
6272 Index: linux-2.6.21.7/drivers/net/arm/at91_ether.c
6273 ===================================================================
6274 --- linux-2.6.21.7.orig/drivers/net/arm/at91_ether.c
6275 +++ linux-2.6.21.7/drivers/net/arm/at91_ether.c
6276 @@ -225,6 +225,16 @@ static irqreturn_t at91ether_phy_interru
6277                 if (!(phy & ((1 << 2) | 1)))
6278                         goto done;
6279         }
6280 +       else if (lp->phy_type == MII_T78Q21x3_ID) {                     /* ack interrupt in Teridian PHY */
6281 +               read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
6282 +               if (!(phy & ((1 << 2) | 1)))
6283 +                       goto done;
6284 +       }
6285 +       else if (lp->phy_type == MII_DP83848_ID) {
6286 +               read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy);      /* ack interrupt in DP83848 PHY */
6287 +               if (!(phy & (1 << 7)))
6288 +                       goto done;
6289 +       }
6290
6291         update_linkspeed(dev, 0);
6292
6293 @@ -280,6 +290,19 @@ static void enable_phyirq(struct net_dev
6294                 dsintr = (1 << 10) | ( 1 << 8);
6295                 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
6296         }
6297 +       else if (lp->phy_type == MII_T78Q21x3_ID) {     /* for Teridian PHY */
6298 +               read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
6299 +               dsintr = dsintr | 0x500;                /* set bits 8, 10 */
6300 +               write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
6301 +       }
6302 +       else if (lp->phy_type == MII_DP83848_ID) {      /* National Semiconductor DP83848 PHY */
6303 +               read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
6304 +               dsintr = dsintr | 0x3c;                 /* set bits 2..5 */
6305 +               write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
6306 +               read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
6307 +               dsintr = dsintr | 0x3;                  /* set bits 0,1 */
6308 +               write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
6309 +       }
6310
6311         disable_mdi();
6312         spin_unlock_irq(&lp->lock);
6313 @@ -323,6 +346,19 @@ static void disable_phyirq(struct net_de
6314                 dsintr = ~((1 << 10) | (1 << 8));
6315                 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
6316         }
6317 +       else if (lp->phy_type == MII_T78Q21x3_ID) {     /* for Teridian PHY */
6318 +               read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
6319 +               dsintr = dsintr & ~0x500;                       /* clear bits 8, 10 */
6320 +               write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
6321 +       }
6322 +       else if (lp->phy_type == MII_DP83848_ID) {      /* National Semiconductor DP83848 PHY */
6323 +               read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
6324 +               dsintr = dsintr & ~0x3;                         /* clear bits 0, 1 */
6325 +               write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
6326 +               read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
6327 +               dsintr = dsintr & ~0x3c;                        /* clear bits 2..5 */
6328 +               write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
6329 +       }
6330
6331         disable_mdi();
6332         spin_unlock_irq(&lp->lock);
6333 @@ -535,8 +571,8 @@ static void at91ether_sethashtable(struc
6334                 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
6335         }
6336
6337 -       at91_emac_write(AT91_EMAC_HSH, mc_filter[0]);
6338 -       at91_emac_write(AT91_EMAC_HSL, mc_filter[1]);
6339 +       at91_emac_write(AT91_EMAC_HSL, mc_filter[0]);
6340 +       at91_emac_write(AT91_EMAC_HSH, mc_filter[1]);
6341  }
6342
6343  /*
6344 @@ -943,14 +979,22 @@ static int __init at91ether_setup(unsign
6345         struct net_device *dev;
6346         struct at91_private *lp;
6347         unsigned int val;
6348 -       int res;
6349 +       struct resource *res;
6350 +       int ret;
6351
6352         dev = alloc_etherdev(sizeof(struct at91_private));
6353         if (!dev)
6354                 return -ENOMEM;
6355
6356 -       dev->base_addr = AT91_VA_BASE_EMAC;
6357 -       dev->irq = AT91RM9200_ID_EMAC;
6358 +       /* Get I/O base address and IRQ */
6359 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6360 +       if (!res) {
6361 +               free_netdev(dev);
6362 +               return -ENODEV;
6363 +       }
6364 +       dev->base_addr = res->start;
6365 +       dev->irq = platform_get_irq(pdev, 0);
6366 +
6367         SET_MODULE_OWNER(dev);
6368
6369         /* Install the interrupt handler */
6370 @@ -1023,12 +1067,12 @@ static int __init at91ether_setup(unsign
6371         lp->phy_address = phy_address;  /* MDI address of PHY */
6372
6373         /* Register the network interface */
6374 -       res = register_netdev(dev);
6375 -       if (res) {
6376 +       ret = register_netdev(dev);
6377 +       if (ret) {
6378                 free_irq(dev->irq, dev);
6379                 free_netdev(dev);
6380                 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
6381 -               return res;
6382 +               return ret;
6383         }
6384
6385         /* Determine current link speed */
6386 @@ -1063,10 +1107,16 @@ static int __init at91ether_setup(unsign
6387                 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
6388         else if (phy_type == MII_DP83847_ID)
6389                 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
6390 +       else if (phy_type == MII_DP83848_ID)
6391 +               printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
6392         else if (phy_type == MII_AC101L_ID)
6393                 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
6394         else if (phy_type == MII_KS8721_ID)
6395                 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
6396 +       else if (phy_type == MII_T78Q21x3_ID)
6397 +               printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
6398 +       else if (phy_type == MII_LAN83C185_ID)
6399 +               printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
6400
6401         return 0;
6402  }
6403 @@ -1104,8 +1154,11 @@ static int __init at91ether_probe(struct
6404                         case MII_RTL8201_ID:            /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
6405                         case MII_BCM5221_ID:            /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
6406                         case MII_DP83847_ID:            /* National Semiconductor DP83847:  */
6407 +                       case MII_DP83848_ID:            /* National Semiconductor DP83848:  */
6408                         case MII_AC101L_ID:             /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
6409                         case MII_KS8721_ID:             /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
6410 +                       case MII_T78Q21x3_ID:           /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
6411 +                       case MII_LAN83C185_ID:          /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
6412                                 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
6413                                 break;
6414                 }
6415 Index: linux-2.6.21.7/drivers/net/arm/at91_ether.h
6416 ===================================================================
6417 --- linux-2.6.21.7.orig/drivers/net/arm/at91_ether.h
6418 +++ linux-2.6.21.7/drivers/net/arm/at91_ether.h
6419 @@ -17,39 +17,46 @@
6420
6421
6422  /* Davicom 9161 PHY */
6423 -#define MII_DM9161_ID  0x0181b880
6424 -#define MII_DM9161A_ID 0x0181b8a0
6425 -
6426 -/* Davicom specific registers */
6427 -#define MII_DSCR_REG   16
6428 -#define MII_DSCSR_REG  17
6429 -#define MII_DSINTR_REG 21
6430 +#define MII_DM9161_ID          0x0181b880
6431 +#define MII_DM9161A_ID         0x0181b8a0
6432 +#define MII_DSCR_REG           16
6433 +#define MII_DSCSR_REG          17
6434 +#define MII_DSINTR_REG         21
6435
6436  /* Intel LXT971A PHY */
6437 -#define MII_LXT971A_ID 0x001378E0
6438 -
6439 -/* Intel specific registers */
6440 -#define MII_ISINTE_REG 18
6441 -#define MII_ISINTS_REG 19
6442 -#define MII_LEDCTRL_REG        20
6443 +#define MII_LXT971A_ID         0x001378E0
6444 +#define MII_ISINTE_REG         18
6445 +#define MII_ISINTS_REG         19
6446 +#define MII_LEDCTRL_REG                20
6447
6448  /* Realtek RTL8201 PHY */
6449 -#define MII_RTL8201_ID 0x00008200
6450 +#define MII_RTL8201_ID         0x00008200
6451
6452  /* Broadcom BCM5221 PHY */
6453 -#define MII_BCM5221_ID 0x004061e0
6454 -
6455 -/* Broadcom specific registers */
6456 -#define MII_BCMINTR_REG        26
6457 +#define MII_BCM5221_ID         0x004061e0
6458 +#define MII_BCMINTR_REG                26
6459
6460  /* National Semiconductor DP83847 */
6461 -#define MII_DP83847_ID 0x20005c30
6462 +#define MII_DP83847_ID         0x20005c30
6463 +
6464 +/* National Semiconductor DP83848 */
6465 +#define MII_DP83848_ID         0x20005c90
6466 +#define MII_DPPHYSTS_REG       16
6467 +#define MII_DPMICR_REG         17
6468 +#define MII_DPMISR_REG         18
6469
6470  /* Altima AC101L PHY */
6471 -#define MII_AC101L_ID  0x00225520
6472 +#define MII_AC101L_ID          0x00225520
6473
6474  /* Micrel KS8721 PHY */
6475 -#define MII_KS8721_ID  0x00221610
6476 +#define MII_KS8721_ID          0x00221610
6477 +
6478 +/* Teridian 78Q2123/78Q2133 */
6479 +#define MII_T78Q21x3_ID                0x000e7230
6480 +#define MII_T78Q21INT_REG      17
6481 +
6482 +/* SMSC LAN83C185 */
6483 +#define MII_LAN83C185_ID       0x0007C0A0
6484
6485  /* ........................................................................ */
6486
6487 Index: linux-2.6.21.7/drivers/pcmcia/at91_cf.c
6488 ===================================================================
6489 --- linux-2.6.21.7.orig/drivers/pcmcia/at91_cf.c
6490 +++ linux-2.6.21.7/drivers/pcmcia/at91_cf.c
6491 @@ -332,20 +332,27 @@ static int at91_cf_suspend(struct platfo
6492         struct at91_cf_data     *board = cf->board;
6493
6494         pcmcia_socket_dev_suspend(&pdev->dev, mesg);
6495 +
6496         if (device_may_wakeup(&pdev->dev)) {
6497                 enable_irq_wake(board->det_pin);
6498                 if (board->irq_pin)
6499                         enable_irq_wake(board->irq_pin);
6500 -       } else {
6501 -               disable_irq_wake(board->det_pin);
6502 -               if (board->irq_pin)
6503 -                       disable_irq_wake(board->irq_pin);
6504         }
6505 +
6506         return 0;
6507  }
6508
6509  static int at91_cf_resume(struct platform_device *pdev)
6510  {
6511 +       struct at91_cf_socket   *cf = platform_get_drvdata(pdev);
6512 +       struct at91_cf_data     *board = cf->board;
6513 +
6514 +       if (device_may_wakeup(&pdev->dev)) {
6515 +               disable_irq_wake(board->det_pin);
6516 +               if (board->irq_pin)
6517 +                       disable_irq_wake(board->irq_pin);
6518 +       }
6519 +
6520         pcmcia_socket_dev_resume(&pdev->dev);
6521         return 0;
6522  }
6523 @@ -360,7 +367,6 @@ static struct platform_driver at91_cf_dr
6524                 .name           = (char *) driver_name,
6525                 .owner          = THIS_MODULE,
6526         },
6527 -       .probe          = at91_cf_probe,
6528         .remove         = __exit_p(at91_cf_remove),
6529         .suspend        = at91_cf_suspend,
6530         .resume         = at91_cf_resume,
6531 @@ -370,7 +376,7 @@ static struct platform_driver at91_cf_dr
6532
6533  static int __init at91_cf_init(void)
6534  {
6535 -       return platform_driver_register(&at91_cf_driver);
6536 +       return platform_driver_probe(&at91_cf_driver, at91_cf_probe);
6537  }
6538  module_init(at91_cf_init);
6539
6540 Index: linux-2.6.21.7/drivers/serial/atmel_serial.c
6541 ===================================================================
6542 --- linux-2.6.21.7.orig/drivers/serial/atmel_serial.c
6543 +++ linux-2.6.21.7/drivers/serial/atmel_serial.c
6544 @@ -7,6 +7,8 @@
6545   *  Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6546   *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6547   *
6548 + *  DMA support added by Chip Coldwell.
6549 + *
6550   * This program is free software; you can redistribute it and/or modify
6551   * it under the terms of the GNU General Public License as published by
6552   * the Free Software Foundation; either version 2 of the License, or
6553 @@ -33,6 +35,7 @@
6554  #include <linux/sysrq.h>
6555  #include <linux/tty_flip.h>
6556  #include <linux/platform_device.h>
6557 +#include <linux/dma-mapping.h>
6558  #include <linux/atmel_pdc.h>
6559
6560  #include <asm/io.h>
6561 @@ -47,6 +50,11 @@
6562
6563  #include "atmel_serial.h"
6564
6565 +#define SUPPORT_PDC
6566 +#define PDC_BUFFER_SIZE                (L1_CACHE_BYTES << 3)
6567 +#warning "Revisit"
6568 +#define PDC_RX_TIMEOUT         (3 * 10)                /* 3 bytes */
6569 +
6570  #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6571  #define SUPPORT_SYSRQ
6572  #endif
6573 @@ -107,6 +115,13 @@
6574  static int (*atmel_open_hook)(struct uart_port *);
6575  static void (*atmel_close_hook)(struct uart_port *);
6576
6577 +struct atmel_dma_buffer {
6578 +       unsigned char   *buf;
6579 +       dma_addr_t      dma_addr;
6580 +       size_t          dma_size;
6581 +       unsigned int    ofs;
6582 +};
6583 +
6584  /*
6585   * We wrap our port structure around the generic uart_port.
6586   */
6587 @@ -114,10 +129,20 @@ struct atmel_uart_port {
6588         struct uart_port        uart;           /* uart */
6589         struct clk              *clk;           /* uart clock */
6590         unsigned short          suspended;      /* is port suspended? */
6591 +
6592 +       short                   use_dma_rx;     /* enable PDC receiver */
6593 +       short                   pdc_rx_idx;     /* current PDC RX buffer */
6594 +       struct atmel_dma_buffer pdc_rx[2];      /* PDC receier */
6595 +
6596 +       short                   use_dma_tx;     /* enable PDC transmitter */
6597 +       struct atmel_dma_buffer pdc_tx;         /* PDC transmitter */
6598  };
6599
6600  static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
6601
6602 +#define PDC_RX_BUF(port)       &(port)->pdc_rx[(port)->pdc_rx_idx]
6603 +#define PDC_RX_SWITCH(port)    (port)->pdc_rx_idx = !(port)->pdc_rx_idx
6604 +
6605  #ifdef SUPPORT_SYSRQ
6606  static struct console atmel_console;
6607  #endif
6608 @@ -205,7 +230,12 @@ static void atmel_stop_tx(struct uart_po
6609  {
6610         struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6611
6612 -       UART_PUT_IDR(port, ATMEL_US_TXRDY);
6613 +       if (atmel_port->use_dma_tx) {
6614 +               UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);          /* disable PDC transmit */
6615 +               UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
6616 +       }
6617 +       else
6618 +               UART_PUT_IDR(port, ATMEL_US_TXRDY);
6619  }
6620
6621  /*
6622 @@ -215,7 +245,17 @@ static void atmel_start_tx(struct uart_p
6623  {
6624         struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6625
6626 -       UART_PUT_IER(port, ATMEL_US_TXRDY);
6627 +       if (atmel_port->use_dma_tx) {
6628 +               if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
6629 +                       /* The transmitter is already running.  Yes, we
6630 +                          really need this.*/
6631 +                       return;
6632 +
6633 +               UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
6634 +               UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);           /* re-enable PDC transmit */
6635 +       }
6636 +       else
6637 +               UART_PUT_IER(port, ATMEL_US_TXRDY);
6638  }
6639
6640  /*
6641 @@ -225,7 +265,12 @@ static void atmel_stop_rx(struct uart_po
6642  {
6643         struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6644
6645 -       UART_PUT_IDR(port, ATMEL_US_RXRDY);
6646 +       if (atmel_port->use_dma_rx) {
6647 +               UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);          /* disable PDC receive */
6648 +               UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
6649 +       }
6650 +       else
6651 +               UART_PUT_IDR(port, ATMEL_US_RXRDY);
6652  }
6653
6654  /*
6655 @@ -248,6 +293,134 @@ static void atmel_break_ctl(struct uart_
6656  }
6657
6658  /*
6659 + * Receive data via the PDC.  A buffer has been fulled.
6660 + */
6661 +static void atmel_pdc_endrx(struct uart_port *port)
6662 +{
6663 +       struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6664 +       struct tty_struct *tty = port->info->tty;
6665 +       struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port);
6666 +       unsigned int count;
6667 +
6668 +       count = pdc->dma_size - pdc->ofs;
6669 +       if (likely(count > 0)) {
6670 +               dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
6671 +               tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
6672 +               tty_flip_buffer_push(tty);
6673 +
6674 +               port->icount.rx += count;
6675 +       }
6676 +
6677 +       /* Set this buffer as the next receive buffer */
6678 +       pdc->ofs = 0;
6679 +       UART_PUT_RNPR(port, pdc->dma_addr);
6680 +       UART_PUT_RNCR(port, pdc->dma_size);
6681 +
6682 +       /* Switch to next buffer */
6683 +       PDC_RX_SWITCH(atmel_port);              /* next PDC buffer */
6684 +}
6685 +
6686 +/*
6687 + * Receive data via the PDC.  At least one byte was received, but the
6688 + * buffer was not full when the inter-character timeout expired.
6689 + */
6690 +static void atmel_pdc_timeout(struct uart_port *port)
6691 +{
6692 +       struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6693 +       struct tty_struct *tty = port->info->tty;
6694 +       struct atmel_dma_buffer *pdc = PDC_RX_BUF(atmel_port);
6695 +       /* unsigned */ int ofs, count;
6696 +
6697 +       ofs = UART_GET_RPR(port) - pdc->dma_addr;       /* current DMA adress */
6698 +       count = ofs - pdc->ofs;
6699 +
6700 +       if (likely(count > 0)) {
6701 +               dma_sync_single_for_cpu(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
6702 +               tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
6703 +               tty_flip_buffer_push(tty);
6704 +
6705 +               pdc->ofs = ofs;
6706 +               port->icount.rx += count;
6707 +       }
6708 +
6709 +       /* reset the UART timeout */
6710 +       UART_PUT_CR(port, ATMEL_US_STTTO);
6711 +}
6712 +
6713 +/*
6714 + * Deal with parity, framing and overrun errors.
6715 + */
6716 +static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
6717 +{
6718 +       /* clear error */
6719 +       UART_PUT_CR(port, ATMEL_US_RSTSTA);
6720 +
6721 +       if (status & ATMEL_US_RXBRK) {
6722 +               status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);    /* ignore side-effect */
6723 +               port->icount.brk++;
6724 +       }
6725 +       if (status & ATMEL_US_PARE)
6726 +               port->icount.parity++;
6727 +       if (status & ATMEL_US_FRAME)
6728 +               port->icount.frame++;
6729 +       if (status & ATMEL_US_OVRE)
6730 +               port->icount.overrun++;
6731 +}
6732 +
6733 +/*
6734 + * A transmission via the PDC is complete.
6735 + */
6736 +static void atmel_pdc_endtx(struct uart_port *port)
6737 +{
6738 +       struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6739 +       struct circ_buf *xmit = &port->info->xmit;
6740 +       struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
6741 +
6742 +       xmit->tail += pdc->ofs;
6743 +       if (xmit->tail >= SERIAL_XMIT_SIZE)
6744 +               xmit->tail -= SERIAL_XMIT_SIZE;
6745 +
6746 +       port->icount.tx += pdc->ofs;
6747 +       pdc->ofs = 0;
6748 +
6749 +       if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
6750 +               uart_write_wakeup(port);
6751 +}
6752 +
6753 +/*
6754 + * The PDC transmitter is idle, so either start the next transfer or
6755 + * disable the transmitter.
6756 + */
6757 +static void atmel_pdc_txbufe(struct uart_port *port)
6758 +{
6759 +       struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6760 +       struct circ_buf *xmit = &port->info->xmit;
6761 +       struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
6762 +       int count;
6763 +
6764 +       if (!uart_circ_empty(xmit)) {
6765 +               /* more to transmit - setup next transfer */
6766 +               UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);                  /* disable PDC transmit */
6767 +               dma_sync_single_for_device(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE);
6768 +
6769 +               if (xmit->tail < xmit->head)
6770 +                       count = xmit->head - xmit->tail;
6771 +               else
6772 +                       count = SERIAL_XMIT_SIZE - xmit->tail;
6773 +               pdc->ofs = count;
6774 +
6775 +               UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
6776 +               UART_PUT_TCR(port, count);
6777 +               UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);                   /* re-enable PDC transmit */
6778 +       }
6779 +       else {
6780 +               /* nothing left to transmit - disable the transmitter */
6781 +               UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);                  /* disable PDC transmit */
6782 +               UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
6783 +       }
6784 +}
6785 +
6786 +/*
6787   * Characters received (called from interrupt handler)
6788   */
6789  static void atmel_rx_chars(struct uart_port *port)
6790 @@ -349,6 +522,14 @@ static irqreturn_t atmel_interrupt(int i
6791         status = UART_GET_CSR(port);
6792         pending = status & UART_GET_IMR(port);
6793         while (pending) {
6794 +               /* PDC receive */
6795 +               if (pending & ATMEL_US_ENDRX)
6796 +                       atmel_pdc_endrx(port);
6797 +               if (pending & ATMEL_US_TIMEOUT)
6798 +                       atmel_pdc_timeout(port);
6799 +               if (atmel_port->use_dma_rx && pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | ATMEL_US_FRAME | ATMEL_US_PARE))
6800 +                       atmel_pdc_rxerr(port, pending);
6801 +
6802                 /* Interrupt receive */
6803                 if (pending & ATMEL_US_RXRDY)
6804                         atmel_rx_chars(port);
6805 @@ -363,6 +544,12 @@ static irqreturn_t atmel_interrupt(int i
6806                 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC))
6807                         wake_up_interruptible(&port->info->delta_msr_wait);
6808
6809 +               /* PDC transmit */
6810 +               if (pending & ATMEL_US_ENDTX)
6811 +                       atmel_pdc_endtx(port);
6812 +               if (pending & ATMEL_US_TXBUFE)
6813 +                       atmel_pdc_txbufe(port);
6814 +
6815                 /* Interrupt transmit */
6816                 if (pending & ATMEL_US_TXRDY)
6817                         atmel_tx_chars(port);
6818 @@ -401,6 +588,47 @@ static int atmel_startup(struct uart_por
6819         }
6820
6821         /*
6822 +        * Initialize DMA (if necessary)
6823 +        */
6824 +       if (atmel_port->use_dma_rx) {
6825 +               int i;
6826 +
6827 +               for (i = 0; i < 2; i++) {
6828 +                       struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
6829 +
6830 +                       pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
6831 +                       if (pdc->buf == NULL) {
6832 +                               if (i != 0) {
6833 +                                       dma_unmap_single(port->dev, atmel_port->pdc_rx[0].dma_addr, PDC_BUFFER_SIZE, DMA_FROM_DEVICE);
6834 +                                       kfree(atmel_port->pdc_rx[0].buf);
6835 +                               }
6836 +                               free_irq(port->irq, port);
6837 +                               return -ENOMEM;
6838 +                       }
6839 +                       pdc->dma_addr = dma_map_single(port->dev, pdc->buf, PDC_BUFFER_SIZE, DMA_FROM_DEVICE);
6840 +                       pdc->dma_size = PDC_BUFFER_SIZE;
6841 +                       pdc->ofs = 0;
6842 +               }
6843 +
6844 +               atmel_port->pdc_rx_idx = 0;
6845 +
6846 +               UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
6847 +               UART_PUT_RCR(port, PDC_BUFFER_SIZE);
6848 +
6849 +               UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
6850 +               UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
6851 +       }
6852 +       if (atmel_port->use_dma_tx) {
6853 +               struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
6854 +               struct circ_buf *xmit = &port->info->xmit;
6855 +
6856 +               pdc->buf = xmit->buf;
6857 +               pdc->dma_addr = dma_map_single(port->dev, pdc->buf, SERIAL_XMIT_SIZE, DMA_TO_DEVICE);
6858 +               pdc->dma_size = SERIAL_XMIT_SIZE;
6859 +               pdc->ofs = 0;
6860 +       }
6861 +
6862 +       /*
6863          * If there is a specific "open" function (to register
6864          * control line interrupts)
6865          */
6866 @@ -418,7 +646,15 @@ static int atmel_startup(struct uart_por
6867         UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
6868         UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);               /* enable xmit & rcvr */
6869
6870 -       UART_PUT_IER(port, ATMEL_US_RXRDY);             /* enable receive only */
6871 +       if (atmel_port->use_dma_rx) {
6872 +               UART_PUT_RTOR(port, PDC_RX_TIMEOUT);            /* set UART timeout */
6873 +               UART_PUT_CR(port, ATMEL_US_STTTO);
6874 +
6875 +               UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
6876 +               UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);           /* enable PDC controller */
6877 +       }
6878 +       else
6879 +               UART_PUT_IER(port, ATMEL_US_RXRDY);             /* enable receive only */
6880
6881         return 0;
6882  }
6883 @@ -431,6 +667,31 @@ static void atmel_shutdown(struct uart_p
6884         struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6885
6886         /*
6887 +        * Ensure everything is stopped.
6888 +        */
6889 +       atmel_stop_rx(port);
6890 +       atmel_stop_tx(port);
6891 +
6892 +       /*
6893 +        * Shut-down the DMA.
6894 +        */
6895 +       if (atmel_port->use_dma_rx) {
6896 +               int i;
6897 +
6898 +               for (i = 0; i < 2; i++) {
6899 +                       struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
6900 +
6901 +                       dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_FROM_DEVICE);
6902 +                       kfree(pdc->buf);
6903 +               }
6904 +       }
6905 +       if (atmel_port->use_dma_tx) {
6906 +               struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
6907 +
6908 +               dma_unmap_single(port->dev, pdc->dma_addr, pdc->dma_size, DMA_TO_DEVICE);
6909 +       }
6910 +
6911 +       /*
6912          * Disable all interrupts, port and break condition.
6913          */
6914         UART_PUT_CR(port, ATMEL_US_RSTSTA);
6915 @@ -481,14 +742,20 @@ static void atmel_serial_pm(struct uart_
6916   */
6917  static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, struct ktermios * old)
6918  {
6919 +       struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6920         unsigned long flags;
6921         unsigned int mode, imr, quot, baud;
6922
6923 +       /* Get current mode register */
6924 +       mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
6925 +
6926         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
6927         quot = uart_get_divisor(port, baud);
6928
6929 -       /* Get current mode register */
6930 -       mode = UART_GET_MR(port) & ~(ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
6931 +       if (quot > 65535) {     /* BRGR is 16-bit, so switch to slower clock */
6932 +               quot /= 8;
6933 +               mode |= ATMEL_US_USCLKS_MCK_DIV8;
6934 +       }
6935
6936         /* byte size */
6937         switch (termios->c_cflag & CSIZE) {
6938 @@ -534,6 +801,9 @@ static void atmel_set_termios(struct uar
6939         if (termios->c_iflag & (BRKINT | PARMRK))
6940                 port->read_status_mask |= ATMEL_US_RXBRK;
6941
6942 +       if (atmel_port->use_dma_rx)     /* need to enable error interrupts */
6943 +               UART_PUT_IER(port, port->read_status_mask);
6944 +
6945         /*
6946          * Characters to ignore
6947          */
6948 @@ -712,6 +982,13 @@ static void __devinit atmel_init_port(st
6949                 clk_enable(atmel_port->clk);
6950                 port->uartclk = clk_get_rate(atmel_port->clk);
6951         }
6952 +
6953 +#ifdef SUPPORT_PDC
6954 +       atmel_port->use_dma_rx = data->use_dma_rx;
6955 +       atmel_port->use_dma_tx = data->use_dma_tx;
6956 +       if (atmel_port->use_dma_tx)
6957 +               port->fifosize = PDC_BUFFER_SIZE;
6958 +#endif
6959  }
6960
6961  /*
6962 @@ -888,7 +1165,8 @@ static int atmel_serial_suspend(struct p
6963         struct uart_port *port = platform_get_drvdata(pdev);
6964         struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
6965
6966 -       if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock())
6967 +       if (device_may_wakeup(&pdev->dev)
6968 +                       && !clk_must_disable(atmel_port->clk))
6969                 enable_irq_wake(port->irq);
6970         else {
6971                 uart_suspend_port(&atmel_uart, port);
6972 Index: linux-2.6.21.7/drivers/serial/atmel_serial.h
6973 ===================================================================
6974 --- linux-2.6.21.7.orig/drivers/serial/atmel_serial.h
6975 +++ linux-2.6.21.7/drivers/serial/atmel_serial.h
6976 @@ -46,6 +46,9 @@
6977  #define                        ATMEL_US_USMODE_ISO7816_T1      6
6978  #define                        ATMEL_US_USMODE_IRDA            8
6979  #define                ATMEL_US_USCLKS         (3   <<  4)             /* Clock Selection */
6980 +#define                        ATMEL_US_USCLKS_MCK             (0 <<  4)
6981 +#define                        ATMEL_US_USCLKS_MCK_DIV8        (1 <<  4)
6982 +#define                        ATMEL_US_USCLKS_SCK             (3 <<  4)
6983  #define                ATMEL_US_CHRL           (3   <<  6)             /* Character Length */
6984  #define                        ATMEL_US_CHRL_5                 (0 <<  6)
6985  #define                        ATMEL_US_CHRL_6                 (1 <<  6)
6986 Index: linux-2.6.21.7/drivers/spi/Kconfig
6987 ===================================================================
6988 --- linux-2.6.21.7.orig/drivers/spi/Kconfig
6989 +++ linux-2.6.21.7/drivers/spi/Kconfig
6990 @@ -54,6 +54,7 @@ comment "SPI Master Controller Drivers"
6991  config SPI_ATMEL
6992         tristate "Atmel SPI Controller"
6993         depends on (ARCH_AT91 || AVR32) && SPI_MASTER
6994 +       select SPI_AT91_MANUAL_CS if ARCH_AT91RM9200
6995         help
6996           This selects a driver for the Atmel SPI Controller, present on
6997           many AT32 (AVR32) and AT91 (ARM) chips.
6998 @@ -82,6 +83,24 @@ config SPI_BUTTERFLY
6999           inexpensive battery powered microcontroller evaluation board.
7000           This same cable can be used to flash new firmware.
7001
7002 +config SPI_AT91
7003 +       tristate "AT91RM9200 Bitbang SPI Master"
7004 +       depends on SPI_MASTER && ARCH_AT91RM9200 && !SPI_ATMEL && EXPERIMENTAL
7005 +       select SPI_BITBANG
7006 +       select SPI_AT91_MANUAL_CS
7007 +       help
7008 +         This is dumb PIO bitbanging driver for the Atmel AT91RM9200.
7009 +         The SPI_ATMEL driver will be its replacement, using the native
7010 +         SPI hardware and its DMA controller.
7011 +
7012 +config SPI_AT91_MANUAL_CS
7013 +       bool
7014 +       depends on ARCH_AT91RM9200
7015 +       help
7016 +         Works around an AT91RM9200 problem whereby the SPI chip-select
7017 +         will be wrongly disabled.  The workaround uses those pins as
7018 +         GPIOs instead of letting the SPI controller manage them.
7019 +
7020  config SPI_IMX
7021         tristate "Freescale iMX SPI controller"
7022         depends on SPI_MASTER && ARCH_IMX && EXPERIMENTAL
7023 Index: linux-2.6.21.7/drivers/spi/Makefile
7024 ===================================================================
7025 --- linux-2.6.21.7.orig/drivers/spi/Makefile
7026 +++ linux-2.6.21.7/drivers/spi/Makefile
7027 @@ -20,6 +20,7 @@ obj-$(CONFIG_SPI_OMAP_UWIRE)          += omap_uw
7028  obj-$(CONFIG_SPI_MPC83xx)              += spi_mpc83xx.o
7029  obj-$(CONFIG_SPI_S3C24XX_GPIO)         += spi_s3c24xx_gpio.o
7030  obj-$(CONFIG_SPI_S3C24XX)              += spi_s3c24xx.o
7031 +obj-$(CONFIG_SPI_AT91)                 += spi_at91_bitbang.o
7032  #      ... add above this line ...
7033
7034  # SPI protocol drivers (device/link on bus)
7035 Index: linux-2.6.21.7/drivers/spi/spi_at91_bitbang.c
7036 ===================================================================
7037 --- /dev/null
7038 +++ linux-2.6.21.7/drivers/spi/spi_at91_bitbang.c
7039 @@ -0,0 +1,207 @@
7040 +/*
7041 + * at91_spi.c - at91 SPI driver (BOOTSTRAP/BITBANG VERSION)
7042 + *
7043 + * Copyright (C) 2006 David Brownell
7044 + *
7045 + * This program is free software; you can redistribute it and/or modify
7046 + * it under the terms of the GNU General Public License as published by
7047 + * the Free Software Foundation; either version 2 of the License, or
7048 + * (at your option) any later version.
7049 + *
7050 + * This program is distributed in the hope that it will be useful,
7051 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7052 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
7053 + * GNU General Public License for more details.
7054 + *
7055 + * You should have received a copy of the GNU General Public License
7056 + * along with this program; if not, write to the Free Software
7057 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
7058 + */
7059 +#include <linux/kernel.h>
7060 +#include <linux/init.h>
7061 +#include <linux/platform_device.h>
7062 +
7063 +#include <linux/spi/spi.h>
7064 +#include <linux/spi/spi_bitbang.h>
7065 +
7066 +#include <asm/arch/gpio.h>
7067 +
7068 +
7069 +/*
7070 + * FIXME this bitbanging version is just to help bootstrap systems until
7071 + * there's a native SPI+IRQ+DMA controller driver ... such a driver should
7072 + * be a drop-in replacement for this one, and much faster.
7073 + *
7074 + * remember:
7075 + *
7076 + *     - other at91 parts (like at91sam9) have multiple controllers
7077 + *       and different pin muxing; this version is at91rm9200 specfic.
7078 + *
7079 + *     - at91sam9261 SPI0 pins are directly muxed with MMC/SD pins.
7080 + *
7081 + *     - rm9200 spi chipselects drop wrongly, so the native driver
7082 + *       will need to use gpios much like this does.
7083 + *
7084 + *     - real hardware only allows 8..16 bits per word, while this
7085 + *       bitbanger allows 1..32 (incompatible superset).
7086 + *
7087 + *     - this disregards clock parameters.  with inlined gpio calls,
7088 + *       gcc 3.4.4 produces about 1.5 mbit/sec, more than 2x faster
7089 + *       than using the subroutined veresion from txrx_word().
7090 + *
7091 + *     - suspend/resume and <linux/clk.h> support is missing ...
7092 + */
7093 +
7094 +#define        spi_miso_bit    AT91_PIN_PA0
7095 +#define        spi_mosi_bit    AT91_PIN_PA1
7096 +#define        spi_sck_bit     AT91_PIN_PA2
7097 +
7098 +struct at91_spi {
7099 +       struct spi_bitbang      bitbang;
7100 +       struct platform_device  *pdev;
7101 +};
7102 +
7103 +/*----------------------------------------------------------------------*/
7104 +
7105 +static inline void setsck(struct spi_device *spi, int is_on)
7106 +{
7107 +       at91_set_gpio_value(spi_sck_bit, is_on);
7108 +}
7109 +
7110 +static inline void setmosi(struct spi_device *spi, int is_on)
7111 +{
7112 +       at91_set_gpio_value(spi_mosi_bit, is_on);
7113 +}
7114 +
7115 +static inline int getmiso(struct spi_device *spi)
7116 +{
7117 +       return at91_get_gpio_value(spi_miso_bit);
7118 +}
7119 +
7120 +static void at91_spi_chipselect(struct spi_device *spi, int is_active)
7121 +{
7122 +       unsigned long cs = (unsigned long) spi->controller_data;
7123 +
7124 +       /* set default clock polarity */
7125 +       if (is_active)
7126 +               setsck(spi, spi->mode & SPI_CPOL);
7127 +
7128 +       /* only support active-low (default) */
7129 +       at91_set_gpio_value(cs, !is_active);
7130 +}
7131 +
7132 +/*
7133 + * NOTE:  this is "as fast as we can"; it should be a function of
7134 + * the device clock ...
7135 + */
7136 +#define        spidelay(X)     do{} while(0)
7137 +
7138 +#define        EXPAND_BITBANG_TXRX
7139 +#include <linux/spi/spi_bitbang.h>
7140 +
7141 +static u32 at91_spi_txrx_word_mode0(struct spi_device *spi,
7142 +               unsigned nsecs, u32 word, u8 bits)
7143 +{
7144 +       return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, 8);
7145 +}
7146 +
7147 +static u32 at91_spi_txrx_word_mode1(struct spi_device *spi,
7148 +               unsigned nsecs, u32 word, u8 bits)
7149 +{
7150 +       return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, 8);
7151 +}
7152 +
7153 +static u32 at91_spi_txrx_word_mode2(struct spi_device *spi,
7154 +               unsigned nsecs, u32 word, u8 bits)
7155 +{
7156 +       return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, 8);
7157 +}
7158 +
7159 +static u32 at91_spi_txrx_word_mode3(struct spi_device *spi,
7160 +               unsigned nsecs, u32 word, u8 bits)
7161 +{
7162 +       return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, 8);
7163 +}
7164 +
7165 +/*----------------------------------------------------------------------*/
7166 +
7167 +static int __init at91_spi_probe(struct platform_device *pdev)
7168 +{
7169 +       int                     status;
7170 +       struct spi_master       *master;
7171 +       struct at91_spi         *at91_spi;
7172 +
7173 +       if (pdev->id != 0)      /* SPI0 bus */
7174 +               return -EINVAL;
7175 +
7176 +       master = spi_alloc_master(&pdev->dev, sizeof *at91_spi);
7177 +       if (!master)
7178 +               return -ENOMEM;
7179 +
7180 +       at91_spi = spi_master_get_devdata(master);
7181 +       at91_spi->pdev = pdev;
7182 +       platform_set_drvdata(pdev, at91_spi);
7183 +
7184 +       /* SPI and bitbang hookup */
7185 +       master->bus_num = 0;
7186 +       master->num_chipselect = 4;
7187 +
7188 +       at91_spi->bitbang.master = spi_master_get(master);
7189 +       at91_spi->bitbang.chipselect = at91_spi_chipselect;
7190 +       at91_spi->bitbang.txrx_word[SPI_MODE_0] = at91_spi_txrx_word_mode0;
7191 +       at91_spi->bitbang.txrx_word[SPI_MODE_1] = at91_spi_txrx_word_mode1;
7192 +       at91_spi->bitbang.txrx_word[SPI_MODE_2] = at91_spi_txrx_word_mode2;
7193 +       at91_spi->bitbang.txrx_word[SPI_MODE_3] = at91_spi_txrx_word_mode3;
7194 +
7195 +       status = spi_bitbang_start(&at91_spi->bitbang);
7196 +       if (status < 0)
7197 +               (void) spi_master_put(at91_spi->bitbang.master);
7198 +
7199 +       return status;
7200 +}
7201 +
7202 +static int __exit at91_spi_remove(struct platform_device *pdev)
7203 +{
7204 +       struct at91_spi *at91_spi = platform_get_drvdata(pdev);
7205 +       int status;
7206 +
7207 +       /* stop() unregisters child devices too */
7208 +       status = spi_bitbang_stop(&at91_spi->bitbang);
7209 +       (void) spi_master_put(at91_spi->bitbang.master);
7210 +
7211 +       platform_set_drvdata(pdev, NULL);
7212 +       return status;
7213 +}
7214 +
7215 +static struct platform_driver at91_spi_driver = {
7216 +       .probe          = at91_spi_probe,
7217 +       .remove         = __exit_p(at91_spi_remove),
7218 +       .driver         = {
7219 +               .name   = "at91_spi",
7220 +               .owner  = THIS_MODULE,
7221 +       },
7222 +};
7223 +
7224 +static int __init at91_spi_init(void)
7225 +{
7226 +       at91_set_gpio_output(spi_sck_bit, 0);
7227 +       at91_set_gpio_output(spi_mosi_bit, 0);
7228 +       at91_set_gpio_input(spi_miso_bit, 1 /* pullup */);
7229 +
7230 +       /* register driver */
7231 +       return platform_driver_register(&at91_spi_driver);
7232 +}
7233 +
7234 +static void __exit at91_spi_exit(void)
7235 +{
7236 +       platform_driver_unregister(&at91_spi_driver);
7237 +}
7238 +
7239 +device_initcall(at91_spi_init);
7240 +module_exit(at91_spi_exit);
7241 +
7242 +MODULE_ALIAS("at91_spi.0");
7243 +
7244 +MODULE_DESCRIPTION("AT91 SPI support (BOOTSTRAP/BITBANG VERSION)");
7245 +MODULE_AUTHOR("David Brownell");
7246 +MODULE_LICENSE("GPL");
7247 Index: linux-2.6.21.7/drivers/usb/gadget/Kconfig
7248 ===================================================================
7249 --- linux-2.6.21.7.orig/drivers/usb/gadget/Kconfig
7250 +++ linux-2.6.21.7/drivers/usb/gadget/Kconfig
7251 @@ -189,7 +189,7 @@ config USB_OTG
7252
7253  config USB_GADGET_AT91
7254         boolean "AT91 USB Device Port"
7255 -       depends on ARCH_AT91
7256 +       depends on ARCH_AT91 && !ARCH_AT91SAM9RL
7257         select USB_GADGET_SELECTED
7258         help
7259            Many Atmel AT91 processors (such as the AT91RM2000) have a
7260 Index: linux-2.6.21.7/drivers/usb/gadget/at91_udc.c
7261 ===================================================================
7262 --- linux-2.6.21.7.orig/drivers/usb/gadget/at91_udc.c
7263 +++ linux-2.6.21.7/drivers/usb/gadget/at91_udc.c
7264 @@ -1804,7 +1804,7 @@ static int at91udc_suspend(struct platfo
7265          */
7266         if ((!udc->suspended && udc->addr)
7267                         || !wake
7268 -                       || at91_suspend_entering_slow_clock()) {
7269 +                       || clk_must_disable(udc->fclk)) {
7270                 pullup(udc, 0);
7271                 wake = 0;
7272         } else
7273 Index: linux-2.6.21.7/drivers/usb/host/ohci-at91.c
7274 ===================================================================
7275 --- linux-2.6.21.7.orig/drivers/usb/host/ohci-at91.c
7276 +++ linux-2.6.21.7/drivers/usb/host/ohci-at91.c
7277 @@ -299,7 +299,7 @@ ohci_hcd_at91_drv_suspend(struct platfor
7278          *
7279          * REVISIT: some boards will be able to turn VBUS off...
7280          */
7281 -       if (at91_suspend_entering_slow_clock()) {
7282 +       if (clk_must_disable(fclk)) {
7283                 ohci_usb_reset (ohci);
7284                 at91_stop_clock();
7285         }
7286 Index: linux-2.6.21.7/drivers/video/Kconfig
7287 ===================================================================
7288 --- linux-2.6.21.7.orig/drivers/video/Kconfig
7289 +++ linux-2.6.21.7/drivers/video/Kconfig
7290 @@ -663,6 +663,17 @@ config FB_EPSON1355
7291           framebuffer.  Product specs at
7292           <http://www.erd.epson.com/vdc/html/products.htm>.
7293
7294 +config FB_S1D15605
7295 +       tristate "Epson S1D15605 framebuffer support"
7296 +       depends on FB
7297 +       default m if MACH_KB9200
7298 +       select FB_CFB_FILLRECT
7299 +       select FB_CFB_COPYAREA
7300 +       select FB_CFB_IMAGEBLIT
7301 +       help
7302 +         Build in support for the S1D15605 Epson Research 128x64
7303 +         LCD controller as a framebuffer.
7304 +
7305  config FB_S1D13XXX
7306         tristate "Epson S1D13XXX framebuffer support"
7307         depends on FB
7308 @@ -674,6 +685,22 @@ config FB_S1D13XXX
7309           working with S1D13806). Product specs at
7310           <http://www.erd.epson.com/vdc/html/legacy_13xxx.htm>
7311
7312 +config FB_ATMEL
7313 +       tristate "AT91/AT32 LCD Controller support"
7314 +       depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || AVR32)
7315 +       select FB_CFB_FILLRECT
7316 +       select FB_CFB_COPYAREA
7317 +       select FB_CFB_IMAGEBLIT
7318 +       help
7319 +         This enables support for the AT91/AT32 LCD Controller.
7320 +
7321 +config FB_INTSRAM
7322 +       bool "Frame Buffer in internal SRAM"
7323 +       depends on FB_ATMEL && ARCH_AT91SAM9261
7324 +       help
7325 +         Say Y if you want to map Frame Buffer in internal SRAM. Say N if you want
7326 +         to let frame buffer in external SDRAM.
7327 +
7328  config FB_NVIDIA
7329         tristate "nVidia Framebuffer Support"
7330         depends on FB && PCI
7331 Index: linux-2.6.21.7/drivers/video/Makefile
7332 ===================================================================
7333 --- linux-2.6.21.7.orig/drivers/video/Makefile
7334 +++ linux-2.6.21.7/drivers/video/Makefile
7335 @@ -75,6 +75,8 @@ obj-$(CONFIG_FB_G364)             += g36
7336  obj-$(CONFIG_FB_SA1100)           += sa1100fb.o
7337  obj-$(CONFIG_FB_HIT)              += hitfb.o
7338  obj-$(CONFIG_FB_EPSON1355)       += epson1355fb.o
7339 +obj-$(CONFIG_FB_S1D15605)        += s1d15605fb.o
7340 +obj-$(CONFIG_FB_ATMEL)            += atmel_lcdfb.o
7341  obj-$(CONFIG_FB_PVR2)             += pvr2fb.o
7342  obj-$(CONFIG_FB_VOODOO1)          += sstfb.o
7343  obj-$(CONFIG_FB_ARMCLCD)         += amba-clcd.o
7344 Index: linux-2.6.21.7/drivers/video/atmel_lcdfb.c
7345 ===================================================================
7346 --- /dev/null
7347 +++ linux-2.6.21.7/drivers/video/atmel_lcdfb.c
7348 @@ -0,0 +1,752 @@
7349 +/*
7350 + *  Driver for AT91/AT32 LCD Controller
7351 + *
7352 + *  Copyright (C) 2007 Atmel Corporation
7353 + *
7354 + * This file is subject to the terms and conditions of the GNU General Public
7355 + * License.  See the file COPYING in the main directory of this archive for
7356 + * more details.
7357 + */
7358 +
7359 +#include <linux/kernel.h>
7360 +#include <linux/platform_device.h>
7361 +#include <linux/dma-mapping.h>
7362 +#include <linux/interrupt.h>
7363 +#include <linux/clk.h>
7364 +#include <linux/fb.h>
7365 +#include <linux/init.h>
7366 +#include <linux/delay.h>
7367 +
7368 +#include <asm/arch/board.h>
7369 +#include <asm/arch/cpu.h>
7370 +#include <asm/arch/gpio.h>
7371 +
7372 +#include <video/atmel_lcdc.h>
7373 +
7374 +#define lcdc_readl(sinfo, reg)         __raw_readl((sinfo)->mmio+(reg))
7375 +#define lcdc_writel(sinfo, reg, val)   __raw_writel((val), (sinfo)->mmio+(reg))
7376 +
7377 +/* configurable parameters */
7378 +#define ATMEL_LCDC_CVAL_DEFAULT                0xc8
7379 +#define ATMEL_LCDC_DMA_BURST_LEN       8
7380 +
7381 +#if defined(CONFIG_ARCH_AT91SAM9263)
7382 +#define ATMEL_LCDC_FIFO_SIZE           2048
7383 +#else
7384 +#define ATMEL_LCDC_FIFO_SIZE           512
7385 +#endif
7386 +
7387 +#if defined(CONFIG_ARCH_AT91)
7388 +#define        ATMEL_LCDFB_FBINFO_DEFAULT      FBINFO_DEFAULT
7389 +
7390 +static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
7391 +                                       struct fb_var_screeninfo *var)
7392 +{
7393 +
7394 +}
7395 +#elif defined(CONFIG_AVR32)
7396 +#define        ATMEL_LCDFB_FBINFO_DEFAULT      (FBINFO_DEFAULT \
7397 +                                       | FBINFO_PARTIAL_PAN_OK \
7398 +                                       | FBINFO_HWACCEL_XPAN \
7399 +                                       | FBINFO_HWACCEL_YPAN)
7400 +
7401 +static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
7402 +                                    struct fb_var_screeninfo *var)
7403 +{
7404 +       u32 dma2dcfg;
7405 +       u32 pixeloff;
7406 +
7407 +       pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f;
7408 +
7409 +       dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8;
7410 +       dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
7411 +       lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
7412 +
7413 +       /* Update configuration */
7414 +       lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
7415 +                   lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
7416 +                   | ATMEL_LCDC_DMAUPDT);
7417 +}
7418 +#endif
7419 +
7420 +
7421 +static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
7422 +       .type           = FB_TYPE_PACKED_PIXELS,
7423 +       .visual         = FB_VISUAL_TRUECOLOR,
7424 +       .xpanstep       = 0,
7425 +       .ypanstep       = 0,
7426 +       .ywrapstep      = 0,
7427 +       .accel          = FB_ACCEL_NONE,
7428 +};
7429 +
7430 +
7431 +static void atmel_lcdfb_update_dma(struct fb_info *info,
7432 +                              struct fb_var_screeninfo *var)
7433 +{
7434 +       struct atmel_lcdfb_info *sinfo = info->par;
7435 +       struct fb_fix_screeninfo *fix = &info->fix;
7436 +       unsigned long dma_addr;
7437 +
7438 +       dma_addr = (fix->smem_start + var->yoffset * fix->line_length
7439 +                   + var->xoffset * var->bits_per_pixel / 8);
7440 +
7441 +       dma_addr &= ~3UL;
7442 +
7443 +       /* Set framebuffer DMA base address and pixel offset */
7444 +       lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
7445 +
7446 +       atmel_lcdfb_update_dma2d(sinfo, var);
7447 +}
7448 +
7449 +static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
7450 +{
7451 +       struct fb_info *info = sinfo->info;
7452 +
7453 +       dma_free_writecombine(info->device, info->fix.smem_len,
7454 +                               info->screen_base, info->fix.smem_start);
7455 +}
7456 +
7457 +/**
7458 + *     atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
7459 + *     @sinfo: the frame buffer to allocate memory for
7460 + */
7461 +static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
7462 +{
7463 +       struct fb_info *info = sinfo->info;
7464 +       struct fb_var_screeninfo *var = &info->var;
7465 +
7466 +       info->fix.smem_len = (var->xres_virtual * var->yres_virtual
7467 +                           * ((var->bits_per_pixel + 7) / 8));
7468 +
7469 +       info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len,
7470 +                                       (dma_addr_t *)&info->fix.smem_start, GFP_KERNEL);
7471 +
7472 +       if (!info->screen_base) {
7473 +               return -ENOMEM;
7474 +       }
7475 +
7476 +       return 0;
7477 +}
7478 +
7479 +/**
7480 + *      atmel_lcdfb_check_var - Validates a var passed in.
7481 + *      @var: frame buffer variable screen structure
7482 + *      @info: frame buffer structure that represents a single frame buffer
7483 + *
7484 + *     Checks to see if the hardware supports the state requested by
7485 + *     var passed in. This function does not alter the hardware
7486 + *     state!!!  This means the data stored in struct fb_info and
7487 + *     struct atmel_lcdfb_info do not change. This includes the var
7488 + *     inside of struct fb_info.  Do NOT change these. This function
7489 + *     can be called on its own if we intent to only test a mode and
7490 + *     not actually set it. The stuff in modedb.c is a example of
7491 + *     this. If the var passed in is slightly off by what the
7492 + *     hardware can support then we alter the var PASSED in to what
7493 + *     we can do. If the hardware doesn't support mode change a
7494 + *     -EINVAL will be returned by the upper layers. You don't need
7495 + *     to implement this function then. If you hardware doesn't
7496 + *     support changing the resolution then this function is not
7497 + *     needed. In this case the driver would just provide a var that
7498 + *     represents the static state the screen is in.
7499 + *
7500 + *     Returns negative errno on error, or zero on success.
7501 + */
7502 +static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
7503 +                            struct fb_info *info)
7504 +{
7505 +       struct device *dev = info->device;
7506 +       struct atmel_lcdfb_info *sinfo = info->par;
7507 +       unsigned long clk_value_khz;
7508 +
7509 +       clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
7510 +
7511 +       dev_dbg(dev, "%s:\n", __func__);
7512 +       dev_dbg(dev, "  resolution: %ux%u\n", var->xres, var->yres);
7513 +       dev_dbg(dev, "  pixclk:     %lu KHz\n", PICOS2KHZ(var->pixclock));
7514 +       dev_dbg(dev, "  bpp:        %u\n", var->bits_per_pixel);
7515 +       dev_dbg(dev, "  clk:        %lu KHz\n", clk_value_khz);
7516 +
7517 +       if ((PICOS2KHZ(var->pixclock) * var->bits_per_pixel / 8) > clk_value_khz) {
7518 +               dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
7519 +               return -EINVAL;
7520 +       }
7521 +
7522 +       /* Force same alignment for each line */
7523 +       var->xres = (var->xres + 3) & ~3UL;
7524 +       var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
7525 +
7526 +       var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
7527 +       var->transp.msb_right = 0;
7528 +       var->transp.offset = var->transp.length = 0;
7529 +       var->xoffset = var->yoffset = 0;
7530 +
7531 +       switch (var->bits_per_pixel) {
7532 +       case 2:
7533 +       case 4:
7534 +       case 8:
7535 +               var->red.offset = var->green.offset = var->blue.offset = 0;
7536 +               var->red.length = var->green.length = var->blue.length
7537 +                       = var->bits_per_pixel;
7538 +               break;
7539 +       case 15:
7540 +       case 16:
7541 +               var->red.offset = 0;
7542 +               var->green.offset = 5;
7543 +               var->blue.offset = 10;
7544 +               var->red.length = var->green.length = var->blue.length = 5;
7545 +               break;
7546 +       case 24:
7547 +       case 32:
7548 +               var->red.offset = 0;
7549 +               var->green.offset = 8;
7550 +               var->blue.offset = 16;
7551 +               var->red.length = var->green.length = var->blue.length = 8;
7552 +               break;
7553 +       default:
7554 +               dev_err(dev, "color depth %d not supported\n",
7555 +                                       var->bits_per_pixel);
7556 +               return -EINVAL;
7557 +       }
7558 +
7559 +       return 0;
7560 +}
7561 +
7562 +/**
7563 + *      atmel_lcdfb_set_par - Alters the hardware state.
7564 + *      @info: frame buffer structure that represents a single frame buffer
7565 + *
7566 + *     Using the fb_var_screeninfo in fb_info we set the resolution
7567 + *     of the this particular framebuffer. This function alters the
7568 + *     par AND the fb_fix_screeninfo stored in fb_info. It doesn't
7569 + *     not alter var in fb_info since we are using that data. This
7570 + *     means we depend on the data in var inside fb_info to be
7571 + *     supported by the hardware.  atmel_lcdfb_check_var is always called
7572 + *     before atmel_lcdfb_set_par to ensure this.  Again if you can't
7573 + *     change the resolution you don't need this function.
7574 + *
7575 + */
7576 +static int atmel_lcdfb_set_par(struct fb_info *info)
7577 +{
7578 +       struct atmel_lcdfb_info *sinfo = info->par;
7579 +       unsigned long value;
7580 +       unsigned long clk_value_khz;
7581 +
7582 +       dev_dbg(info->device, "%s:\n", __func__);
7583 +       dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
7584 +                info->var.xres, info->var.yres,
7585 +                info->var.xres_virtual, info->var.yres_virtual);
7586 +
7587 +       /* Turn off the LCD controller and the DMA controller */
7588 +       lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
7589 +
7590 +       lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
7591 +
7592 +       if (info->var.bits_per_pixel <= 8)
7593 +               info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
7594 +       else
7595 +               info->fix.visual = FB_VISUAL_TRUECOLOR;
7596 +
7597 +       info->fix.line_length = info->var.xres_virtual * (info->var.bits_per_pixel / 8);
7598 +
7599 +       /* Re-initialize the DMA engine... */
7600 +       dev_dbg(info->device, "  * update DMA engine\n");
7601 +       atmel_lcdfb_update_dma(info, &info->var);
7602 +
7603 +       /* ...set frame size and burst length = 8 words (?) */
7604 +       value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
7605 +       value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
7606 +       lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
7607 +
7608 +       /* Now, the LCDC core... */
7609 +
7610 +       /* Set pixel clock */
7611 +       clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
7612 +
7613 +       value = clk_value_khz / PICOS2KHZ(info->var.pixclock);
7614 +
7615 +       if (clk_value_khz % PICOS2KHZ(info->var.pixclock))
7616 +               value++;
7617 +
7618 +       value = (value / 2) - 1;
7619 +
7620 +       if (value <= 0) {
7621 +               dev_notice(info->device, "Bypassing pixel clock divider\n");
7622 +               lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
7623 +       } else
7624 +               lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, value << ATMEL_LCDC_CLKVAL_OFFSET);
7625 +
7626 +       /* Initialize control register 2 */
7627 +       value = sinfo->default_lcdcon2;
7628 +
7629 +       if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
7630 +               value |= ATMEL_LCDC_INVLINE_INVERTED;
7631 +       if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
7632 +               value |= ATMEL_LCDC_INVFRAME_INVERTED;
7633 +
7634 +       switch (info->var.bits_per_pixel) {
7635 +               case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
7636 +               case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
7637 +               case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
7638 +               case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
7639 +               case 15: /* fall through */
7640 +               case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
7641 +               case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
7642 +               case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
7643 +               default: BUG(); break;
7644 +       }
7645 +       dev_dbg(info->device, "  * LCDCON2 = %08lx\n", value);
7646 +       lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
7647 +
7648 +       /* Vertical timing */
7649 +       value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
7650 +       value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
7651 +       value |= info->var.lower_margin;
7652 +       dev_dbg(info->device, "  * LCDTIM1 = %08lx\n", value);
7653 +       lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
7654 +
7655 +       /* Horizontal timing */
7656 +       value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
7657 +       value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
7658 +       value |= (info->var.left_margin - 1);
7659 +       dev_dbg(info->device, "  * LCDTIM2 = %08lx\n", value);
7660 +       lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
7661 +
7662 +       /* Display size */
7663 +       value = (info->var.xres - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
7664 +       value |= info->var.yres - 1;
7665 +       lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
7666 +
7667 +       /* FIFO Threshold: Use formula from data sheet */
7668 +       value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
7669 +       lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
7670 +
7671 +       /* Toggle LCD_MODE every frame */
7672 +       lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
7673 +
7674 +       /* Disable all interrupts */
7675 +       lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
7676 +
7677 +       /* Set contrast */
7678 +       value = ATMEL_LCDC_PS_DIV8 | ATMEL_LCDC_POL_POSITIVE | ATMEL_LCDC_ENA_PWMENABLE;
7679 +       lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value);
7680 +       lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
7681 +       /* ...wait for DMA engine to become idle... */
7682 +       while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
7683 +               msleep(10);
7684 +
7685 +       dev_dbg(info->device, "  * re-enable DMA engine\n");
7686 +       /* ...and enable it with updated configuration */
7687 +       lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
7688 +
7689 +       dev_dbg(info->device, "  * re-enable LCDC core\n");
7690 +       lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
7691 +               (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
7692 +
7693 +       dev_dbg(info->device, "  * DONE\n");
7694 +
7695 +       return 0;
7696 +}
7697 +
7698 +static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
7699 +{
7700 +       chan &= 0xffff;
7701 +       chan >>= 16 - bf->length;
7702 +       return chan << bf->offset;
7703 +}
7704 +
7705 +/**
7706 + *     atmel_lcdfb_setcolreg - Optional function. Sets a color register.
7707 + *      @regno: Which register in the CLUT we are programming
7708 + *      @red: The red value which can be up to 16 bits wide
7709 + *     @green: The green value which can be up to 16 bits wide
7710 + *     @blue:  The blue value which can be up to 16 bits wide.
7711 + *     @transp: If supported the alpha value which can be up to 16 bits wide.
7712 + *      @info: frame buffer info structure
7713 + *
7714 + *     Set a single color register. The values supplied have a 16 bit
7715 + *     magnitude which needs to be scaled in this function for the hardware.
7716 + *     Things to take into consideration are how many color registers, if
7717 + *     any, are supported with the current color visual. With truecolor mode
7718 + *     no color palettes are supported. Here a psuedo palette is created
7719 + *     which we store the value in pseudo_palette in struct fb_info. For
7720 + *     pseudocolor mode we have a limited color palette. To deal with this
7721 + *     we can program what color is displayed for a particular pixel value.
7722 + *     DirectColor is similar in that we can program each color field. If
7723 + *     we have a static colormap we don't need to implement this function.
7724 + *
7725 + *     Returns negative errno on error, or zero on success. In an
7726 + *     ideal world, this would have been the case, but as it turns
7727 + *     out, the other drivers return 1 on failure, so that's what
7728 + *     we're going to do.
7729 + */
7730 +static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
7731 +                            unsigned int green, unsigned int blue,
7732 +                            unsigned int transp, struct fb_info *info)
7733 +{
7734 +       struct atmel_lcdfb_info *sinfo = info->par;
7735 +       unsigned int val;
7736 +       u32 *pal;
7737 +       int ret = 1;
7738 +
7739 +       if (info->var.grayscale)
7740 +               red = green = blue = (19595 * red + 38470 * green
7741 +                                     + 7471 * blue) >> 16;
7742 +
7743 +       switch (info->fix.visual) {
7744 +       case FB_VISUAL_TRUECOLOR:
7745 +               if (regno < 16) {
7746 +                       pal = info->pseudo_palette;
7747 +
7748 +                       val  = chan_to_field(red, &info->var.red);
7749 +                       val |= chan_to_field(green, &info->var.green);
7750 +                       val |= chan_to_field(blue, &info->var.blue);
7751 +
7752 +                       pal[regno] = val;
7753 +                       ret = 0;
7754 +               }
7755 +               break;
7756 +
7757 +       case FB_VISUAL_PSEUDOCOLOR:
7758 +               if (regno < 256) {
7759 +                       val  = ((red   >> 11) & 0x001f);
7760 +                       val |= ((green >>  6) & 0x03e0);
7761 +                       val |= ((blue  >>  1) & 0x7c00);
7762 +
7763 +                       /*
7764 +                        * TODO: intensity bit. Maybe something like
7765 +                        *   ~(red[10] ^ green[10] ^ blue[10]) & 1
7766 +                        */
7767 +
7768 +                       lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
7769 +                       ret = 0;
7770 +               }
7771 +               break;
7772 +       }
7773 +
7774 +       return ret;
7775 +}
7776 +
7777 +static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
7778 +                              struct fb_info *info)
7779 +{
7780 +       dev_dbg(info->device, "%s\n", __func__);
7781 +
7782 +       atmel_lcdfb_update_dma(info, var);
7783 +
7784 +       return 0;
7785 +}
7786 +
7787 +static struct fb_ops atmel_lcdfb_ops = {
7788 +       .owner          = THIS_MODULE,
7789 +       .fb_check_var   = atmel_lcdfb_check_var,
7790 +       .fb_set_par     = atmel_lcdfb_set_par,
7791 +       .fb_setcolreg   = atmel_lcdfb_setcolreg,
7792 +       .fb_pan_display = atmel_lcdfb_pan_display,
7793 +       .fb_fillrect    = cfb_fillrect,
7794 +       .fb_copyarea    = cfb_copyarea,
7795 +       .fb_imageblit   = cfb_imageblit,
7796 +};
7797 +
7798 +static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
7799 +{
7800 +       struct fb_info *info = dev_id;
7801 +       struct atmel_lcdfb_info *sinfo = info->par;
7802 +       u32 status;
7803 +
7804 +       status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
7805 +       lcdc_writel(sinfo, ATMEL_LCDC_IDR, status);
7806 +       return IRQ_HANDLED;
7807 +}
7808 +
7809 +static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
7810 +{
7811 +       struct fb_info *info = sinfo->info;
7812 +       int ret = 0;
7813 +
7814 +       memset_io(info->screen_base, 0, info->fix.smem_len);
7815 +       info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
7816 +
7817 +       dev_info(info->device,
7818 +              "%luKiB frame buffer at %08lx (mapped at %p)\n",
7819 +              (unsigned long)info->fix.smem_len / 1024,
7820 +              (unsigned long)info->fix.smem_start,
7821 +              info->screen_base);
7822 +
7823 +       /* Allocate colormap */
7824 +       ret = fb_alloc_cmap(&info->cmap, 256, 0);
7825 +       if (ret < 0)
7826 +               dev_err(info->device, "Alloc color map failed\n");
7827 +
7828 +       return ret;
7829 +}
7830 +
7831 +static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
7832 +{
7833 +       if (sinfo->bus_clk)
7834 +               clk_enable(sinfo->bus_clk);
7835 +       clk_enable(sinfo->lcdc_clk);
7836 +}
7837 +
7838 +static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
7839 +{
7840 +       if (sinfo->bus_clk)
7841 +               clk_disable(sinfo->bus_clk);
7842 +       clk_disable(sinfo->lcdc_clk);
7843 +}
7844 +
7845 +
7846 +static int __init atmel_lcdfb_probe(struct platform_device *pdev)
7847 +{
7848 +       struct device *dev = &pdev->dev;
7849 +       struct fb_info *info;
7850 +       struct atmel_lcdfb_info *sinfo;
7851 +       struct atmel_lcdfb_info *pdata_sinfo;
7852 +       struct resource *regs = NULL;
7853 +       struct resource *map = NULL;
7854 +       int ret;
7855 +
7856 +       dev_dbg(dev, "%s BEGIN\n", __func__);
7857 +
7858 +       ret = -ENOMEM;
7859 +       info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
7860 +       if (!info) {
7861 +               dev_err(dev, "cannot allocate memory\n");
7862 +               goto out;
7863 +       }
7864 +
7865 +       sinfo = info->par;
7866 +
7867 +       if (dev->platform_data) {
7868 +               pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data;
7869 +               sinfo->default_bpp = pdata_sinfo->default_bpp;
7870 +               sinfo->default_dmacon = pdata_sinfo->default_dmacon;
7871 +               sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2;
7872 +               sinfo->default_monspecs = pdata_sinfo->default_monspecs;
7873 +               sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
7874 +               sinfo->guard_time = pdata_sinfo->guard_time;
7875 +       } else {
7876 +               dev_err(dev, "cannot get default configuration\n");
7877 +               goto free_info;
7878 +       }
7879 +       sinfo->info = info;
7880 +       sinfo->pdev = pdev;
7881 +
7882 +       strcpy(info->fix.id, sinfo->pdev->name);
7883 +       info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
7884 +       info->pseudo_palette = sinfo->pseudo_palette;
7885 +       info->fbops = &atmel_lcdfb_ops;
7886 +
7887 +       memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
7888 +       info->fix = atmel_lcdfb_fix;
7889 +
7890 +       /* Enable LCDC Clocks */
7891 +       if (cpu_is_at91sam9261()) {
7892 +               sinfo->bus_clk = clk_get(dev, "hck1");
7893 +               if (IS_ERR(sinfo->bus_clk)) {
7894 +                       ret = PTR_ERR(sinfo->bus_clk);
7895 +                       goto free_info;
7896 +               }
7897 +       }
7898 +       sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
7899 +       if (IS_ERR(sinfo->lcdc_clk)) {
7900 +               ret = PTR_ERR(sinfo->lcdc_clk);
7901 +               goto put_bus_clk;
7902 +       }
7903 +       atmel_lcdfb_start_clock(sinfo);
7904 +
7905 +       ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
7906 +                       info->monspecs.modedb_len, info->monspecs.modedb,
7907 +                       sinfo->default_bpp);
7908 +       if (!ret) {
7909 +               dev_err(dev, "no suitable video mode found\n");
7910 +               goto stop_clk;
7911 +       }
7912 +
7913 +
7914 +       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7915 +       if (!regs) {
7916 +               dev_err(dev, "resources unusable\n");
7917 +               ret = -ENXIO;
7918 +               goto stop_clk;
7919 +       }
7920 +
7921 +       sinfo->irq_base = platform_get_irq(pdev, 0);
7922 +       if (sinfo->irq_base < 0) {
7923 +               dev_err(dev, "unable to get irq\n");
7924 +               ret = sinfo->irq_base;
7925 +               goto stop_clk;
7926 +       }
7927 +
7928 +       /* Initialize video memory */
7929 +       map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
7930 +       if (map) {
7931 +               /* use a pre-allocated memory buffer */
7932 +               info->fix.smem_start = map->start;
7933 +               info->fix.smem_len = map->end - map->start + 1;
7934 +               if (!request_mem_region(info->fix.smem_start,
7935 +                                       info->fix.smem_len, pdev->name)) {
7936 +                       ret = -EBUSY;
7937 +                       goto stop_clk;
7938 +               }
7939 +
7940 +               info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
7941 +               if (!info->screen_base)
7942 +                       goto release_intmem;
7943 +       } else {
7944 +               /* alocate memory buffer */
7945 +               ret = atmel_lcdfb_alloc_video_memory(sinfo);
7946 +               if (ret < 0) {
7947 +                       dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
7948 +                       goto stop_clk;
7949 +               }
7950 +       }
7951 +
7952 +       /* LCDC registers */
7953 +       info->fix.mmio_start = regs->start;
7954 +       info->fix.mmio_len = regs->end - regs->start + 1;
7955 +
7956 +       if (!request_mem_region(info->fix.mmio_start,
7957 +                               info->fix.mmio_len, pdev->name)) {
7958 +               ret = -EBUSY;
7959 +               goto free_fb;
7960 +       }
7961 +
7962 +       sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
7963 +       if (!sinfo->mmio) {
7964 +               dev_err(dev, "cannot map LCDC registers\n");
7965 +               goto release_mem;
7966 +       }
7967 +
7968 +       /* interrupt */
7969 +       ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
7970 +       if (ret) {
7971 +               dev_err(dev, "request_irq failed: %d\n", ret);
7972 +               goto unmap_mmio;
7973 +       }
7974 +
7975 +       ret = atmel_lcdfb_init_fbinfo(sinfo);
7976 +       if (ret < 0) {
7977 +               dev_err(dev, "init fbinfo failed: %d\n", ret);
7978 +               goto unregister_irqs;
7979 +       }
7980 +
7981 +       /*
7982 +        * This makes sure that our colour bitfield
7983 +        * descriptors are correctly initialised.
7984 +        */
7985 +       atmel_lcdfb_check_var(&info->var, info);
7986 +
7987 +       ret = fb_set_var(info, &info->var);
7988 +       if (ret) {
7989 +               dev_warn(dev, "unable to set display parameters\n");
7990 +               goto free_cmap;
7991 +       }
7992 +
7993 +       dev_set_drvdata(dev, info);
7994 +
7995 +       /*
7996 +        * Tell the world that we're ready to go
7997 +        */
7998 +       ret = register_framebuffer(info);
7999 +       if (ret < 0) {
8000 +               dev_err(dev, "failed to register framebuffer device: %d\n", ret);
8001 +               goto free_cmap;
8002 +       }
8003 +
8004 +       /* Power up the LCDC screen */
8005 +       if (sinfo->atmel_lcdfb_power_control)
8006 +               sinfo->atmel_lcdfb_power_control(1);
8007 +
8008 +       dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %lu\n",
8009 +                      info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
8010 +
8011 +       return 0;
8012 +
8013 +
8014 +free_cmap:
8015 +       fb_dealloc_cmap(&info->cmap);
8016 +unregister_irqs:
8017 +       free_irq(sinfo->irq_base, info);
8018 +unmap_mmio:
8019 +       iounmap(sinfo->mmio);
8020 +release_mem:
8021 +       release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
8022 +free_fb:
8023 +       if (map)
8024 +               iounmap(info->screen_base);
8025 +       else
8026 +               atmel_lcdfb_free_video_memory(sinfo);
8027 +
8028 +release_intmem:
8029 +       if (map)
8030 +               release_mem_region(info->fix.smem_start, info->fix.smem_len);
8031 +stop_clk:
8032 +       atmel_lcdfb_stop_clock(sinfo);
8033 +       clk_put(sinfo->lcdc_clk);
8034 +put_bus_clk:
8035 +       if (sinfo->bus_clk)
8036 +               clk_put(sinfo->bus_clk);
8037 +free_info:
8038 +       framebuffer_release(info);
8039 +out:
8040 +       dev_dbg(dev, "%s FAILED\n", __func__);
8041 +       return ret;
8042 +}
8043 +
8044 +static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
8045 +{
8046 +       struct device *dev = &pdev->dev;
8047 +       struct fb_info *info = dev_get_drvdata(dev);
8048 +       struct atmel_lcdfb_info *sinfo = info->par;
8049 +
8050 +       if (!sinfo)
8051 +               return 0;
8052 +
8053 +       if (sinfo->atmel_lcdfb_power_control)
8054 +               sinfo->atmel_lcdfb_power_control(0);
8055 +       unregister_framebuffer(info);
8056 +       atmel_lcdfb_stop_clock(sinfo);
8057 +       clk_put(sinfo->lcdc_clk);
8058 +       if (sinfo->bus_clk)
8059 +               clk_put(sinfo->bus_clk);
8060 +       fb_dealloc_cmap(&info->cmap);
8061 +       free_irq(sinfo->irq_base, info);
8062 +       iounmap(sinfo->mmio);
8063 +       release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
8064 +       if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
8065 +               iounmap(info->screen_base);
8066 +               release_mem_region(info->fix.smem_start, info->fix.smem_len);
8067 +       } else {
8068 +               atmel_lcdfb_free_video_memory(sinfo);
8069 +       }
8070 +
8071 +       dev_set_drvdata(dev, NULL);
8072 +       framebuffer_release(info);
8073 +
8074 +       return 0;
8075 +}
8076 +
8077 +static struct platform_driver atmel_lcdfb_driver = {
8078 +       .remove         = __exit_p(atmel_lcdfb_remove),
8079 +       .driver         = {
8080 +               .name   = "atmel_lcdfb",
8081 +               .owner  = THIS_MODULE,
8082 +       },
8083 +};
8084 +
8085 +static int __init atmel_lcdfb_init(void)
8086 +{
8087 +       return platform_driver_probe(&atmel_lcdfb_driver, atmel_lcdfb_probe);
8088 +}
8089 +
8090 +static void __exit atmel_lcdfb_exit(void)
8091 +{
8092 +       platform_driver_unregister(&atmel_lcdfb_driver);
8093 +}
8094 +
8095 +module_init(atmel_lcdfb_init);
8096 +module_exit(atmel_lcdfb_exit);
8097 +
8098 +MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver");
8099 +MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@rfo.atmel.com>");
8100 +MODULE_LICENSE("GPL");
8101 Index: linux-2.6.21.7/drivers/video/backlight/Kconfig
8102 ===================================================================
8103 --- linux-2.6.21.7.orig/drivers/video/backlight/Kconfig
8104 +++ linux-2.6.21.7/drivers/video/backlight/Kconfig
8105 @@ -63,3 +63,11 @@ config BACKLIGHT_PROGEAR
8106         help
8107           If you have a Frontpath ProGear say Y to enable the
8108           backlight driver.
8109 +
8110 +config BACKLIGHT_KB920x
8111 +       tristate "KwikByte KB9202 Backlight Driver"
8112 +       depends on BACKLIGHT_CLASS_DEVICE && MACH_KB9200
8113 +       default y
8114 +       help
8115 +         If you have a KwikByte KB9202 board, say Y to enable the
8116 +         backlight driver.
8117 Index: linux-2.6.21.7/drivers/video/backlight/Makefile
8118 ===================================================================
8119 --- linux-2.6.21.7.orig/drivers/video/backlight/Makefile
8120 +++ linux-2.6.21.7/drivers/video/backlight/Makefile
8121 @@ -6,3 +6,4 @@ obj-$(CONFIG_BACKLIGHT_CORGI)   += corgi_b
8122  obj-$(CONFIG_BACKLIGHT_HP680)  += hp680_bl.o
8123  obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o
8124  obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o
8125 +obj-$(CONFIG_BACKLIGHT_KB920x) += kb920x_bl.o
8126 Index: linux-2.6.21.7/drivers/video/backlight/kb920x_bl.c
8127 ===================================================================
8128 --- /dev/null
8129 +++ linux-2.6.21.7/drivers/video/backlight/kb920x_bl.c
8130 @@ -0,0 +1,164 @@
8131 +/*
8132 + * Backlight Driver for KB9202
8133 + *
8134 + * Copyright (c) 2006 KwikByte
8135 + *
8136 + * Based on Sharp's Corgi Backlight Driver
8137 + *
8138 + * This file is subject to the terms and conditions of the GNU General Public
8139 + * License.  See the file "COPYING" in the main directory of this archive
8140 + * for more details.
8141 + */
8142 +
8143 +#include <linux/module.h>
8144 +#include <linux/kernel.h>
8145 +#include <linux/init.h>
8146 +#include <linux/platform_device.h>
8147 +#include <linux/spinlock.h>
8148 +#include <linux/fb.h>
8149 +#include <linux/backlight.h>
8150 +
8151 +#include <asm/arch/gpio.h>
8152 +
8153 +/* The backlight is on(1)/off(0) */
8154 +#define        KB9202_DEFAULT_INTENSITY        1
8155 +#define        KB9202_MAX_INTENSITY            1
8156 +
8157 +static int kb9202bl_suspended;
8158 +static int current_intensity = 0;
8159 +static DEFINE_SPINLOCK(bl_lock);
8160 +
8161 +static int kb9202bl_set_intensity(struct backlight_device *bd)
8162 +{
8163 +       unsigned long flags;
8164 +       int intensity = bd->props.brightness;
8165 +
8166 +       if (bd->props.power != FB_BLANK_UNBLANK)
8167 +               intensity = 0;
8168 +       if (bd->props.fb_blank != FB_BLANK_UNBLANK)
8169 +               intensity = 0;
8170 +       if (kb9202bl_suspended)
8171 +               intensity = 0;
8172 +
8173 +       if ((!current_intensity) && (bd->props.power == FB_BLANK_UNBLANK))
8174 +               intensity = 1;
8175 +
8176 +       spin_lock_irqsave(&bl_lock, flags);
8177 +       if (intensity)
8178 +               gpio_set_value(AT91_PIN_PC23, 1);
8179 +       else
8180 +               gpio_set_value(AT91_PIN_PC23, 0);
8181 +       spin_unlock_irqrestore(&bl_lock, flags);
8182 +
8183 +       current_intensity = intensity;
8184 +
8185 +       return 0;
8186 +}
8187 +
8188 +static int kb9202bl_get_intensity(struct backlight_device *bd)
8189 +{
8190 +       return current_intensity;
8191 +}
8192 +
8193 +static struct backlight_ops kb9202bl_ops = {
8194 +       .get_brightness = kb9202bl_get_intensity,
8195 +       .update_status  = kb9202bl_set_intensity,
8196 +};
8197 +
8198 +static int __init kb9202bl_probe(struct platform_device *pdev)
8199 +{
8200 +       struct backlight_device *bd;
8201 +
8202 +       bd = backlight_device_register ("kb9202-bl", &pdev->dev, NULL, &kb9202bl_ops);
8203 +       if (IS_ERR(bd))
8204 +               return PTR_ERR(bd);
8205 +
8206 +       platform_set_drvdata(pdev, bd);
8207 +
8208 +       bd->props.max_brightness = KB9202_MAX_INTENSITY;
8209 +       bd->props.brightness = KB9202_DEFAULT_INTENSITY;
8210 +       (void) kb9202bl_set_intensity(bd);
8211 +
8212 +       return 0;
8213 +}
8214 +
8215 +static int kb9202bl_remove(struct platform_device *pdev)
8216 +{
8217 +       struct backlight_device *bd = platform_get_drvdata(pdev);
8218 +
8219 +       bd->props.brightness = 0;
8220 +       bd->props.power = 0;
8221 +       (void) kb9202bl_set_intensity(bd);
8222 +
8223 +       backlight_device_unregister(bd);
8224 +
8225 +       return 0;
8226 +}
8227 +
8228 +#ifdef CONFIG_PM
8229 +static int kb9202bl_suspend(struct platform_device *dev, pm_message_t state)
8230 +{
8231 +       struct backlight_device *bd = platform_get_drvdata(pdev);
8232 +
8233 +       kb9202bl_suspended = 1;
8234 +       (void) kb9202bl_set_intensity(bd);
8235 +       return 0;
8236 +}
8237 +
8238 +static int kb9202bl_resume(struct platform_device *dev)
8239 +{
8240 +       struct backlight_device *bd = platform_get_drvdata(pdev);
8241 +
8242 +       kb9202bl_suspended = 0;
8243 +       (void) kb9202bl_set_intensity(bd);
8244 +       return 0;
8245 +}
8246 +#else
8247 +#define kb9202bl_suspend       NULL
8248 +#define kb9202bl_resume                NULL
8249 +#endif
8250 +
8251 +static struct platform_driver kb9202bl_driver = {
8252 +       .probe          = kb9202bl_probe,
8253 +       .remove         = kb9202bl_remove,
8254 +       .suspend        = kb9202bl_suspend,
8255 +       .resume         = kb9202bl_resume,
8256 +       .driver         = {
8257 +               .name   = "kb9202-bl",
8258 +               .owner  = THIS_MODULE,
8259 +       },
8260 +};
8261 +
8262 +static struct platform_device *kb9202bl_device;
8263 +
8264 +static int __init kb9202bl_init(void)
8265 +{
8266 +       int ret;
8267 +
8268 +       ret = platform_driver_register(&kb9202bl_driver);
8269 +       if (!ret) {
8270 +               kb9202bl_device = platform_device_alloc("kb9202-bl", -1);
8271 +               if (!kb9202bl_device)
8272 +                       return -ENOMEM;
8273 +
8274 +               ret = platform_device_add(kb9202bl_device);
8275 +               if (ret) {
8276 +                       platform_device_put(kb9202bl_device);
8277 +                       platform_driver_unregister(&kb9202bl_driver);
8278 +               }
8279 +       }
8280 +       return ret;
8281 +}
8282 +
8283 +static void __exit kb9202bl_exit(void)
8284 +{
8285 +       platform_device_unregister(kb9202bl_device);
8286 +       platform_driver_unregister(&kb9202bl_driver);
8287 +}
8288 +
8289 +module_init(kb9202bl_init);
8290 +module_exit(kb9202bl_exit);
8291 +
8292 +MODULE_AUTHOR("KwikByte <kb9200_dev@kwikbyte.com>");
8293 +MODULE_DESCRIPTION("KB9202 Backlight Driver");
8294 +MODULE_LICENSE("GPL");
8295 Index: linux-2.6.21.7/drivers/video/s1d15605fb.c
8296 ===================================================================
8297 --- /dev/null
8298 +++ linux-2.6.21.7/drivers/video/s1d15605fb.c
8299 @@ -0,0 +1,659 @@
8300 +/*
8301 + *  drivers/video/s1d15605.c
8302 + *
8303 + * Adapted from several sources including:
8304 + * 1) Driver for AT91 LCD Controller
8305 + *    Copyright (C) 2006 Atmel
8306 + *
8307 + * 2) Copyright (C) 2005 S. Kevin Hester
8308 + *
8309 + *   This file is subject to the terms and conditions of the GNU General Public
8310 + *   License. See the file COPYING in the main directory of this archive for
8311 + *   more details.
8312 + *
8313 + *   This is a basic framebuffer driver for the Optrex F-51320 128x64 mono LCD
8314 + *   display.  This display uses a clone of the common Epson SED 1531 display
8315 + *   controller.
8316 + *
8317 + *   I've heavily borrowed code from the vfb.c driver.
8318 + *
8319 + * This program is free software; you can redistribute it and/or modify
8320 + * it under the terms of the GNU General Public License as published by
8321 + * the Free Software Foundation; either version 2 of the License, or
8322 + * (at your option) any later version.
8323 + *
8324 + * This program is distributed in the hope that it will be useful,
8325 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8326 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8327 + * GNU General Public License for more details.
8328 + *
8329 + * You should have received a copy of the GNU General Public License
8330 + * along with this program; if not, write to the Free Software
8331 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
8332 + */
8333 +
8334 +#ifdef DEBUG
8335 +#define MSG(string, args...) printk("s1d15605fb:" string, ##args)
8336 +#else
8337 +#define MSG(string, args...)
8338 +#endif
8339 +
8340 +#include <linux/kernel.h>
8341 +#include <linux/platform_device.h>
8342 +#include <linux/dma-mapping.h>
8343 +#include <linux/interrupt.h>
8344 +#include <linux/clk.h>
8345 +#include <linux/fb.h>
8346 +#include <linux/init.h>
8347 +#include <linux/delay.h>
8348 +
8349 +#include <asm/uaccess.h>
8350 +
8351 +#include <asm/arch/board.h>
8352 +#include <asm/arch/gpio.h>
8353 +
8354 +#ifdef CONFIG_PMAC_BACKLIGHT
8355 +#include <asm/backlight.h>
8356 +#endif
8357 +
8358 +#define VIDEOWIDTH             128
8359 +#define VIDEOHEIGHT            64
8360 +#define VIDEODEPTH             1       /* bits/pixel */
8361 +#define VIDEOWIDTH_BYTES       ((VIDEOWIDTH * VIDEODEPTH) / 8)
8362 +
8363 +/* The number of bytes that actually go to the device */
8364 +#define ACTUALVIDEOMEMSIZE     (VIDEOWIDTH_BYTES * VIDEOHEIGHT)
8365 +#define VIDEOMEMSIZE           PAGE_SIZE
8366 +
8367 +static struct fb_var_screeninfo s1d15605_default __initdata = {
8368 +       .xres           = VIDEOWIDTH,
8369 +       .yres           = VIDEOHEIGHT,
8370 +       .xres_virtual   = VIDEOWIDTH,
8371 +       .yres_virtual   = VIDEOHEIGHT,
8372 +       .bits_per_pixel = VIDEODEPTH,
8373 +       .red            = { 0, 1, 0 },
8374 +       .green          = { 0, 1, 0 },
8375 +       .blue           = { 0, 1, 0 },
8376 +       .activate       = FB_ACTIVATE_NOW,
8377 +       .pixclock       = 20000,
8378 +       .vmode          = FB_VMODE_NONINTERLACED,
8379 +};
8380 +
8381 +static struct fb_fix_screeninfo s1d15605_fix __initdata = {
8382 +       .id             = "s1d15605",
8383 +       .type           = FB_TYPE_PACKED_PIXELS,
8384 +       .visual         = FB_VISUAL_MONO10,
8385 +       .xpanstep       = 0,
8386 +       .ypanstep       = 0,
8387 +       .ywrapstep      = 0,
8388 +       .accel          = FB_ACCEL_NONE,
8389 +};
8390 +
8391 +struct s1d15605fb_info {
8392 +       struct fb_info          *info;
8393 +       char                    *mmio;
8394 +       unsigned long           reset_pin;
8395 +       struct platform_device  *pdev;
8396 +};
8397 +
8398 +/*
8399 + * LCD device interface
8400 + */
8401 +#define        RESET_DISPLAY           0xE2
8402 +#define        LCD_BIAS_1_9            0xA2
8403 +#define        ADC_SELECT_REVERSE      0xA1
8404 +#define        COMMON_OUTPUT_NORMAL    0xC0
8405 +#define        V5_RESISTOR_RATIO       0x26
8406 +#define        ELECTRONIC_VOLUME_SET   0x81
8407 +#define        ELECTRONIC_VOLUME_INIT  0x20
8408 +#define        POWER_CONTROL_SET       0x28
8409 +#define        VOLTAGE_REGULATOR       0x02
8410 +#define        VOLTAGE_FOLLOWER        0x01
8411 +#define        BOOSTER_CIRCUIT         0x04
8412 +#define        DISPLAY_ON              0xAF
8413 +#define        START_LINE_SET          0x40
8414 +#define        PAGE_ADDRESS_SET        0xB0
8415 +#define        COLUMN_ADDRESS_HIGH     0x10
8416 +#define        COLUMN_ADDRESS_LOW      0x00
8417 +#define        RESISTOR_RATIO_START    0x20
8418 +
8419 +#define        NUM_OF_PAGES            8
8420 +#define        NUM_OF_COLUMNS          128
8421 +
8422 +#define        WRITE_COMMAND(x)        __raw_writeb((x), (sinfo)->mmio)
8423 +#define        READ_COMMAND            __raw_readb((sinfo)->mmio)
8424 +#define        WRITE_DATA(x)           __raw_writeb((x), (sinfo)->mmio + (0x10000))
8425 +#define        READ_DATA               __raw_readb((sinfo)->mmio + (0x10000))
8426 +
8427 +
8428 +/*
8429 + *     s1d15605fb_resize_framebuffer
8430 + *
8431 + *     Free allocated space if different.  Allocate on new of changed.
8432 + *     Returns -ENOMEM if the new framebuffer can not be allocated,
8433 + *     zero on success.
8434 + */
8435 +static int s1d15605fb_resize_framebuffer(struct s1d15605fb_info *sinfo)
8436 +{
8437 +       struct fb_info                  *info = sinfo->info;
8438 +       struct fb_fix_screeninfo        *fix = &info->fix;
8439 +       struct fb_var_screeninfo        *var = &info->var;
8440 +       unsigned int                    new_size;
8441 +       void                            *new_vaddr;
8442 +
8443 +       new_size = ((var->xres_virtual * var->yres_virtual * var->bits_per_pixel) / 8);
8444 +
8445 +       MSG("%s: x (%d) y (%d) bpp (%d): new size 0x%08x\n", __FUNCTION__,
8446 +               var->xres_virtual, var->yres_virtual, var->bits_per_pixel, new_size);
8447 +
8448 +       if (new_size == fix->smem_len)
8449 +               return 0;
8450 +
8451 +       if (fix->smem_len) {
8452 +               kfree(info->screen_base);
8453 +       }
8454 +
8455 +       new_vaddr = kmalloc(new_size, GFP_KERNEL);
8456 +
8457 +       if (!new_vaddr) {
8458 +               fix->smem_len = 0;
8459 +               return -ENOMEM;
8460 +       }
8461 +
8462 +       info->screen_base = new_vaddr;
8463 +       fix->smem_start = (unsigned)new_vaddr;
8464 +       fix->smem_len = new_size;
8465 +       fix->line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
8466 +
8467 +       dev_info(info->device,
8468 +               "%luKiB frame buffer at %08lx (mapped at %p)\n",
8469 +               (unsigned long)info->fix.smem_len / 1024,
8470 +               (unsigned long)info->fix.smem_start,
8471 +               info->screen_base);
8472 +
8473 +       return 0;
8474 +}
8475 +
8476 +
8477 +/*
8478 + * The s1d15605 seems to be divided into eight 128 pixel wide pages (from top to
8479 + * bottom) each page seems to be eight pixels high, where these eight pixels are
8480 + * one byte
8481 + */
8482 +static void s1d15605_update(struct fb_info *info)
8483 +{
8484 +       struct s1d15605fb_info  *sinfo = info->par;
8485 +       int                     page, i, row, colmask;
8486 +       u8                      retVal, *rowPtr;
8487 +
8488 +       WRITE_COMMAND(START_LINE_SET);
8489 +       for (page = 0; page < NUM_OF_PAGES; ++page) {
8490 +               WRITE_COMMAND(PAGE_ADDRESS_SET + page);
8491 +               WRITE_COMMAND(COLUMN_ADDRESS_HIGH);
8492 +               WRITE_COMMAND(COLUMN_ADDRESS_LOW);
8493 +
8494 +               for (i = 0; i < NUM_OF_COLUMNS; ++i)
8495 +               {
8496 +                       /* point of opportunity: optimization */
8497 +                       colmask = (1 << (i & 0x7));
8498 +                       rowPtr = (u8*)(info->screen_base);
8499 +                       rowPtr += (VIDEOWIDTH_BYTES * 8 * page);
8500 +                       rowPtr += (i >> 3);
8501 +                       retVal = 0;
8502 +                       for (row = 0; row < 8; ++row)
8503 +                       {
8504 +                               retVal = (retVal >> 1) | (((*rowPtr) & colmask) ? 0x80 : 0);
8505 +                               rowPtr += VIDEOWIDTH_BYTES;
8506 +                       }
8507 +                       WRITE_DATA(retVal);
8508 +               }
8509 +       }
8510 +
8511 +       WRITE_COMMAND(DISPLAY_ON);
8512 +}
8513 +
8514 +
8515 +/*
8516 + * Setting the video mode has been split into two parts.
8517 + * First part, xxxfb_check_var, must not write anything
8518 + * to hardware, it should only verify and adjust var.
8519 + * This means it doesn't alter par but it does use hardware
8520 + * data from it to check this var.
8521 + */
8522 +static int s1d15605_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
8523 +{
8524 +       /*
8525 +        * Some very basic checks
8526 +        */
8527 +       if (!var->xres)
8528 +               var->xres = 1;
8529 +       if (!var->yres)
8530 +               var->yres = 1;
8531 +       if (var->xres > var->xres_virtual)
8532 +               var->xres_virtual = var->xres;
8533 +       if (var->yres > var->yres_virtual)
8534 +               var->yres_virtual = var->yres;
8535 +
8536 +       if(var->bits_per_pixel > VIDEODEPTH)
8537 +               return -EINVAL;
8538 +
8539 +       /*
8540 +        * Memory limit
8541 +        */
8542 +       if (((var->yres_virtual * var->bits_per_pixel * var->yres_virtual) >> 3) >
8543 +                       ACTUALVIDEOMEMSIZE)
8544 +               return -ENOMEM;
8545 +
8546 +       /*
8547 +        * Now that we checked it we alter var. The reason being is that the video
8548 +        * mode passed in might not work but slight changes to it might make it
8549 +        * work. This way we let the user know what is acceptable.
8550 +        */
8551 +       switch (var->bits_per_pixel) {
8552 +       case 1:
8553 +               var->red.offset = var->green.offset = var->blue.offset = 0;
8554 +               var->red.length = var->green.length = var->blue.length
8555 +                       = var->bits_per_pixel;
8556 +               break;
8557 +       default:
8558 +               return -EINVAL;
8559 +       }
8560 +
8561 +       var->xoffset = var->yoffset = 0;
8562 +       var->red.msb_right = var->green.msb_right = var->blue.msb_right =
8563 +               var->transp.msb_right = 0;
8564 +
8565 +       return 0;
8566 +}
8567 +
8568 +
8569 +/*
8570 + * This routine actually sets the video mode. It's in here where we
8571 + * the hardware state info->par and fix which can be affected by the
8572 + * change in par. For this driver it doesn't do much.
8573 + */
8574 +static int s1d15605_set_par(struct fb_info *info)
8575 +{
8576 +       int     ret;
8577 +
8578 +       MSG("%s:\n", __func__);
8579 +       MSG("  * resolution: %ux%u (%ux%u virtual)\n",
8580 +                info->var.xres, info->var.yres,
8581 +                info->var.xres_virtual, info->var.yres_virtual);
8582 +
8583 +       ret = s1d15605fb_resize_framebuffer(info->par);
8584 +
8585 +       info->fix.visual = FB_VISUAL_MONO10;
8586 +       return ret;
8587 +}
8588 +
8589 +
8590 +/*
8591 + * Set a single color register. The values supplied are already
8592 + * rounded down to the hardware's capabilities (according to the
8593 + * entries in the var structure). Return != 0 for invalid regno.
8594 + */
8595 +static int s1d15605_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
8596 +                       u_int transp, struct fb_info *info)
8597 +{
8598 +       if (regno > 1)  /* no. of hw registers - we only do mono now */
8599 +               return 1;
8600 +
8601 +       return 0;
8602 +}
8603 +
8604 +
8605 +/*
8606 + * Currently, the routine will simply shut-off the backlight and prevent
8607 + * updates/refreshes.  Modify according to application.
8608 + *
8609 + * 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off
8610 + */
8611 +static int s1d15605_blank(int blank, struct fb_info *info)
8612 +{
8613 +#ifdef CONFIG_PMAC_BACKLIGHT
8614 +       if (blank)
8615 +               pmac_backlight->props.power = FB_BLANK_POWERDOWN;
8616 +       else
8617 +               pmac_backlight->props.power = FB_BLANK_UNBLANK;
8618 +       backlight_update_status(pmac_backlight);
8619 +#endif
8620 +       return 1;
8621 +}
8622 +
8623 +
8624 +/*
8625 + * Pan or Wrap the Display
8626 + *
8627 + * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
8628 + */
8629 +/*
8630 +static int s1d15605_pan_display(struct fb_var_screeninfo *var,
8631 +                       struct fb_info *info)
8632 +{
8633 +       if (var->vmode & FB_VMODE_YWRAP) {
8634 +               if (var->yoffset < 0
8635 +                   || var->yoffset >= info->var.yres_virtual
8636 +                   || var->xoffset)
8637 +                       return -EINVAL;
8638 +       } else {
8639 +               if (var->xoffset + var->xres > info->var.xres_virtual ||
8640 +                   var->yoffset + var->yres > info->var.yres_virtual)
8641 +                       return -EINVAL;
8642 +       }
8643 +       info->var.xoffset = var->xoffset;
8644 +       info->var.yoffset = var->yoffset;
8645 +       if (var->vmode & FB_VMODE_YWRAP)
8646 +               info->var.vmode |= FB_VMODE_YWRAP;
8647 +       else
8648 +               info->var.vmode &= ~FB_VMODE_YWRAP;
8649 +       return 0;
8650 +}
8651 +*/
8652 +
8653 +
8654 +static void s1d15605_copyarea(struct fb_info *info, const struct fb_copyarea *region)
8655 +{
8656 +       cfb_copyarea(info, region);
8657 +       s1d15605_update(info);
8658 +}
8659 +
8660 +
8661 +static void s1d15605_fillrect (struct fb_info *info, const struct fb_fillrect *rect)
8662 +{
8663 +       cfb_fillrect(info, rect);
8664 +       s1d15605_update(info);
8665 +}
8666 +
8667 +
8668 +static void s1d15605_imageblit(struct fb_info *p, const struct fb_image *image)
8669 +{
8670 +       cfb_imageblit(p, image);
8671 +       s1d15605_update(p);
8672 +}
8673 +
8674 +
8675 +/*
8676 + * Write the users data to our framebuffer, and then trigger a psuedo DMA
8677 + */
8678 +static ssize_t s1d15605_write(struct file *file, const char *buf,
8679 +                       size_t count, loff_t *ppos)
8680 +{
8681 +       unsigned long p = *ppos;
8682 +       struct inode *inode = file->f_dentry->d_inode;
8683 +       int fbidx = iminor(inode);
8684 +       struct fb_info *info = registered_fb[fbidx];
8685 +       int err;
8686 +
8687 +       if (p > info->fix.smem_len)
8688 +               return -ENOSPC;
8689 +       if (count >= info->fix.smem_len)
8690 +               count = info->fix.smem_len;
8691 +       err = 0;
8692 +       if (count + p > info->fix.smem_len) {
8693 +               count = info->fix.smem_len - p;
8694 +               err = -ENOSPC;
8695 +       }
8696 +       if (count) {
8697 +               char *base_addr;
8698 +
8699 +               base_addr = info->screen_base;
8700 +               count -= copy_from_user(base_addr+p, buf, count);
8701 +               *ppos += count;
8702 +               err = -EFAULT;
8703 +       }
8704 +
8705 +       s1d15605_update(info);
8706 +
8707 +       if (count)
8708 +               return count;
8709 +
8710 +       return err;
8711 +}
8712 +
8713 +#ifdef USE_PRIVATE_VMA_FXS
8714 +static void s1d15605_vma_open(struct vm_area_struct *vma)
8715 +{
8716 +       // FIXME - store stats in the device data via vm_private_data
8717 +}
8718 +
8719 +
8720 +static void s1d15605_vma_close(struct vm_area_struct *vma)
8721 +{
8722 +       // FIXME - store stats in the device data via vm_private_data
8723 +}
8724 +
8725 +
8726 +static struct page *s1d15605_vma_nopage(struct vm_area_struct *vma,
8727 +                               unsigned long address, int *type)
8728 +{
8729 +       struct page *page;
8730 +       struct fb_info *info = vma->vm_private_data;
8731 +
8732 +       page = virt_to_page(info->screen_base);
8733 +       get_page(page);
8734 +
8735 +       // FIXME - now someone has a link to our page, start periodically blitting
8736 +       // latest updates to the actual device.
8737 +
8738 +       return page;
8739 +}
8740 +
8741 +
8742 +static struct vm_operations_struct s1d15605_vm_ops = {
8743 +       .open   = s1d15605_vma_open,
8744 +       .close  = s1d15605_vma_close,
8745 +       .nopage = s1d15605_vma_nopage
8746 +};
8747 +
8748 +
8749 +/* We don't do much here - because we have special vm_ops */
8750 +static int s1d15605_mmap(struct fb_info *info, struct vm_area_struct *vma)
8751 +{
8752 +       vma->vm_ops = &s1d15605_vm_ops;
8753 +       vma->vm_flags |= VM_RESERVED;
8754 +       vma->vm_private_data = info;
8755 +       s1d15605_vma_open(vma);
8756 +
8757 +       return 0;
8758 +}
8759 +#endif /* USE_PRIVATE_VMA_FXS */
8760 +
8761 +
8762 +static struct fb_ops s1d15605fb_ops = {
8763 +       .owner          = THIS_MODULE,
8764 +       .fb_check_var   = s1d15605_check_var,
8765 +       .fb_set_par     = s1d15605_set_par,
8766 +       .fb_setcolreg   = s1d15605_setcolreg,
8767 +       .fb_blank       = s1d15605_blank,
8768 +//     .fb_pan_display = s1d15605_pan_display,
8769 +       .fb_fillrect    = s1d15605_fillrect,
8770 +       .fb_copyarea    = s1d15605_copyarea,
8771 +       .fb_imageblit   = s1d15605_imageblit,
8772 +       .fb_write       = s1d15605_write,
8773 +#ifdef USE_PRIVATE_VMA_FXS
8774 +       .fb_mmap        = s1d15605_mmap,
8775 +#endif
8776 +};
8777 +
8778 +
8779 +static void s1d15605_device_init(struct s1d15605fb_info *sinfo) {
8780 +
8781 +       char    value;
8782 +
8783 +       /* release the reset line by reading the device - proto hardware */
8784 +       value = READ_COMMAND;
8785 +       value = READ_COMMAND;
8786 +
8787 +#ifdef CONFIG_MACH_KB9200
8788 +       /* new boards have dedicated reset line */
8789 +       gpio_set_value(sinfo->reset_pin, 1);
8790 +#endif
8791 +
8792 +       /* initialize the device within 5ms */
8793 +       WRITE_COMMAND(RESET_DISPLAY);
8794 +       WRITE_COMMAND(LCD_BIAS_1_9);
8795 +       WRITE_COMMAND(ADC_SELECT_REVERSE);
8796 +       WRITE_COMMAND(COMMON_OUTPUT_NORMAL);
8797 +       WRITE_COMMAND(V5_RESISTOR_RATIO);
8798 +       WRITE_COMMAND(ELECTRONIC_VOLUME_SET);
8799 +       WRITE_COMMAND(ELECTRONIC_VOLUME_INIT);
8800 +       WRITE_COMMAND(POWER_CONTROL_SET | VOLTAGE_REGULATOR | VOLTAGE_FOLLOWER | BOOSTER_CIRCUIT);
8801 +       WRITE_COMMAND(DISPLAY_ON);
8802 +
8803 +       WRITE_COMMAND(RESISTOR_RATIO_START + 4);
8804 +       WRITE_COMMAND(ELECTRONIC_VOLUME_SET);
8805 +       WRITE_COMMAND(0x33);
8806 +}
8807 +
8808 +
8809 +static int s1d15605fb_probe(struct platform_device *pdev)
8810 +{
8811 +       struct device *dev = &pdev->dev;
8812 +       struct fb_info *info;
8813 +       struct s1d15605fb_info *sinfo;
8814 +       int ret;
8815 +
8816 +       MSG("%s\n", __func__);
8817 +
8818 +       if (!(info = framebuffer_alloc(sizeof(struct s1d15605fb_info), dev))) {
8819 +               dev_err(dev, "Cannot allocate framebuffer struct\n");
8820 +               return -ENOMEM;
8821 +       }
8822 +
8823 +       sinfo = info->par;
8824 +       sinfo->info = info;
8825 +       sinfo->pdev = pdev;
8826 +
8827 +       if (pdev->num_resources < 2) {
8828 +               dev_err(dev, "Resources unusable\n");
8829 +               ret = -ENODEV;
8830 +               goto free_info;
8831 +       }
8832 +
8833 +       info->fbops = &s1d15605fb_ops;
8834 +       strcpy(info->fix.id, pdev->name);
8835 +
8836 +       info->fix.mmio_start = pdev->resource[0].start;
8837 +       info->fix.mmio_len = pdev->resource[0].end - pdev->resource[0].start + 1;
8838 +       sinfo->reset_pin = pdev->resource[1].start;
8839 +
8840 +       ret = s1d15605fb_resize_framebuffer(sinfo);
8841 +       if (ret < 0) {
8842 +               dev_err(dev, "Cannot resize framebuffer: %d\n", ret);
8843 +               goto free_fb;
8844 +       }
8845 +
8846 +       if (!request_mem_region(info->fix.mmio_start,
8847 +                               info->fix.mmio_len, pdev->name)) {
8848 +               ret = -EBUSY;
8849 +               goto free_fb;
8850 +       }
8851 +
8852 +       sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
8853 +       if (!sinfo->mmio) {
8854 +               dev_err(dev, "Cannot map LCD memory region\n");
8855 +               goto release_mem;
8856 +       }
8857 +
8858 +       s1d15605_device_init(sinfo);
8859 +
8860 +       ret = fb_find_mode(&info->var, info, NULL, NULL, 0, NULL, 1);
8861 +
8862 +       if (!ret || (ret == 4))
8863 +               info->var = s1d15605_default;
8864 +
8865 +       info->fix = s1d15605_fix;
8866 +       info->flags = FBINFO_FLAG_DEFAULT |
8867 +/*             FBINFO_HWACCEL_YPAN | */
8868 +               FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
8869 +
8870 +       ret = register_framebuffer(info);
8871 +       if (ret < 0) {
8872 +               dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
8873 +               goto unmap_mmio;
8874 +       }
8875 +
8876 +       dev_set_drvdata(dev, info);
8877 +
8878 +       memset(info->screen_base, 0, info->fix.smem_len);
8879 +       info->var.activate |= FB_ACTIVATE_NOW;
8880 +       ret = fb_set_var(info, &info->var);
8881 +       if (ret) {
8882 +               dev_warn(dev, "Unable to set display parameters\n");
8883 +       }
8884 +
8885 +       info->var.activate &= ~(FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW);
8886 +
8887 +       dev_dbg(dev, "%s SUCCESS\n", __func__);
8888 +
8889 +       dev_info(dev, "Driver $Revision: 1.1 $\n");
8890 +
8891 +       return 0;
8892 +
8893 +unmap_mmio:
8894 +       iounmap(sinfo->mmio);
8895 +release_mem:
8896 +       release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
8897 +free_fb:
8898 +       kfree(info->screen_base);
8899 +
8900 +free_info:
8901 +       framebuffer_release(info);
8902 +
8903 +       dev_dbg(dev, "%s FAILED\n", __func__);
8904 +       return ret;
8905 +}
8906 +
8907 +
8908 +static int s1d15605fb_remove(struct platform_device *pdev)
8909 +{
8910 +       struct device *dev = &pdev->dev;
8911 +       struct fb_info *info = dev_get_drvdata(dev);
8912 +       struct s1d15605fb_info *sinfo = info->par;
8913 +
8914 +       if (!sinfo)
8915 +               return 0;
8916 +
8917 +       unregister_framebuffer(info);
8918 +
8919 +       iounmap(sinfo->mmio);
8920 +       release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
8921 +
8922 +       kfree(info->screen_base);
8923 +
8924 +       dev_set_drvdata(dev, NULL);
8925 +       framebuffer_release(info);
8926 +       return 0;
8927 +}
8928 +
8929 +
8930 +static struct platform_driver s1d15605fb_driver = {
8931 +       .probe          = s1d15605fb_probe,
8932 +       .remove         = s1d15605fb_remove,
8933 +       .driver         = {
8934 +               .name   = "s1d15605fb",
8935 +               .owner  = THIS_MODULE,
8936 +       },
8937 +};
8938 +
8939 +
8940 +static int __init s1d15605fb_init(void)
8941 +{
8942 +       return platform_driver_register(&s1d15605fb_driver);
8943 +}
8944 +
8945 +
8946 +static void __exit s1d15605fb_exit(void)
8947 +{
8948 +       platform_driver_unregister(&s1d15605fb_driver);
8949 +}
8950 +
8951 +
8952 +module_init(s1d15605fb_init);
8953 +module_exit(s1d15605fb_exit);
8954 +
8955 +
8956 +MODULE_AUTHOR("KwikByte");
8957 +MODULE_DESCRIPTION("Epson S1D15605 LCD Controller framebuffer driver");
8958 +MODULE_LICENSE("GPL");
8959 Index: linux-2.6.21.7/include/asm-arm/arch-at91/at91_adc.h
8960 ===================================================================
8961 --- /dev/null
8962 +++ linux-2.6.21.7/include/asm-arm/arch-at91/at91_adc.h
8963 @@ -0,0 +1,61 @@
8964 +/*
8965 + * include/asm-arm/arch-at91/at91_adc.h
8966 + *
8967 + * Copyright (C) SAN People
8968 + *
8969 + * Analog-to-Digital Converter (ADC) registers.
8970 + * Based on AT91SAM9260 datasheet revision D.
8971 + *
8972 + * This program is free software; you can redistribute it and/or modify
8973 + * it under the terms of the GNU General Public License as published by
8974 + * the Free Software Foundation; either version 2 of the License, or
8975 + * (at your option) any later version.
8976 + */
8977 +
8978 +#ifndef AT91_ADC_H
8979 +#define AT91_ADC_H
8980 +
8981 +#define AT91_ADC_CR            0x00            /* Control Register */
8982 +#define                AT91_ADC_SWRST          (1 << 0)        /* Software Reset */
8983 +#define                AT91_ADC_START          (1 << 1)        /* Start Conversion */
8984 +
8985 +#define AT91_ADC_MR            0x04            /* Mode Register */
8986 +#define                AT91_ADC_TRGEN          (1 << 0)        /* Trigger Enable */
8987 +#define                AT91_ADC_TRGSEL         (7 << 1)        /* Trigger Selection */
8988 +#define                        AT91_ADC_TRGSEL_TC0             (0 << 1)
8989 +#define                        AT91_ADC_TRGSEL_TC1             (1 << 1)
8990 +#define                        AT91_ADC_TRGSEL_TC2             (2 << 1)
8991 +#define                        AT91_ADC_TRGSEL_EXTERNAL        (6 << 1)
8992 +#define                AT91_ADC_LOWRES         (1 << 4)        /* Low Resolution */
8993 +#define                AT91_ADC_SLEEP          (1 << 5)        /* Sleep Mode */
8994 +#define                AT91_ADC_PRESCAL        (0x3f << 8)     /* Prescalar Rate Selection */
8995 +#define                        AT91_ADC_PRESCAL_(x)    ((x) << 8)
8996 +#define                AT91_ADC_STARTUP        (0x1f << 16)    /* Startup Up Time */
8997 +#define                        AT91_ADC_STARTUP_(x)    ((x) << 16)
8998 +#define                AT91_ADC_SHTIM          (0xf  << 24)    /* Sample & Hold Time */
8999 +#define                        AT91_ADC_SHTIM_(x)      ((x) << 24)
9000 +
9001 +#define AT91_ADC_CHER          0x10            /* Channel Enable Register */
9002 +#define AT91_ADC_CHDR          0x14            /* Channel Disable Register */
9003 +#define AT91_ADC_CHSR          0x18            /* Channel Status Register */
9004 +#define                AT91_ADC_CH(n)          (1 << (n))      /* Channel Number */
9005 +
9006 +#define AT91_ADC_SR            0x1C            /* Status Register */
9007 +#define                AT91_ADC_EOC(n)         (1 << (n))      /* End of Conversion on Channel N */
9008 +#define                AT91_ADC_OVRE(n)        (1 << ((n) + 8))/* Overrun Error on Channel N */
9009 +#define                AT91_ADC_DRDY           (1 << 16)       /* Data Ready */
9010 +#define                AT91_ADC_GOVRE          (1 << 17)       /* General Overrun Error */
9011 +#define                AT91_ADC_ENDRX          (1 << 18)       /* End of RX Buffer */
9012 +#define                AT91_ADC_RXFUFF         (1 << 19)       /* RX Buffer Full */
9013 +
9014 +#define AT91_ADC_LCDR          0x20            /* Last Converted Data Register */
9015 +#define                AT91_ADC_LDATA          (0x3ff)
9016 +
9017 +#define AT91_ADC_IER           0x24            /* Interrupt Enable Register */
9018 +#define AT91_ADC_IDR           0x28            /* Interrupt Disable Register */
9019 +#define AT91_ADC_IMR           0x2C            /* Interrupt Mask Register */
9020 +
9021 +#define AT91_ADC_CHR(n)                (0x30 + ((n) * 4)       /* Channel Data Register N */
9022 +#define                AT91_ADC_DATA           (0x3ff)
9023 +
9024 +#endif
9025 Index: linux-2.6.21.7/include/asm-arm/arch-at91/at91_mci.h
9026 ===================================================================
9027 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/at91_mci.h
9028 +++ linux-2.6.21.7/include/asm-arm/arch-at91/at91_mci.h
9029 @@ -26,6 +26,9 @@
9030  #define AT91_MCI_MR            0x04            /* Mode Register */
9031  #define                AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
9032  #define                AT91_MCI_PWSDIV         (7     <<  8)   /* Power Saving Divider */
9033 +#define                AT91_MCI_RDPROOF        (1     << 11)   /* Read Proof Enable [SAM926[03] only] */
9034 +#define                AT91_MCI_WRPROOF        (1     << 12)   /* Write Proof Enable [SAM926[03] only] */
9035 +#define                AT91_MCI_PDCFBYTE       (1     << 13)   /* PDC Force Byte Transfer [SAM926[03] only] */
9036  #define                AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
9037  #define                AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
9038  #define                AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
9039 Index: linux-2.6.21.7/include/asm-arm/arch-at91/at91_pmc.h
9040 ===================================================================
9041 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/at91_pmc.h
9042 +++ linux-2.6.21.7/include/asm-arm/arch-at91/at91_pmc.h
9043 @@ -37,7 +37,9 @@
9044  #define        AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
9045  #define        AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
9046
9047 -#define        AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register */
9048 +#define AT91_CKGR_UCKR         (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL only] */
9049 +
9050 +#define        AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
9051  #define                AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
9052  #define                AT91_PMC_OSCBYPASS      (1    << 1)             /* Oscillator Bypass [AT91SAM926x only] */
9053  #define                AT91_PMC_OSCOUNT        (0xff << 8)             /* Main Oscillator Start-up Time */
9054 Index: linux-2.6.21.7/include/asm-arm/arch-at91/at91rm9200.h
9055 ===================================================================
9056 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/at91rm9200.h
9057 +++ linux-2.6.21.7/include/asm-arm/arch-at91/at91rm9200.h
9058 @@ -107,185 +107,4 @@
9059  #define AT91RM9200_UHP_BASE    0x00300000      /* USB Host controller */
9060
9061
9062 -#if 0
9063 -/*
9064 - * PIO pin definitions (peripheral A/B multiplexing).
9065 - */
9066 -#define AT91_PA0_MISO          (1 <<  0)       /* A: SPI Master-In Slave-Out */
9067 -#define AT91_PA0_PCK3          (1 <<  0)       /* B: PMC Programmable Clock Output 3 */
9068 -#define AT91_PA1_MOSI          (1 <<  1)       /* A: SPI Master-Out Slave-In */
9069 -#define AT91_PA1_PCK0          (1 <<  1)       /* B: PMC Programmable Clock Output 0 */
9070 -#define AT91_PA2_SPCK          (1 <<  2)       /* A: SPI Serial Clock */
9071 -#define AT91_PA2_IRQ4          (1 <<  2)       /* B: External Interrupt 4 */
9072 -#define AT91_PA3_NPCS0         (1 <<  3)       /* A: SPI Peripheral Chip Select 0 */
9073 -#define AT91_PA3_IRQ5          (1 <<  3)       /* B: External Interrupt 5 */
9074 -#define AT91_PA4_NPCS1         (1 <<  4)       /* A: SPI Peripheral Chip Select 1 */
9075 -#define AT91_PA4_PCK1          (1 <<  4)       /* B: PMC Programmable Clock Output 1 */
9076 -#define AT91_PA5_NPCS2         (1 <<  5)       /* A: SPI Peripheral Chip Select 2 */
9077 -#define AT91_PA5_TXD3          (1 <<  5)       /* B: USART Transmit Data 3 */
9078 -#define AT91_PA6_NPCS3         (1 <<  6)       /* A: SPI Peripheral Chip Select 3 */
9079 -#define AT91_PA6_RXD3          (1 <<  6)       /* B: USART Receive Data 3 */
9080 -#define AT91_PA7_ETXCK_EREFCK  (1 <<  7)       /* A: Ethernet Reference Clock / Transmit Clock */
9081 -#define AT91_PA7_PCK2          (1 <<  7)       /* B: PMC Programmable Clock Output 2 */
9082 -#define AT91_PA8_ETXEN         (1 <<  8)       /* A: Ethernet Transmit Enable */
9083 -#define AT91_PA8_MCCDB         (1 <<  8)       /* B: MMC Multimedia Card B Command */
9084 -#define AT91_PA9_ETX0          (1 <<  9)       /* A: Ethernet Transmit Data 0 */
9085 -#define AT91_PA9_MCDB0         (1 <<  9)       /* B: MMC Multimedia Card B Data 0 */
9086 -#define AT91_PA10_ETX1         (1 << 10)       /* A: Ethernet Transmit Data 1 */
9087 -#define AT91_PA10_MCDB1                (1 << 10)       /* B: MMC Multimedia Card B Data 1 */
9088 -#define AT91_PA11_ECRS_ECRSDV  (1 << 11)       /* A: Ethernet Carrier Sense / Data Valid */
9089 -#define AT91_PA11_MCDB2                (1 << 11)       /* B: MMC Multimedia Card B Data 2 */
9090 -#define AT91_PA12_ERX0         (1 << 12)       /* A: Ethernet Receive Data 0 */
9091 -#define AT91_PA12_MCDB3                (1 << 12)       /* B: MMC Multimedia Card B Data 3 */
9092 -#define AT91_PA13_ERX1         (1 << 13)       /* A: Ethernet Receive Data 1 */
9093 -#define AT91_PA13_TCLK0                (1 << 13)       /* B: TC External Clock Input 0 */
9094 -#define AT91_PA14_ERXER                (1 << 14)       /* A: Ethernet Receive Error */
9095 -#define AT91_PA14_TCLK1                (1 << 14)       /* B: TC External Clock Input 1 */
9096 -#define AT91_PA15_EMDC         (1 << 15)       /* A: Ethernet Management Data Clock */
9097 -#define AT91_PA15_TCLK2                (1 << 15)       /* B: TC External Clock Input 2 */
9098 -#define AT91_PA16_EMDIO                (1 << 16)       /* A: Ethernet Management Data I/O */
9099 -#define AT91_PA16_IRQ6         (1 << 16)       /* B: External Interrupt 6 */
9100 -#define AT91_PA17_TXD0         (1 << 17)       /* A: USART Transmit Data 0 */
9101 -#define AT91_PA17_TIOA0                (1 << 17)       /* B: TC I/O Line A 0 */
9102 -#define AT91_PA18_RXD0         (1 << 18)       /* A: USART Receive Data 0 */
9103 -#define AT91_PA18_TIOB0                (1 << 18)       /* B: TC I/O Line B 0 */
9104 -#define AT91_PA19_SCK0         (1 << 19)       /* A: USART Serial Clock 0 */
9105 -#define AT91_PA19_TIOA1                (1 << 19)       /* B: TC I/O Line A 1 */
9106 -#define AT91_PA20_CTS0         (1 << 20)       /* A: USART Clear To Send 0 */
9107 -#define AT91_PA20_TIOB1                (1 << 20)       /* B: TC I/O Line B 1 */
9108 -#define AT91_PA21_RTS0         (1 << 21)       /* A: USART Ready To Send 0 */
9109 -#define AT91_PA21_TIOA2                (1 << 21)       /* B: TC I/O Line A 2 */
9110 -#define AT91_PA22_RXD2         (1 << 22)       /* A: USART Receive Data 2 */
9111 -#define AT91_PA22_TIOB2                (1 << 22)       /* B: TC I/O Line B 2 */
9112 -#define AT91_PA23_TXD2         (1 << 23)       /* A: USART Transmit Data 2 */
9113 -#define AT91_PA23_IRQ3         (1 << 23)       /* B: External Interrupt 3 */
9114 -#define AT91_PA24_SCK2         (1 << 24)       /* A: USART Serial Clock 2 */
9115 -#define AT91_PA24_PCK1         (1 << 24)       /* B: PMC Programmable Clock Output 1 */
9116 -#define AT91_PA25_TWD          (1 << 25)       /* A: TWI Two-wire Serial Data */
9117 -#define AT91_PA25_IRQ2         (1 << 25)       /* B: External Interrupt 2 */
9118 -#define AT91_PA26_TWCK         (1 << 26)       /* A: TWI Two-wire Serial Clock */
9119 -#define AT91_PA26_IRQ1         (1 << 26)       /* B: External Interrupt 1 */
9120 -#define AT91_PA27_MCCK         (1 << 27)       /* A: MMC Multimedia Card Clock */
9121 -#define AT91_PA27_TCLK3                (1 << 27)       /* B: TC External Clock Input 3 */
9122 -#define AT91_PA28_MCCDA                (1 << 28)       /* A: MMC Multimedia Card A Command */
9123 -#define AT91_PA28_TCLK4                (1 << 28)       /* B: TC External Clock Input 4 */
9124 -#define AT91_PA29_MCDA0                (1 << 29)       /* A: MMC Multimedia Card A Data 0 */
9125 -#define AT91_PA29_TCLK5                (1 << 29)       /* B: TC External Clock Input 5 */
9126 -#define AT91_PA30_DRXD         (1 << 30)       /* A: DBGU Receive Data */
9127 -#define AT91_PA30_CTS2         (1 << 30)       /* B: USART Clear To Send 2 */
9128 -#define AT91_PA31_DTXD         (1 << 31)       /* A: DBGU Transmit Data */
9129 -#define AT91_PA31_RTS2         (1 << 31)       /* B: USART Ready To Send 2 */
9130 -
9131 -#define AT91_PB0_TF0           (1 <<  0)       /* A: SSC Transmit Frame Sync 0 */
9132 -#define AT91_PB0_RTS3          (1 <<  0)       /* B: USART Ready To Send 3 */
9133 -#define AT91_PB1_TK0           (1 <<  1)       /* A: SSC Transmit Clock 0 */
9134 -#define AT91_PB1_CTS3          (1 <<  1)       /* B: USART Clear To Send 3 */
9135 -#define AT91_PB2_TD0           (1 <<  2)       /* A: SSC Transmit Data 0 */
9136 -#define AT91_PB2_SCK3          (1 <<  2)       /* B: USART Serial Clock 3 */
9137 -#define AT91_PB3_RD0           (1 <<  3)       /* A: SSC Receive Data 0 */
9138 -#define AT91_PB3_MCDA1         (1 <<  3)       /* B: MMC Multimedia Card A Data 1 */
9139 -#define AT91_PB4_RK0           (1 <<  4)       /* A: SSC Receive Clock 0 */
9140 -#define AT91_PB4_MCDA2         (1 <<  4)       /* B: MMC Multimedia Card A Data 2 */
9141 -#define AT91_PB5_RF0           (1 <<  5)       /* A: SSC Receive Frame Sync 0 */
9142 -#define AT91_PB5_MCDA3         (1 <<  5)       /* B: MMC Multimedia Card A Data 3 */
9143 -#define AT91_PB6_TF1           (1 <<  6)       /* A: SSC Transmit Frame Sync 1 */
9144 -#define AT91_PB6_TIOA3         (1 <<  6)       /* B: TC I/O Line A 3 */
9145 -#define AT91_PB7_TK1           (1 <<  7)       /* A: SSC Transmit Clock 1 */
9146 -#define AT91_PB7_TIOB3         (1 <<  7)       /* B: TC I/O Line B 3 */
9147 -#define AT91_PB8_TD1           (1 <<  8)       /* A: SSC Transmit Data 1 */
9148 -#define AT91_PB8_TIOA4         (1 <<  8)       /* B: TC I/O Line A 4 */
9149 -#define AT91_PB9_RD1           (1 <<  9)       /* A: SSC Receive Data 1 */
9150 -#define AT91_PB9_TIOB4         (1 <<  9)       /* B: TC I/O Line B 4 */
9151 -#define AT91_PB10_RK1          (1 << 10)       /* A: SSC Receive Clock 1 */
9152 -#define AT91_PB10_TIOA5                (1 << 10)       /* B: TC I/O Line A 5 */
9153 -#define AT91_PB11_RF1          (1 << 11)       /* A: SSC Receive Frame Sync 1 */
9154 -#define AT91_PB11_TIOB5                (1 << 11)       /* B: TC I/O Line B 5 */
9155 -#define AT91_PB12_TF2          (1 << 12)       /* A: SSC Transmit Frame Sync 2 */
9156 -#define AT91_PB12_ETX2         (1 << 12)       /* B: Ethernet Transmit Data 2 */
9157 -#define AT91_PB13_TK2          (1 << 13)       /* A: SSC Transmit Clock 3 */
9158 -#define AT91_PB13_ETX3         (1 << 13)       /* B: Ethernet Transmit Data 3 */
9159 -#define AT91_PB14_TD2          (1 << 14)       /* A: SSC Transmit Data 2 */
9160 -#define AT91_PB14_ETXER                (1 << 14)       /* B: Ethernet Transmit Coding Error */
9161 -#define AT91_PB15_RD2          (1 << 15)       /* A: SSC Receive Data 2 */
9162 -#define AT91_PB15_ERX2         (1 << 15)       /* B: Ethernet Receive Data 2 */
9163 -#define AT91_PB16_RK2          (1 << 16)       /* A: SSC Receive Clock 2 */
9164 -#define AT91_PB16_ERX3         (1 << 16)       /* B: Ethernet Receive Data 3 */
9165 -#define AT91_PB17_RF2          (1 << 17)       /* A: SSC Receive Frame Sync 2 */
9166 -#define AT91_PB17_ERXDV                (1 << 17)       /* B: Ethernet Receive Data Valid */
9167 -#define AT91_PB18_RI1          (1 << 18)       /* A: USART Ring Indicator 1 */
9168 -#define AT91_PB18_ECOL         (1 << 18)       /* B: Ethernet Collision Detected */
9169 -#define AT91_PB19_DTR1         (1 << 19)       /* A: USART Data Terminal Ready 1 */
9170 -#define AT91_PB19_ERXCK                (1 << 19)       /* B: Ethernet Receive Clock */
9171 -#define AT91_PB20_TXD1         (1 << 20)       /* A: USART Transmit Data 1 */
9172 -#define AT91_PB21_RXD1         (1 << 21)       /* A: USART Receive Data 1 */
9173 -#define AT91_PB22_SCK1         (1 << 22)       /* A: USART Serial Clock 1 */
9174 -#define AT91_PB23_DCD1         (1 << 23)       /* A: USART Data Carrier Detect 1 */
9175 -#define AT91_PB24_CTS1         (1 << 24)       /* A: USART Clear To Send 1 */
9176 -#define AT91_PB25_DSR1         (1 << 25)       /* A: USART Data Set Ready 1 */
9177 -#define AT91_PB25_EF100                (1 << 25)       /* B: Ethernet Force 100 Mbit */
9178 -#define AT91_PB26_RTS1         (1 << 26)       /* A: USART Ready To Send 1 */
9179 -#define AT91_PB27_PCK0         (1 << 27)       /* B: PMC Programmable Clock Output 0 */
9180 -#define AT91_PB28_FIQ          (1 << 28)       /* A: Fast Interrupt */
9181 -#define AT91_PB29_IRQ0         (1 << 29)       /* A: External Interrupt 0 */
9182 -
9183 -#define AT91_PC0_BFCK          (1 <<  0)       /* A: Burst Flash Clock */
9184 -#define AT91_PC1_BFRDY_SMOE    (1 <<  1)       /* A: Burst Flash Ready / SmartMedia Output Enable */
9185 -#define AT91_PC2_BFAVD         (1 <<  2)       /* A: Burst Flash Address Valid */
9186 -#define AT91_PC3_BFBAA_SMWE    (1 <<  3)       /* A: Burst Flash Address Advance / SmartMedia Write Enable */
9187 -#define AT91_PC4_BFOE          (1 <<  4)       /* A: Burst Flash Output Enable */
9188 -#define AT91_PC5_BFWE          (1 <<  5)       /* A: Burst Flash Write Enable */
9189 -#define AT91_PC6_NWAIT         (1 <<  6)       /* A: SMC Wait Signal */
9190 -#define AT91_PC7_A23           (1 <<  7)       /* A: Address Bus 23 */
9191 -#define AT91_PC8_A24           (1 <<  8)       /* A: Address Bus 24 */
9192 -#define AT91_PC9_A25_CFRNW     (1 <<  9)       /* A: Address Bus 25 / Compact Flash Read Not Write */
9193 -#define AT91_PC10_NCS4_CFCS    (1 << 10)       /* A: SMC Chip Select 4 / Compact Flash Chip Select */
9194 -#define AT91_PC11_NCS5_CFCE1   (1 << 11)       /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
9195 -#define AT91_PC12_NCS6_CFCE2   (1 << 12)       /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
9196 -#define AT91_PC13_NCS7         (1 << 13)       /* A: Chip Select 7 */
9197 -
9198 -#define AT91_PD0_ETX0          (1 <<  0)       /* A: Ethernet Transmit Data 0 */
9199 -#define AT91_PD1_ETX1          (1 <<  1)       /* A: Ethernet Transmit Data 1 */
9200 -#define AT91_PD2_ETX2          (1 <<  2)       /* A: Ethernet Transmit Data 2 */
9201 -#define AT91_PD3_ETX3          (1 <<  3)       /* A: Ethernet Transmit Data 3 */
9202 -#define AT91_PD4_ETXEN         (1 <<  4)       /* A: Ethernet Transmit Enable */
9203 -#define AT91_PD5_ETXER         (1 <<  5)       /* A: Ethernet Transmit Coding Error */
9204 -#define AT91_PD6_DTXD          (1 <<  6)       /* A: DBGU Transmit Data */
9205 -#define AT91_PD7_PCK0          (1 <<  7)       /* A: PMC Programmable Clock Output 0 */
9206 -#define AT91_PD7_TSYNC         (1 <<  7)       /* B: ETM Trace Synchronization Signal */
9207 -#define AT91_PD8_PCK1          (1 <<  8)       /* A: PMC Programmable Clock Output 1 */
9208 -#define AT91_PD8_TCLK          (1 <<  8)       /* B: ETM Trace Clock */
9209 -#define AT91_PD9_PCK2          (1 <<  9)       /* A: PMC Programmable Clock Output 2 */
9210 -#define AT91_PD9_TPS0          (1 <<  9)       /* B: ETM Trace ARM Pipeline Status 0 */
9211 -#define AT91_PD10_PCK3         (1 << 10)       /* A: PMC Programmable Clock Output 3 */
9212 -#define AT91_PD10_TPS1         (1 << 10)       /* B: ETM Trace ARM Pipeline Status 1 */
9213 -#define AT91_PD11_TPS2         (1 << 11)       /* B: ETM Trace ARM Pipeline Status 2 */
9214 -#define AT91_PD12_TPK0         (1 << 12)       /* B: ETM Trace Packet Port 0 */
9215 -#define AT91_PD13_TPK1         (1 << 13)       /* B: ETM Trace Packet Port 1 */
9216 -#define AT91_PD14_TPK2         (1 << 14)       /* B: ETM Trace Packet Port 2 */
9217 -#define AT91_PD15_TD0          (1 << 15)       /* A: SSC Transmit Data 0 */
9218 -#define AT91_PD15_TPK3         (1 << 15)       /* B: ETM Trace Packet Port 3 */
9219 -#define AT91_PD16_TD1          (1 << 16)       /* A: SSC Transmit Data 1 */
9220 -#define AT91_PD16_TPK4         (1 << 16)       /* B: ETM Trace Packet Port 4 */
9221 -#define AT91_PD17_TD2          (1 << 17)       /* A: SSC Transmit Data 2 */
9222 -#define AT91_PD17_TPK5         (1 << 17)       /* B: ETM Trace Packet Port 5 */
9223 -#define AT91_PD18_NPCS1                (1 << 18)       /* A: SPI Peripheral Chip Select 1 */
9224 -#define AT91_PD18_TPK6         (1 << 18)       /* B: ETM Trace Packet Port 6 */
9225 -#define AT91_PD19_NPCS2                (1 << 19)       /* A: SPI Peripheral Chip Select 2 */
9226 -#define AT91_PD19_TPK7         (1 << 19)       /* B: ETM Trace Packet Port 7 */
9227 -#define AT91_PD20_NPCS3                (1 << 20)       /* A: SPI Peripheral Chip Select 3 */
9228 -#define AT91_PD20_TPK8         (1 << 20)       /* B: ETM Trace Packet Port 8 */
9229 -#define AT91_PD21_RTS0         (1 << 21)       /* A: USART Ready To Send 0 */
9230 -#define AT91_PD21_TPK9         (1 << 21)       /* B: ETM Trace Packet Port 9 */
9231 -#define AT91_PD22_RTS1         (1 << 22)       /* A: USART Ready To Send 1 */
9232 -#define AT91_PD22_TPK10                (1 << 22)       /* B: ETM Trace Packet Port 10 */
9233 -#define AT91_PD23_RTS2         (1 << 23)       /* A: USART Ready To Send 2 */
9234 -#define AT91_PD23_TPK11                (1 << 23)       /* B: ETM Trace Packet Port 11 */
9235 -#define AT91_PD24_RTS3         (1 << 24)       /* A: USART Ready To Send 3 */
9236 -#define AT91_PD24_TPK12                (1 << 24)       /* B: ETM Trace Packet Port 12 */
9237 -#define AT91_PD25_DTR1         (1 << 25)       /* A: USART Data Terminal Ready 1 */
9238 -#define AT91_PD25_TPK13                (1 << 25)       /* B: ETM Trace Packet Port 13 */
9239 -#define AT91_PD26_TPK14                (1 << 26)       /* B: ETM Trace Packet Port 14 */
9240 -#define AT91_PD27_TPK15                (1 << 27)       /* B: ETM Trace Packet Port 15 */
9241 -#endif
9242 -
9243  #endif
9244 Index: linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9260.h
9245 ===================================================================
9246 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/at91sam9260.h
9247 +++ linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9260.h
9248 @@ -117,13 +117,4 @@
9249  #define AT91SAM9XE_SRAM_BASE   0x00300000      /* Internal SRAM base address */
9250
9251
9252 -#if 0
9253 -/*
9254 - * PIO pin definitions (peripheral A/B multiplexing).
9255 - */
9256 -
9257 -// TODO: Add
9258 -
9259 -#endif
9260 -
9261  #endif
9262 Index: linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9260_matrix.h
9263 ===================================================================
9264 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/at91sam9260_matrix.h
9265 +++ linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9260_matrix.h
9266 @@ -67,7 +67,7 @@
9267  #define                AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
9268  #define                        AT91_MATRIX_CS4A_SMC            (0 << 4)
9269  #define                        AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
9270 -#define                AT91_MATRIX_CS5A                (1 << 5 )       /* Chip Select 5 Assignment */
9271 +#define                AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
9272  #define                        AT91_MATRIX_CS5A_SMC            (0 << 5)
9273  #define                        AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
9274  #define                AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
9275 Index: linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9261.h
9276 ===================================================================
9277 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/at91sam9261.h
9278 +++ linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9261.h
9279 @@ -98,195 +98,4 @@
9280  #define AT91SAM9261_LCDC_BASE  0x00600000      /* LDC controller */
9281
9282
9283 -#if 0
9284 -/*
9285 - * PIO pin definitions (peripheral A/B multiplexing).
9286 - */
9287 -#define AT91_PA0_SPI0_MISO     (1 <<  0)       /* A: SPI0 Master In Slave */
9288 -#define AT91_PA0_MCDA0         (1 <<  0)       /* B: Multimedia Card A Data 0 */
9289 -#define AT91_PA1_SPI0_MOSI     (1 <<  1)       /* A: SPI0 Master Out Slave */
9290 -#define AT91_PA1_MCCDA         (1 <<  1)       /* B: Multimedia Card A Command */
9291 -#define AT91_PA2_SPI0_SPCK     (1 <<  2)       /* A: SPI0 Serial Clock */
9292 -#define AT91_PA2_MCCK          (1 <<  2)       /* B: Multimedia Card Clock */
9293 -#define AT91_PA3_SPI0_NPCS0    (1 <<  3)       /* A: SPI0 Peripheral Chip Select 0 */
9294 -#define AT91_PA4_SPI0_NPCS1    (1 <<  4)       /* A: SPI0 Peripheral Chip Select 1 */
9295 -#define AT91_PA4_MCDA1         (1 <<  4)       /* B: Multimedia Card A Data 1 */
9296 -#define AT91_PA5_SPI0_NPCS2    (1 <<  5)       /* A: SPI0 Peripheral Chip Select 2 */
9297 -#define AT91_PA5_MCDA2         (1 <<  5)       /* B: Multimedia Card A Data 2 */
9298 -#define AT91_PA6_SPI0_NPCS3    (1 <<  6)       /* A: SPI0 Peripheral Chip Select 3 */
9299 -#define AT91_PA6_MCDA3         (1 <<  6)       /* B: Multimedia Card A Data 3 */
9300 -#define AT91_PA7_TWD           (1 <<  7)       /* A: TWI Two-wire Serial Data */
9301 -#define AT91_PA7_PCK0          (1 <<  7)       /* B: PMC Programmable clock Output 0 */
9302 -#define AT91_PA8_TWCK          (1 <<  8)       /* A: TWI Two-wire Serial Clock */
9303 -#define AT91_PA8_PCK1          (1 <<  8)       /* B: PMC Programmable clock Output 1 */
9304 -#define AT91_PA9_DRXD          (1 <<  9)       /* A: DBGU Debug Receive Data */
9305 -#define AT91_PA9_PCK2          (1 <<  9)       /* B: PMC Programmable clock Output 2 */
9306 -#define AT91_PA10_DTXD         (1 << 10)       /* A: DBGU Debug Transmit Data */
9307 -#define AT91_PA10_PCK3         (1 << 10)       /* B: PMC Programmable clock Output 3 */
9308 -#define AT91_PA11_TSYNC                (1 << 11)       /* A: Trace Synchronization Signal */
9309 -#define AT91_PA11_SCK1         (1 << 11)       /* B: USART1 Serial Clock */
9310 -#define AT91_PA12_TCLK         (1 << 12)       /* A: Trace Clock */
9311 -#define AT91_PA12_RTS1         (1 << 12)       /* B: USART1 Ready To Send */
9312 -#define AT91_PA13_TPS0         (1 << 13)       /* A: Trace ARM Pipeline Status 0 */
9313 -#define AT91_PA13_CTS1         (1 << 13)       /* B: USART1 Clear To Send */
9314 -#define AT91_PA14_TPS1         (1 << 14)       /* A: Trace ARM Pipeline Status 1 */
9315 -#define AT91_PA14_SCK2         (1 << 14)       /* B: USART2 Serial Clock */
9316 -#define AT91_PA15_TPS2         (1 << 15)       /* A: Trace ARM Pipeline Status 2 */
9317 -#define AT91_PA15_RTS2         (1 << 15)       /* B: USART2 Ready To Send */
9318 -#define AT91_PA16_TPK0         (1 << 16)       /* A: Trace Packet Port 0 */
9319 -#define AT91_PA16_CTS2         (1 << 16)       /* B: USART2 Clear To Send */
9320 -#define AT91_PA17_TPK1         (1 << 17)       /* A: Trace Packet Port 1 */
9321 -#define AT91_PA17_TF1          (1 << 17)       /* B: SSC1 Transmit Frame Sync */
9322 -#define AT91_PA18_TPK2         (1 << 18)       /* A: Trace Packet Port 2 */
9323 -#define AT91_PA18_TK1          (1 << 18)       /* B: SSC1 Transmit Clock */
9324 -#define AT91_PA19_TPK3         (1 << 19)       /* A: Trace Packet Port 3 */
9325 -#define AT91_PA19_TD1          (1 << 19)       /* B: SSC1 Transmit Data */
9326 -#define AT91_PA20_TPK4         (1 << 20)       /* A: Trace Packet Port 4 */
9327 -#define AT91_PA20_RD1          (1 << 20)       /* B: SSC1 Receive Data */
9328 -#define AT91_PA21_TPK5         (1 << 21)       /* A: Trace Packet Port 5 */
9329 -#define AT91_PA21_RK1          (1 << 21)       /* B: SSC1 Receive Clock */
9330 -#define AT91_PA22_TPK6         (1 << 22)       /* A: Trace Packet Port 6 */
9331 -#define AT91_PA22_RF1          (1 << 22)       /* B: SSC1 Receive Frame Sync */
9332 -#define AT91_PA23_TPK7         (1 << 23)       /* A: Trace Packet Port 7 */
9333 -#define AT91_PA23_RTS0         (1 << 23)       /* B: USART0 Ready To Send */
9334 -#define AT91_PA24_TPK8         (1 << 24)       /* A: Trace Packet Port 8 */
9335 -#define AT91_PA24_SPI1_NPCS1   (1 << 24)       /* B: SPI1 Peripheral Chip Select 1 */
9336 -#define AT91_PA25_TPK9         (1 << 25)       /* A: Trace Packet Port 9 */
9337 -#define AT91_PA25_SPI1_NPCS2   (1 << 25)       /* B: SPI1 Peripheral Chip Select 2 */
9338 -#define AT91_PA26_TPK10                (1 << 26)       /* A: Trace Packet Port 10 */
9339 -#define AT91_PA26_SPI1_NPCS3   (1 << 26)       /* B: SPI1 Peripheral Chip Select 3 */
9340 -#define AT91_PA27_TPK11                (1 << 27)       /* A: Trace Packet Port 11 */
9341 -#define AT91_PA27_SPI0_NPCS1   (1 << 27)       /* B: SPI0 Peripheral Chip Select 1 */
9342 -#define AT91_PA28_TPK12                (1 << 28)       /* A: Trace Packet Port 12 */
9343 -#define AT91_PA28_SPI0_NPCS2   (1 << 28)       /* B: SPI0 Peripheral Chip Select 2 */
9344 -#define AT91_PA29_TPK13                (1 << 29)       /* A: Trace Packet Port 13 */
9345 -#define AT91_PA29_SPI0_NPCS3   (1 << 29)       /* B: SPI0 Peripheral Chip Select 3 */
9346 -#define AT91_PA30_TPK14                (1 << 30)       /* A: Trace Packet Port 14 */
9347 -#define AT91_PA30_A23          (1 << 30)       /* B: Address Bus bit 23 */
9348 -#define AT91_PA31_TPK15                (1 << 31)       /* A: Trace Packet Port 15 */
9349 -#define AT91_PA31_A24          (1 << 31)       /* B: Address Bus bit 24 */
9350 -
9351 -#define AT91_PB0_LCDVSYNC      (1 <<  0)       /* A: LCD Vertical Synchronization */
9352 -#define AT91_PB1_LCDHSYNC      (1 <<  1)       /* A: LCD Horizontal Synchronization */
9353 -#define AT91_PB2_LCDDOTCK      (1 <<  2)       /* A: LCD Dot Clock */
9354 -#define AT91_PB2_PCK0          (1 <<  2)       /* B: PMC Programmable clock Output 0 */
9355 -#define AT91_PB3_LCDDEN                (1 <<  3)       /* A: LCD Data Enable */
9356 -#define AT91_PB4_LCDCC         (1 <<  4)       /* A: LCD Contrast Control */
9357 -#define AT91_PB4_LCDD2         (1 <<  4)       /* B: LCD Data Bus Bit 2 */
9358 -#define AT91_PB5_LCDD0         (1 <<  5)       /* A: LCD Data Bus Bit 0 */
9359 -#define AT91_PB5_LCDD3         (1 <<  5)       /* B: LCD Data Bus Bit 3 */
9360 -#define AT91_PB6_LCDD1         (1 <<  6)       /* A: LCD Data Bus Bit 1 */
9361 -#define AT91_PB6_LCDD4         (1 <<  6)       /* B: LCD Data Bus Bit 4 */
9362 -#define AT91_PB7_LCDD2         (1 <<  7)       /* A: LCD Data Bus Bit 2 */
9363 -#define AT91_PB7_LCDD5         (1 <<  7)       /* B: LCD Data Bus Bit 5 */
9364 -#define AT91_PB8_LCDD3         (1 <<  8)       /* A: LCD Data Bus Bit 3 */
9365 -#define AT91_PB8_LCDD6         (1 <<  8)       /* B: LCD Data Bus Bit 6 */
9366 -#define AT91_PB9_LCDD4         (1 <<  9)       /* A: LCD Data Bus Bit 4 */
9367 -#define AT91_PB9_LCDD7         (1 <<  9)       /* B: LCD Data Bus Bit 7 */
9368 -#define AT91_PB10_LCDD5                (1 << 10)       /* A: LCD Data Bus Bit 5 */
9369 -#define AT91_PB10_LCDD10       (1 << 10)       /* B: LCD Data Bus Bit 10 */
9370 -#define AT91_PB11_LCDD6                (1 << 11)       /* A: LCD Data Bus Bit 6 */
9371 -#define AT91_PB11_LCDD11       (1 << 11)       /* B: LCD Data Bus Bit 11 */
9372 -#define AT91_PB12_LCDD7                (1 << 12)       /* A: LCD Data Bus Bit 7 */
9373 -#define AT91_PB12_LCDD12       (1 << 12)       /* B: LCD Data Bus Bit 12 */
9374 -#define AT91_PB13_LCDD8                (1 << 13)       /* A: LCD Data Bus Bit 8 */
9375 -#define AT91_PB13_LCDD13       (1 << 13)       /* B: LCD Data Bus Bit 13 */
9376 -#define AT91_PB14_LCDD9                (1 << 14)       /* A: LCD Data Bus Bit 9 */
9377 -#define AT91_PB14_LCDD14       (1 << 14)       /* B: LCD Data Bus Bit 14 */
9378 -#define AT91_PB15_LCDD10       (1 << 15)       /* A: LCD Data Bus Bit 10 */
9379 -#define AT91_PB15_LCDD15       (1 << 15)       /* B: LCD Data Bus Bit 15 */
9380 -#define AT91_PB16_LCDD11       (1 << 16)       /* A: LCD Data Bus Bit 11 */
9381 -#define AT91_PB16_LCDD19       (1 << 16)       /* B: LCD Data Bus Bit 19 */
9382 -#define AT91_PB17_LCDD12       (1 << 17)       /* A: LCD Data Bus Bit 12 */
9383 -#define AT91_PB17_LCDD20       (1 << 17)       /* B: LCD Data Bus Bit 20 */
9384 -#define AT91_PB18_LCDD13       (1 << 18)       /* A: LCD Data Bus Bit 13 */
9385 -#define AT91_PB18_LCDD21       (1 << 18)       /* B: LCD Data Bus Bit 21 */
9386 -#define AT91_PB19_LCDD14       (1 << 19)       /* A: LCD Data Bus Bit 14 */
9387 -#define AT91_PB19_LCDD22       (1 << 19)       /* B: LCD Data Bus Bit 22 */
9388 -#define AT91_PB20_LCDD15       (1 << 20)       /* A: LCD Data Bus Bit 15 */
9389 -#define AT91_PB20_LCDD23       (1 << 20)       /* B: LCD Data Bus Bit 23 */
9390 -#define AT91_PB21_TF0          (1 << 21)       /* A: SSC0 Transmit Frame Sync */
9391 -#define AT91_PB21_LCDD16       (1 << 21)       /* B: LCD Data Bus Bit 16 */
9392 -#define AT91_PB22_TK0          (1 << 22)       /* A: SSC0 Transmit Clock */
9393 -#define AT91_PB22_LCDD17       (1 << 22)       /* B: LCD Data Bus Bit 17 */
9394 -#define AT91_PB23_TD0          (1 << 23)       /* A: SSC0 Transmit Data */
9395 -#define AT91_PB23_LCDD18       (1 << 23)       /* B: LCD Data Bus Bit 18 */
9396 -#define AT91_PB24_RD0          (1 << 24)       /* A: SSC0 Receive Data */
9397 -#define AT91_PB24_LCDD19       (1 << 24)       /* B: LCD Data Bus Bit 19 */
9398 -#define AT91_PB25_RK0          (1 << 25)       /* A: SSC0 Receive Clock */
9399 -#define AT91_PB25_LCDD20       (1 << 25)       /* B: LCD Data Bus Bit 20 */
9400 -#define AT91_PB26_RF0          (1 << 26)       /* A: SSC0 Receive Frame Sync */
9401 -#define AT91_PB26_LCDD21       (1 << 26)       /* B: LCD Data Bus Bit 21 */
9402 -#define AT91_PB27_SPI1_NPCS1   (1 << 27)       /* A: SPI1 Peripheral Chip Select 1 */
9403 -#define AT91_PB27_LCDD22       (1 << 27)       /* B: LCD Data Bus Bit 22 */
9404 -#define AT91_PB28_SPI1_NPCS0   (1 << 28)       /* A: SPI1 Peripheral Chip Select 0 */
9405 -#define AT91_PB28_LCDD23       (1 << 28)       /* B: LCD Data Bus Bit 23 */
9406 -#define AT91_PB29_SPI1_SPCK    (1 << 29)       /* A: SPI1 Serial Clock */
9407 -#define AT91_PB29_IRQ2         (1 << 29)       /* B: Interrupt input 2 */
9408 -#define AT91_PB30_SPI1_MISO    (1 << 30)       /* A: SPI1 Master In Slave */
9409 -#define AT91_PB30_IRQ1         (1 << 30)       /* B: Interrupt input 1 */
9410 -#define AT91_PB31_SPI1_MOSI    (1 << 31)       /* A: SPI1 Master Out Slave */
9411 -#define AT91_PB31_PCK2         (1 << 31)       /* B: PMC Programmable clock Output 2 */
9412 -
9413 -#define AT91_PC0_SMOE          (1 << 0)        /* A: SmartMedia Output Enable */
9414 -#define AT91_PC0_NCS6          (1 << 0)        /* B: Chip Select 6 */
9415 -#define AT91_PC1_SMWE          (1 << 1)        /* A: SmartMedia Write Enable */
9416 -#define AT91_PC1_NCS7          (1 << 1)        /* B: Chip Select 7 */
9417 -#define AT91_PC2_NWAIT         (1 << 2)        /* A: NWAIT */
9418 -#define AT91_PC2_IRQ0          (1 << 2)        /* B: Interrupt input 0 */
9419 -#define AT91_PC3_A25_CFRNW     (1 << 3)        /* A: Address Bus[25] / Compact Flash Read Not Write */
9420 -#define AT91_PC4_NCS4_CFCS0    (1 << 4)        /* A: Chip Select 4 / CompactFlash Chip Select 0 */
9421 -#define AT91_PC5_NCS5_CFCS1    (1 << 5)        /* A: Chip Select 5 / CompactFlash Chip Select 1 */
9422 -#define AT91_PC6_CFCE1         (1 << 6)        /* A: CompactFlash Chip Enable 1 */
9423 -#define AT91_PC7_CFCE2         (1 << 7)        /* A: CompactFlash Chip Enable 2 */
9424 -#define AT91_PC8_TXD0          (1 << 8)        /* A: USART0 Transmit Data */
9425 -#define AT91_PC8_PCK2          (1 << 8)        /* B: PMC Programmable clock Output 2 */
9426 -#define AT91_PC9_RXD0          (1 << 9)        /* A: USART0 Receive Data */
9427 -#define AT91_PC9_PCK3          (1 << 9)        /* B: PMC Programmable clock Output 3 */
9428 -#define AT91_PC10_RTS0         (1 << 10)       /* A: USART0 Ready To Send */
9429 -#define AT91_PC10_SCK0         (1 << 10)       /* B: USART0 Serial Clock */
9430 -#define AT91_PC11_CTS0         (1 << 11)       /* A: USART0 Clear To Send */
9431 -#define AT91_PC11_FIQ          (1 << 11)       /* B: AIC Fast Interrupt Input */
9432 -#define AT91_PC12_TXD1         (1 << 12)       /* A: USART1 Transmit Data */
9433 -#define AT91_PC12_NCS6         (1 << 12)       /* B: Chip Select 6 */
9434 -#define AT91_PC13_RXD1         (1 << 13)       /* A: USART1 Receive Data */
9435 -#define AT91_PC13_NCS7         (1 << 13)       /* B: Chip Select 7 */
9436 -#define AT91_PC14_TXD2         (1 << 14)       /* A: USART2 Transmit Data */
9437 -#define AT91_PC14_SPI1_NPCS2   (1 << 14)       /* B: SPI1 Peripheral Chip Select 2 */
9438 -#define AT91_PC15_RXD2         (1 << 15)       /* A: USART2 Receive Data */
9439 -#define AT91_PC15_SPI1_NPCS3   (1 << 15)       /* B: SPI1 Peripheral Chip Select 3 */
9440 -#define AT91_PC16_D16          (1 << 16)       /* A: Data Bus [16] */
9441 -#define AT91_PC16_TCLK0                (1 << 16)       /* B: Timer Counter 0 external clock input */
9442 -#define AT91_PC17_D17          (1 << 17)       /* A: Data Bus [17] */
9443 -#define AT91_PC17_TCLK1                (1 << 17)       /* B: Timer Counter 1 external clock input */
9444 -#define AT91_PC18_D18          (1 << 18)       /* A: Data Bus [18] */
9445 -#define AT91_PC18_TCLK2                (1 << 18)       /* B: Timer Counter 2 external clock input */
9446 -#define AT91_PC19_D19          (1 << 19)       /* A: Data Bus [19] */
9447 -#define AT91_PC19_TIOA0                (1 << 19)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
9448 -#define AT91_PC20_D20          (1 << 20)       /* A: Data Bus [20] */
9449 -#define AT91_PC20_TIOB0                (1 << 20)       /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
9450 -#define AT91_PC21_D21          (1 << 21)       /* A: Data Bus [21] */
9451 -#define AT91_PC21_TIOA1                (1 << 21)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
9452 -#define AT91_PC22_D22          (1 << 22)       /* A: Data Bus [22] */
9453 -#define AT91_PC22_TIOB1                (1 << 22)       /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
9454 -#define AT91_PC23_D23          (1 << 23)       /* A: Data Bus [23] */
9455 -#define AT91_PC23_TIOA2                (1 << 23)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
9456 -#define AT91_PC24_D24          (1 << 24)       /* A: Data Bus [24] */
9457 -#define AT91_PC24_TIOB2                (1 << 24)       /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
9458 -#define AT91_PC25_D25          (1 << 25)       /* A: Data Bus [25] */
9459 -#define AT91_PC25_TF2          (1 << 25)       /* B: SSC2 Transmit Frame Sync */
9460 -#define AT91_PC26_D26          (1 << 26)       /* A: Data Bus [26] */
9461 -#define AT91_PC26_TK2          (1 << 26)       /* B: SSC2 Transmit Clock */
9462 -#define AT91_PC27_D27          (1 << 27)       /* A: Data Bus [27] */
9463 -#define AT91_PC27_TD2          (1 << 27)       /* B: SSC2 Transmit Data */
9464 -#define AT91_PC28_D28          (1 << 28)       /* A: Data Bus [28] */
9465 -#define AT91_PC28_RD2          (1 << 28)       /* B: SSC2 Receive Data */
9466 -#define AT91_PC29_D29          (1 << 29)       /* A: Data Bus [29] */
9467 -#define AT91_PC29_RK2          (1 << 29)       /* B: SSC2 Receive Clock */
9468 -#define AT91_PC30_D30          (1 << 30)       /* A: Data Bus [30] */
9469 -#define AT91_PC30_RF2          (1 << 30)       /* B: SSC2 Receive Frame Sync */
9470 -#define AT91_PC31_D31          (1 << 31)       /* A: Data Bus [31] */
9471 -#define AT91_PC31_PCK1         (1 << 31)       /* B: PMC Programmable clock Output 1 */
9472 -#endif
9473 -
9474  #endif
9475 Index: linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9263.h
9476 ===================================================================
9477 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/at91sam9263.h
9478 +++ linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9263.h
9479 @@ -119,13 +119,5 @@
9480  #define AT91SAM9263_DMAC_BASE  0x00800000      /* DMA Controller */
9481  #define AT91SAM9263_UHP_BASE   0x00a00000      /* USB Host controller */
9482
9483 -#if 0
9484 -/*
9485 - * PIO pin definitions (peripheral A/B multiplexing).
9486 - */
9487 -
9488 -// TODO: Add
9489 -
9490 -#endif
9491
9492  #endif
9493 Index: linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9rl.h
9494 ===================================================================
9495 --- /dev/null
9496 +++ linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9rl.h
9497 @@ -0,0 +1,110 @@
9498 +/*
9499 + * include/asm-arm/arch-at91/at91sam9260.h
9500 + *
9501 + *  Copyright (C) 2007 Atmel Corporation
9502 + *
9503 + * Common definitions.
9504 + * Based on AT91SAM9RL datasheet revision A. (Preliminary)
9505 + *
9506 + * This file is subject to the terms and conditions of the GNU General Public
9507 + * License.  See the file COPYING in the main directory of this archive for
9508 + * more details.
9509 + */
9510 +
9511 +#ifndef AT91SAM9RL_H
9512 +#define AT91SAM9RL_H
9513 +
9514 +/*
9515 + * Peripheral identifiers/interrupts.
9516 + */
9517 +#define AT91_ID_FIQ            0       /* Advanced Interrupt Controller (FIQ) */
9518 +#define AT91_ID_SYS            1       /* System Controller */
9519 +#define AT91SAM9RL_ID_PIOA     2       /* Parallel IO Controller A */
9520 +#define AT91SAM9RL_ID_PIOB     3       /* Parallel IO Controller B */
9521 +#define AT91SAM9RL_ID_PIOC     4       /* Parallel IO Controller C */
9522 +#define AT91SAM9RL_ID_PIOD     5       /* Parallel IO Controller D */
9523 +#define AT91SAM9RL_ID_US0      6       /* USART 0 */
9524 +#define AT91SAM9RL_ID_US1      7       /* USART 1 */
9525 +#define AT91SAM9RL_ID_US2      8       /* USART 2 */
9526 +#define AT91SAM9RL_ID_US3      9       /* USART 3 */
9527 +#define AT91SAM9RL_ID_MCI      10      /* Multimedia Card Interface */
9528 +#define AT91SAM9RL_ID_TWI0     11      /* TWI 0 */
9529 +#define AT91SAM9RL_ID_TWI1     12      /* TWI 1 */
9530 +#define AT91SAM9RL_ID_SPI      13      /* Serial Peripheral Interface */
9531 +#define AT91SAM9RL_ID_SSC0     14      /* Serial Synchronous Controller 0 */
9532 +#define AT91SAM9RL_ID_SSC1     15      /* Serial Synchronous Controller 1 */
9533 +#define AT91SAM9RL_ID_TC0      16      /* Timer Counter 0 */
9534 +#define AT91SAM9RL_ID_TC1      17      /* Timer Counter 1 */
9535 +#define AT91SAM9RL_ID_TC2      18      /* Timer Counter 2 */
9536 +#define AT91SAM9RL_ID_PWMC     19      /* Pulse Width Modulation Controller */
9537 +#define AT91SAM9RL_ID_TSC      20      /* Touch Screen Controller */
9538 +#define AT91SAM9RL_ID_DMA      21      /* DMA Controller */
9539 +#define AT91SAM9RL_ID_UDPHS    22      /* USB Device HS */
9540 +#define AT91SAM9RL_ID_LCDC     23      /* LCD Controller */
9541 +#define AT91SAM9RL_ID_AC97C    24      /* AC97 Controller */
9542 +#define AT91SAM9RL_ID_IRQ0     31      /* Advanced Interrupt Controller (IRQ0) */
9543 +
9544 +
9545 +/*
9546 + * User Peripheral physical base addresses.
9547 + */
9548 +#define AT91SAM9RL_BASE_TCB0   0xfffa0000
9549 +#define AT91SAM9RL_BASE_TC0    0xfffa0000
9550 +#define AT91SAM9RL_BASE_TC1    0xfffa0040
9551 +#define AT91SAM9RL_BASE_TC2    0xfffa0080
9552 +#define AT91SAM9RL_BASE_MCI    0xfffa4000
9553 +#define AT91SAM9RL_BASE_TWI0   0xfffa8000
9554 +#define AT91SAM9RL_BASE_TWI1   0xfffac000
9555 +#define AT91SAM9RL_BASE_US0    0xfffb0000
9556 +#define AT91SAM9RL_BASE_US1    0xfffb4000
9557 +#define AT91SAM9RL_BASE_US2    0xfffb8000
9558 +#define AT91SAM9RL_BASE_US3    0xfffbc000
9559 +#define AT91SAM9RL_BASE_SSC0   0xfffc0000
9560 +#define AT91SAM9RL_BASE_SSC1   0xfffc4000
9561 +#define AT91SAM9RL_BASE_PWMC   0xfffc8000
9562 +#define AT91SAM9RL_BASE_SPI    0xfffcc000
9563 +#define AT91SAM9RL_BASE_TSC    0xfffd0000
9564 +#define AT91SAM9RL_BASE_UDPHS  0xfffd4000
9565 +#define AT91SAM9RL_BASE_AC97C  0xfffd8000
9566 +#define AT91_BASE_SYS          0xffffc000
9567 +
9568 +
9569 +/*
9570 + * System Peripherals (offset from AT91_BASE_SYS)
9571 + */
9572 +#define AT91_DMA       (0xffffe600 - AT91_BASE_SYS)
9573 +#define AT91_ECC       (0xffffe800 - AT91_BASE_SYS)
9574 +#define AT91_SDRAMC    (0xffffea00 - AT91_BASE_SYS)
9575 +#define AT91_SMC       (0xffffec00 - AT91_BASE_SYS)
9576 +#define AT91_MATRIX    (0xffffee00 - AT91_BASE_SYS)
9577 +#define AT91_CCFG      (0xffffef10 - AT91_BASE_SYS)
9578 +#define AT91_AIC       (0xfffff000 - AT91_BASE_SYS)
9579 +#define AT91_DBGU      (0xfffff200 - AT91_BASE_SYS)
9580 +#define AT91_PIOA      (0xfffff400 - AT91_BASE_SYS)
9581 +#define AT91_PIOB      (0xfffff600 - AT91_BASE_SYS)
9582 +#define AT91_PIOC      (0xfffff800 - AT91_BASE_SYS)
9583 +#define AT91_PIOD      (0xfffffa00 - AT91_BASE_SYS)
9584 +#define AT91_PMC       (0xfffffc00 - AT91_BASE_SYS)
9585 +#define AT91_RSTC      (0xfffffd00 - AT91_BASE_SYS)
9586 +#define AT91_SHDWC     (0xfffffd10 - AT91_BASE_SYS)
9587 +#define AT91_RTT       (0xfffffd20 - AT91_BASE_SYS)
9588 +#define AT91_PIT       (0xfffffd30 - AT91_BASE_SYS)
9589 +#define AT91_WDT       (0xfffffd40 - AT91_BASE_SYS)
9590 +#define AT91_SCKCR     (0xfffffd50 - AT91_BASE_SYS)
9591 +#define AT91_GPBR      (0xfffffd60 - AT91_BASE_SYS)
9592 +#define AT91_RTC       (0xfffffe00 - AT91_BASE_SYS)
9593 +
9594 +
9595 +/*
9596 + * Internal Memory.
9597 + */
9598 +#define AT91SAM9RL_SRAM_BASE   0x00300000      /* Internal SRAM base address */
9599 +#define AT91SAM9RL_SRAM_SIZE   SZ_16K          /* Internal SRAM size (16Kb) */
9600 +
9601 +#define AT91SAM9RL_ROM_BASE    0x00400000      /* Internal ROM base address */
9602 +#define AT91SAM9RL_ROM_SIZE    (2 * SZ_16K)    /* Internal ROM size (32Kb) */
9603 +
9604 +#define AT91SAM9RL_LCDC_BASE   0x00500000      /* LCD Controller */
9605 +#define AT91SAM9RL_UDPHS_BASE  0x00600000      /* USB Device HS controller */
9606 +
9607 +#endif
9608 Index: linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9rl_matrix.h
9609 ===================================================================
9610 --- /dev/null
9611 +++ linux-2.6.21.7/include/asm-arm/arch-at91/at91sam9rl_matrix.h
9612 @@ -0,0 +1,96 @@
9613 +/*
9614 + * include/asm-arm/arch-at91/at91sam9rl_matrix.h
9615 + *
9616 + *  Copyright (C) 2007 Atmel Corporation
9617 + *
9618 + * Memory Controllers (MATRIX, EBI) - System peripherals registers.
9619 + * Based on AT91SAM9RL datasheet revision A. (Preliminary)
9620 + *
9621 + * This file is subject to the terms and conditions of the GNU General Public
9622 + * License.  See the file COPYING in the main directory of this archive for
9623 + * more details.
9624 + */
9625 +
9626 +#ifndef AT91SAM9RL_MATRIX_H
9627 +#define AT91SAM9RL_MATRIX_H
9628 +
9629 +#define AT91_MATRIX_MCFG0      (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
9630 +#define AT91_MATRIX_MCFG1      (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
9631 +#define AT91_MATRIX_MCFG2      (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
9632 +#define AT91_MATRIX_MCFG3      (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
9633 +#define AT91_MATRIX_MCFG4      (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
9634 +#define AT91_MATRIX_MCFG5      (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
9635 +#define                AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
9636 +#define                        AT91_MATRIX_ULBT_INFINITE       (0 << 0)
9637 +#define                        AT91_MATRIX_ULBT_SINGLE         (1 << 0)
9638 +#define                        AT91_MATRIX_ULBT_FOUR           (2 << 0)
9639 +#define                        AT91_MATRIX_ULBT_EIGHT          (3 << 0)
9640 +#define                        AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
9641 +
9642 +#define AT91_MATRIX_SCFG0      (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
9643 +#define AT91_MATRIX_SCFG1      (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
9644 +#define AT91_MATRIX_SCFG2      (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
9645 +#define AT91_MATRIX_SCFG3      (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
9646 +#define AT91_MATRIX_SCFG4      (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
9647 +#define AT91_MATRIX_SCFG5      (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
9648 +#define                AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
9649 +#define                AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
9650 +#define                        AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
9651 +#define                        AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
9652 +#define                        AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
9653 +#define                AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
9654 +#define                AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
9655 +#define                        AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
9656 +#define                        AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
9657 +
9658 +#define AT91_MATRIX_PRAS0      (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
9659 +#define AT91_MATRIX_PRAS1      (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
9660 +#define AT91_MATRIX_PRAS2      (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
9661 +#define AT91_MATRIX_PRAS3      (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
9662 +#define AT91_MATRIX_PRAS4      (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
9663 +#define AT91_MATRIX_PRAS5      (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
9664 +#define                AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
9665 +#define                AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
9666 +#define                AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
9667 +#define                AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
9668 +#define                AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
9669 +#define                AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
9670 +
9671 +#define AT91_MATRIX_MRCR       (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
9672 +#define                AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
9673 +#define                AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
9674 +#define                AT91_MATRIX_RCB2                (1 << 2)
9675 +#define                AT91_MATRIX_RCB3                (1 << 3)
9676 +#define                AT91_MATRIX_RCB4                (1 << 4)
9677 +#define                AT91_MATRIX_RCB5                (1 << 5)
9678 +
9679 +#define AT91_MATRIX_TCMR       (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
9680 +#define                AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
9681 +#define                        AT91_MATRIX_ITCM_0              (0 << 0)
9682 +#define                        AT91_MATRIX_ITCM_16             (5 << 0)
9683 +#define                        AT91_MATRIX_ITCM_32             (6 << 0)
9684 +#define                AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
9685 +#define                        AT91_MATRIX_DTCM_0              (0 << 4)
9686 +#define                        AT91_MATRIX_DTCM_16             (5 << 4)
9687 +#define                        AT91_MATRIX_DTCM_32             (6 << 4)
9688 +
9689 +#define AT91_MATRIX_EBICSA     (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
9690 +#define                AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
9691 +#define                        AT91_MATRIX_CS1A_SMC            (0 << 1)
9692 +#define                        AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
9693 +#define                AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
9694 +#define                        AT91_MATRIX_CS3A_SMC            (0 << 3)
9695 +#define                        AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
9696 +#define                AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
9697 +#define                        AT91_MATRIX_CS4A_SMC            (0 << 4)
9698 +#define                        AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
9699 +#define                AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
9700 +#define                        AT91_MATRIX_CS5A_SMC            (0 << 5)
9701 +#define                        AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
9702 +#define                AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
9703 +#define                AT91_MATRIX_VDDIOMSEL           (1 << 16)       /* Memory voltage selection */
9704 +#define                        AT91_MATRIX_VDDIOMSEL_1_8V      (0 << 16)
9705 +#define                        AT91_MATRIX_VDDIOMSEL_3_3V      (1 << 16)
9706 +
9707 +
9708 +#endif
9709 Index: linux-2.6.21.7/include/asm-arm/arch-at91/board.h
9710 ===================================================================
9711 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/board.h
9712 +++ linux-2.6.21.7/include/asm-arm/arch-at91/board.h
9713 @@ -62,7 +62,7 @@ struct at91_mmc_data {
9714  };
9715  extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
9716
9717 - /* Ethernet */
9718 + /* Ethernet (EMAC & MACB) */
9719  struct at91_eth_data {
9720         u8              phy_irq_pin;    /* PHY IRQ */
9721         u8              is_rmii;        /* using RMII interface? */
9722 @@ -114,9 +114,31 @@ struct atmel_uart_data {
9723  };
9724  extern void __init at91_add_device_serial(void);
9725
9726 + /* LCD Controller */
9727 +struct atmel_lcdfb_info;
9728 +extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
9729 +
9730 + /* AC97 */
9731 +struct atmel_ac97_data {
9732 +       u8              reset_pin;      /* reset */
9733 +};
9734 +extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
9735 +
9736 + /* ISI */
9737 +extern void __init at91_add_device_isi(void);
9738 +
9739   /* LEDs */
9740  extern u8 at91_leds_cpu;
9741  extern u8 at91_leds_timer;
9742  extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
9743
9744 +struct at91_gpio_led {
9745 +       u8              index;          /* index of LED */
9746 +       char*           name;           /* name of LED */
9747 +       u8              gpio;           /* AT91_PIN_xx */
9748 +       u8              flags;          /* 1=active-high */
9749 +       char*           trigger;        /* default trigger */
9750 +};
9751 +extern void __init at91_gpio_leds(struct at91_gpio_led *leds, int nr);
9752 +
9753  #endif
9754 Index: linux-2.6.21.7/include/asm-arm/arch-at91/cpu.h
9755 ===================================================================
9756 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/cpu.h
9757 +++ linux-2.6.21.7/include/asm-arm/arch-at91/cpu.h
9758 @@ -26,6 +26,8 @@
9759  #define ARCH_ID_AT91SAM9XE256  0x329a93a0
9760  #define ARCH_ID_AT91SAM9XE512  0x329aa3a0
9761
9762 +#define ARCH_ID_AT91SAM9RL64   0x019b03a0
9763 +
9764  static inline unsigned long at91_cpu_identify(void)
9765  {
9766         return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
9767 @@ -68,4 +70,10 @@ static inline unsigned long at91_arch_id
9768  #define cpu_is_at91sam9263()   (0)
9769  #endif
9770
9771 +#ifdef CONFIG_ARCH_AT91SAM9RL
9772 +#define cpu_is_at91sam9rl()    (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
9773 +#else
9774 +#define cpu_is_at91sam9rl()    (0)
9775 +#endif
9776 +
9777  #endif
9778 Index: linux-2.6.21.7/include/asm-arm/arch-at91/hardware.h
9779 ===================================================================
9780 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/hardware.h
9781 +++ linux-2.6.21.7/include/asm-arm/arch-at91/hardware.h
9782 @@ -24,6 +24,8 @@
9783  #include <asm/arch/at91sam9261.h>
9784  #elif defined(CONFIG_ARCH_AT91SAM9263)
9785  #include <asm/arch/at91sam9263.h>
9786 +#elif defined(CONFIG_ARCH_AT91SAM9RL)
9787 +#include <asm/arch/at91sam9rl.h>
9788  #else
9789  #error "Unsupported AT91 processor"
9790  #endif
9791 @@ -69,22 +71,5 @@
9792  /* Clocks */
9793  #define AT91_SLOW_CLOCK                32768           /* slow clock */
9794
9795 -#ifndef __ASSEMBLY__
9796 -#include <asm/io.h>
9797 -
9798 -static inline unsigned int at91_sys_read(unsigned int reg_offset)
9799 -{
9800 -       void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
9801 -
9802 -       return __raw_readl(addr + reg_offset);
9803 -}
9804 -
9805 -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
9806 -{
9807 -       void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
9808 -
9809 -       __raw_writel(value, addr + reg_offset);
9810 -}
9811 -#endif
9812
9813  #endif
9814 Index: linux-2.6.21.7/include/asm-arm/arch-at91/ics1523.h
9815 ===================================================================
9816 --- /dev/null
9817 +++ linux-2.6.21.7/include/asm-arm/arch-at91/ics1523.h
9818 @@ -0,0 +1,154 @@
9819 +//*----------------------------------------------------------------------------
9820 +//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
9821 +//*----------------------------------------------------------------------------
9822 +//* The software is delivered "AS IS" without warranty or condition of any
9823 +//* kind, either express, implied or statutory. This includes without
9824 +//* limitation any warranty or condition with respect to merchantability or
9825 +//* fitness for any particular purpose, or against the infringements of
9826 +//* intellectual property rights of others.
9827 +//*----------------------------------------------------------------------------
9828 +//* File Name           : ics1523.h
9829 +//* Object              : Clock Generator Prototyping File.
9830 +//*
9831 +//* 1.0 08/28/02 ED     : Creation
9832 +//* 1.2 13/01/03 FB            : Update on lib V3
9833 +//*----------------------------------------------------------------------------
9834 +
9835 +#ifndef ics1523_h
9836 +#define ics1523_h
9837 +
9838 +/*-------------------------------------------*/
9839 +/* ICS1523 TWI Serial Clock Definition       */
9840 +/*-------------------------------------------*/
9841 +
9842 +#define                ICS_MIN_CLOCK           100             /* Min Frequency Access Clock KHz */
9843 +#define                ICS_MAX_CLOCK           400             /* Max Frequency Access Clock KHz */
9844 +#define                ICS_TRANSFER_RATE       ICS_MAX_CLOCK   /* Transfer speed to apply */
9845 +
9846 +#define                ICS_WRITE_CLK_PNB       30              /* TWCK Clock Periods required to write */
9847 +#define                ICS_READ_CLK_PNB        40              /* TWCK Clock Periods required to read */
9848 +
9849 +/*-------------------------------------------*/
9850 +/* ICS1523 Write Operation Definition        */
9851 +/*-------------------------------------------*/
9852 +
9853 +#define                ICS1523_ACCESS_OK       0               /* OK */
9854 +#define                ICS1523_ACCESS_ERROR    -1              /* NOK */
9855 +
9856 +/*-------------------------------------------*/
9857 +/* ICS1523 Device Addresses Definition       */
9858 +/*-------------------------------------------*/
9859 +
9860 +#define                ICS_ADDR                0x26            /* Device Address */
9861 +
9862 +/*--------------------------------------------------*/
9863 +/* ICS1523 Registers Internal Addresses Definition  */
9864 +/*--------------------------------------------------*/
9865 +
9866 +#define                ICS_ICR                 0x0             /* Input Control Register */
9867 +#define                ICS_LCR                 0x1             /* Loop Control Register */
9868 +#define                ICS_FD0                 0x2             /* PLL FeedBack Divider LSBs */
9869 +#define                ICS_FD1                 0x3             /* PLL FeedBack Divider MSBs */
9870 +#define                ICS_DPAO                0x4             /* Dynamic Phase Aligner Offset */
9871 +#define                ICS_DPAC                0x5             /* Dynamic Phase Aligner Resolution */
9872 +#define                ICS_OE                  0x6             /* Output Enables Register */
9873 +#define                ICS_OD                  0x7             /* Osc Divider Register */
9874 +#define                ICS_SWRST               0x8             /* DPA & PLL Reset Register */
9875 +#define                ICS_VID                 0x10            /* Chip Version Register */
9876 +#define                ICS_RID                 0x11            /* Chip Revision Register */
9877 +#define                ICS_SR                  0x12            /* Status Register */
9878 +
9879 +/*------------------------------------------------------*/
9880 +/* ICS1523 Input Control Register Bits Definition       */
9881 +/*------------------------------------------------------*/
9882 +
9883 +#define                ICS_PDEN                0x1             /* Phase Detector Enable */
9884 +#define                ICS_PDPOL               0x2             /* Phase Detector Enable Polarity */
9885 +#define                ICS_REFPOL              0x4             /* External Reference Polarity */
9886 +#define                ICS_FBKPOL              0x8             /* External Feedback Polarity */
9887 +#define                ICS_FBKSEL              0x10            /* External Feedback Select */
9888 +#define                ICS_FUNCSEL             0x20            /* Function Out Select */
9889 +#define                ICS_ENPLS               0x40            /* Enable PLL Lock/Ref Status Output */
9890 +#define                ICS_ENDLS               0x80            /* Enable DPA Lock/Ref Status Output */
9891 +
9892 +/*-----------------------------------------------------*/
9893 +/* ICS1523 Loop Control Register Bits Definition       */
9894 +/*-----------------------------------------------------*/
9895 +
9896 +#define                ICS_PFD                 0x7             /* Phase Detector Gain */
9897 +#define                ICS_PSD                 0x30            /* Post-Scaler Divider */
9898 +
9899 +/*----------------------------------------------------*/
9900 +/* ICS1523 PLL FeedBack Divider LSBs Definition       */
9901 +/*----------------------------------------------------*/
9902 +
9903 +#define                ICS_FBDL                0xFF            /* PLL FeedBack Divider LSBs */
9904 +
9905 +/*----------------------------------------------------*/
9906 +/* ICS1523 PLL FeedBack Divider MSBs Definition       */
9907 +/*----------------------------------------------------*/
9908 +
9909 +#define                ICS_FBDM                0xF             /* PLL FeedBack Divider MSBs */
9910 +
9911 +/*------------------------------------------------------------*/
9912 +/* ICS1523 Dynamic Phase Aligner Offset Bits Definition       */
9913 +/*------------------------------------------------------------*/
9914 +
9915 +#define                ICS_DPAOS               0x2F            /* Dynamic Phase Aligner Offset */
9916 +#define                ICS_FILSEL              0x80            /* Loop Filter Select */
9917 +
9918 +/*----------------------------------------------------------------*/
9919 +/* ICS1523 Dynamic Phase Aligner Resolution Bits Definition       */
9920 +/*----------------------------------------------------------------*/
9921 +
9922 +#define                ICS_DPARES              0x3             /* Dynamic Phase Aligner Resolution */
9923 +#define                ICS_MMREV               0xFC            /* Metal Mask Revision Number */
9924 +
9925 +/*-------------------------------------------------------*/
9926 +/* ICS1523 Output Enables Register Bits Definition       */
9927 +/*-------------------------------------------------------*/
9928 +
9929 +#define                ICS_OEPCK               0x1             /* Output Enable for PECL PCLK Outputs */
9930 +#define                ICS_OETCK               0x2             /* Output Enable for STTL CLK Output */
9931 +#define                ICS_OEP2                0x4             /* Output Enable for PECL CLK/2 Outputs */
9932 +#define                ICS_OET2                0x8             /* Output Enable for STTL CLK/2 Output */
9933 +#define                ICS_OEF                 0x10            /* Output Enable for STTL FUNC Output */
9934 +#define                ICS_CLK2INV             0x20            /* CLK/2 Invert */
9935 +#define                ICS_OSCL                0xC0            /* SSTL Clock Scaler */
9936 +
9937 +/*----------------------------------------------------*/
9938 +/* ICS1523 Osc Divider Register Bits Definition       */
9939 +/*----------------------------------------------------*/
9940 +
9941 +#define                ICS_OSCDIV              0x7F            /* Oscillator Divider Modulus */
9942 +#define                ICS_INSEL               0x80            /* Input Select */
9943 +
9944 +/*---------------------------------------------------*/
9945 +/* ICS1523 DPA & PLL Reset Register Definition       */
9946 +/*---------------------------------------------------*/
9947 +
9948 +#define                ICS_DPAR                0x0A            /* DPA Reset Command */
9949 +#define                ICS_PLLR                0x50            /* PLL Reset Command */
9950 +
9951 +/*------------------------------------------------*/
9952 +/* ICS1523 Chip Version Register Definition       */
9953 +/*------------------------------------------------*/
9954 +
9955 +#define                ICS_CHIPV               0xFF            /* Chip Version */
9956 +
9957 +/*-------------------------------------------------*/
9958 +/* ICS1523 Chip Revision Register Definition       */
9959 +/*-------------------------------------------------*/
9960 +
9961 +#define                ICS_CHIPR               0xFF            /* Chip Revision */
9962 +
9963 +/*------------------------------------------*/
9964 +/* ICS1523 Status Register Definition       */
9965 +/*------------------------------------------*/
9966 +
9967 +#define                ICS_DPALOCK             0x1             /* DPA Lock Status */
9968 +#define                ICS_PLLLOCK             0x2             /* PLL Lock Status */
9969 +
9970 +int at91_ics1523_init(void);
9971 +
9972 +#endif /* ics1523_h */
9973 Index: linux-2.6.21.7/include/asm-arm/arch-at91/io.h
9974 ===================================================================
9975 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/io.h
9976 +++ linux-2.6.21.7/include/asm-arm/arch-at91/io.h
9977 @@ -29,4 +29,22 @@
9978  #define __mem_pci(a)           (a)
9979
9980
9981 +#ifndef __ASSEMBLY__
9982 +
9983 +static inline unsigned int at91_sys_read(unsigned int reg_offset)
9984 +{
9985 +       void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
9986 +
9987 +       return __raw_readl(addr + reg_offset);
9988 +}
9989 +
9990 +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
9991 +{
9992 +       void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
9993 +
9994 +       __raw_writel(value, addr + reg_offset);
9995 +}
9996 +
9997 +#endif
9998 +
9999  #endif
10000 Index: linux-2.6.21.7/include/asm-arm/arch-at91/irqs.h
10001 ===================================================================
10002 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/irqs.h
10003 +++ linux-2.6.21.7/include/asm-arm/arch-at91/irqs.h
10004 @@ -21,6 +21,7 @@
10005  #ifndef __ASM_ARCH_IRQS_H
10006  #define __ASM_ARCH_IRQS_H
10007
10008 +#include <asm/io.h>
10009  #include <asm/arch/at91_aic.h>
10010
10011  #define NR_AIC_IRQS 32
10012 Index: linux-2.6.21.7/include/asm-arm/arch-at91/spi.h
10013 ===================================================================
10014 --- /dev/null
10015 +++ linux-2.6.21.7/include/asm-arm/arch-at91/spi.h
10016 @@ -0,0 +1,54 @@
10017 +/*
10018 + * Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200
10019 + *
10020 + * (c) SAN People (Pty) Ltd
10021 + *
10022 + * This program is free software; you can redistribute it and/or
10023 + * modify it under the terms of the GNU General Public License
10024 + * as published by the Free Software Foundation; either version
10025 + * 2 of the License, or (at your option) any later version.
10026 + */
10027 +
10028 +#ifndef AT91_LEGACY_SPI_H
10029 +#define AT91_LEGACY_SPI_H
10030 +
10031 +#define SPI_MAJOR              153     /* registered device number */
10032 +
10033 +#define DEFAULT_SPI_CLK                6000000
10034 +
10035 +
10036 +/* Maximum number of buffers in a single SPI transfer.
10037 + *  DataFlash uses maximum of 2
10038 + *  spidev interface supports up to 8.
10039 + */
10040 +#define MAX_SPI_TRANSFERS      8
10041 +#define NR_SPI_DEVICES         4       /* number of devices on SPI bus */
10042 +
10043 +/*
10044 + * Describes the buffers for a SPI transfer.
10045 + * A transmit & receive buffer must be specified for each transfer
10046 + */
10047 +struct spi_transfer_list {
10048 +       void* tx[MAX_SPI_TRANSFERS];    /* transmit */
10049 +       int txlen[MAX_SPI_TRANSFERS];
10050 +       void* rx[MAX_SPI_TRANSFERS];    /* receive */
10051 +       int rxlen[MAX_SPI_TRANSFERS];
10052 +       int nr_transfers;               /* number of transfers */
10053 +       int curr;                       /* current transfer */
10054 +};
10055 +
10056 +struct spi_local {
10057 +       unsigned int pcs;               /* Peripheral Chip Select value */
10058 +
10059 +       struct spi_transfer_list *xfers;        /* current transfer list */
10060 +       dma_addr_t tx, rx;              /* DMA address for current transfer */
10061 +       dma_addr_t txnext, rxnext;      /* DMA address for next transfer */
10062 +};
10063 +
10064 +
10065 +/* Exported functions */
10066 +extern void spi_access_bus(short device);
10067 +extern void spi_release_bus(short device);
10068 +extern int spi_transfer(struct spi_transfer_list* list);
10069 +
10070 +#endif
10071 Index: linux-2.6.21.7/include/asm-arm/arch-at91/timex.h
10072 ===================================================================
10073 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/timex.h
10074 +++ linux-2.6.21.7/include/asm-arm/arch-at91/timex.h
10075 @@ -37,6 +37,11 @@
10076  #define AT91SAM9_MASTER_CLOCK  99959500
10077  #define CLOCK_TICK_RATE                (AT91SAM9_MASTER_CLOCK/16)
10078
10079 +#elif defined(CONFIG_ARCH_AT91SAM9RL)
10080 +
10081 +#define AT91SAM9_MASTER_CLOCK  100000000
10082 +#define CLOCK_TICK_RATE                (AT91SAM9_MASTER_CLOCK/16)
10083 +
10084  #endif
10085
10086  #endif
10087 Index: linux-2.6.21.7/include/asm-arm/arch-at91/uncompress.h
10088 ===================================================================
10089 --- linux-2.6.21.7.orig/include/asm-arm/arch-at91/uncompress.h
10090 +++ linux-2.6.21.7/include/asm-arm/arch-at91/uncompress.h
10091 @@ -21,7 +21,7 @@
10092  #ifndef __ASM_ARCH_UNCOMPRESS_H
10093  #define __ASM_ARCH_UNCOMPRESS_H
10094
10095 -#include <asm/hardware.h>
10096 +#include <asm/io.h>
10097  #include <asm/arch/at91_dbgu.h>
10098
10099  /*
10100 Index: linux-2.6.21.7/include/linux/clk.h
10101 ===================================================================
10102 --- linux-2.6.21.7.orig/include/linux/clk.h
10103 +++ linux-2.6.21.7/include/linux/clk.h
10104 @@ -121,4 +121,24 @@ int clk_set_parent(struct clk *clk, stru
10105   */
10106  struct clk *clk_get_parent(struct clk *clk);
10107
10108 +/**
10109 + * clk_must_disable - report whether a clock's users must disable it
10110 + * @clk: one node in the clock tree
10111 + *
10112 + * This routine returns true only if the upcoming system state requires
10113 + * disabling the specified clock.
10114 + *
10115 + * It's common for platform power states to constrain certain clocks (and
10116 + * their descendants) to be unavailable, while other states allow that
10117 + * clock to be active.  A platform's power states often include an "all on"
10118 + * mode; system wide sleep states like "standby" or "suspend-to-RAM"; and
10119 + * operating states which sacrifice functionality for lower power usage.
10120 + *
10121 + * The constraint value is commonly tested in device driver suspend(), to
10122 + * leave clocks active if they are needed for features like wakeup events.
10123 + * On platforms that support reduced functionality operating states, the
10124 + * constraint may also need to be tested during resume() and probe() calls.
10125 + */
10126 +int clk_must_disable(struct clk *clk);
10127 +
10128  #endif
10129 Index: linux-2.6.21.7/include/linux/i2c-id.h
10130 ===================================================================
10131 --- linux-2.6.21.7.orig/include/linux/i2c-id.h
10132 +++ linux-2.6.21.7/include/linux/i2c-id.h
10133 @@ -202,6 +202,7 @@
10134
10135  /* --- PCA 9564 based algorithms */
10136  #define I2C_HW_A_ISA           0x1a0000 /* generic ISA Bus interface card */
10137 +#define I2C_HW_A_PLAT          0x1a0001 /* generic platform_bus interface */
10138
10139  /* --- ACPI Embedded controller algorithms                              */
10140  #define I2C_HW_ACPI_EC          0x1f0000
10141 Index: linux-2.6.21.7/include/video/atmel_lcdc.h
10142 ===================================================================
10143 --- /dev/null
10144 +++ linux-2.6.21.7/include/video/atmel_lcdc.h
10145 @@ -0,0 +1,196 @@
10146 +/*
10147 + *  Header file for AT91/AT32 LCD Controller
10148 + *
10149 + *  Data structure and register user interface
10150 + *
10151 + *  Copyright (C) 2007 Atmel Corporation
10152 + *
10153 + * This program is free software; you can redistribute it and/or modify
10154 + * it under the terms of the GNU General Public License as published by
10155 + * the Free Software Foundation; either version 2 of the License, or
10156 + * (at your option) any later version.
10157 + *
10158 + * This program is distributed in the hope that it will be useful,
10159 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
10160 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10161 + * GNU General Public License for more details.
10162 + *
10163 + * You should have received a copy of the GNU General Public License
10164 + * along with this program; if not, write to the Free Software
10165 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
10166 + */
10167 +#ifndef __ATMEL_LCDC_H__
10168 +#define __ATMEL_LCDC_H__
10169 +
10170 + /* LCD Controller info data structure */
10171 +struct atmel_lcdfb_info {
10172 +       spinlock_t              lock;
10173 +       struct fb_info          *info;
10174 +       void __iomem            *mmio;
10175 +       unsigned long           irq_base;
10176 +
10177 +       unsigned int            guard_time;
10178 +       struct platform_device  *pdev;
10179 +       struct clk              *bus_clk;
10180 +       struct clk              *lcdc_clk;
10181 +       unsigned int            default_bpp;
10182 +       unsigned int            default_lcdcon2;
10183 +       unsigned int            default_dmacon;
10184 +       void (*atmel_lcdfb_power_control)(int on);
10185 +       struct fb_monspecs      *default_monspecs;
10186 +       u32                     pseudo_palette[16];
10187 +};
10188 +
10189 +#define ATMEL_LCDC_DMABADDR1   0x00
10190 +#define ATMEL_LCDC_DMABADDR2   0x04
10191 +#define ATMEL_LCDC_DMAFRMPT1   0x08
10192 +#define ATMEL_LCDC_DMAFRMPT2   0x0c
10193 +#define ATMEL_LCDC_DMAFRMADD1  0x10
10194 +#define ATMEL_LCDC_DMAFRMADD2  0x14
10195 +
10196 +#define ATMEL_LCDC_DMAFRMCFG   0x18
10197 +#define        ATMEL_LCDC_FRSIZE       (0x7fffff <<  0)
10198 +#define        ATMEL_LCDC_BLENGTH_OFFSET       24
10199 +#define        ATMEL_LCDC_BLENGTH      (0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
10200 +
10201 +#define ATMEL_LCDC_DMACON      0x1c
10202 +#define        ATMEL_LCDC_DMAEN        (0x1 << 0)
10203 +#define        ATMEL_LCDC_DMARST       (0x1 << 1)
10204 +#define        ATMEL_LCDC_DMABUSY      (0x1 << 2)
10205 +#define                ATMEL_LCDC_DMAUPDT      (0x1 << 3)
10206 +#define                ATMEL_LCDC_DMA2DEN      (0x1 << 4)
10207 +
10208 +#define ATMEL_LCDC_DMA2DCFG    0x20
10209 +#define                ATMEL_LCDC_ADDRINC_OFFSET       0
10210 +#define                ATMEL_LCDC_ADDRINC              (0xffff)
10211 +#define                ATMEL_LCDC_PIXELOFF_OFFSET      24
10212 +#define                ATMEL_LCDC_PIXELOFF             (0x1f << 24)
10213 +
10214 +#define ATMEL_LCDC_LCDCON1     0x0800
10215 +#define        ATMEL_LCDC_BYPASS       (1     <<  0)
10216 +#define        ATMEL_LCDC_CLKVAL_OFFSET        12
10217 +#define        ATMEL_LCDC_CLKVAL       (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
10218 +#define        ATMEL_LCDC_LINCNT       (0x7ff << 21)
10219 +
10220 +#define ATMEL_LCDC_LCDCON2     0x0804
10221 +#define        ATMEL_LCDC_DISTYPE      (3 << 0)
10222 +#define                ATMEL_LCDC_DISTYPE_STNMONO      (0 << 0)
10223 +#define                ATMEL_LCDC_DISTYPE_STNCOLOR     (1 << 0)
10224 +#define                ATMEL_LCDC_DISTYPE_TFT          (2 << 0)
10225 +#define        ATMEL_LCDC_SCANMOD      (1 << 2)
10226 +#define                ATMEL_LCDC_SCANMOD_SINGLE       (0 << 2)
10227 +#define                ATMEL_LCDC_SCANMOD_DUAL         (1 << 2)
10228 +#define        ATMEL_LCDC_IFWIDTH      (3 << 3)
10229 +#define                ATMEL_LCDC_IFWIDTH_4            (0 << 3)
10230 +#define                ATMEL_LCDC_IFWIDTH_8            (1 << 3)
10231 +#define                ATMEL_LCDC_IFWIDTH_16           (2 << 3)
10232 +#define        ATMEL_LCDC_PIXELSIZE    (7 << 5)
10233 +#define                ATMEL_LCDC_PIXELSIZE_1          (0 << 5)
10234 +#define                ATMEL_LCDC_PIXELSIZE_2          (1 << 5)
10235 +#define                ATMEL_LCDC_PIXELSIZE_4          (2 << 5)
10236 +#define                ATMEL_LCDC_PIXELSIZE_8          (3 << 5)
10237 +#define                ATMEL_LCDC_PIXELSIZE_16         (4 << 5)
10238 +#define                ATMEL_LCDC_PIXELSIZE_24         (5 << 5)
10239 +#define                ATMEL_LCDC_PIXELSIZE_32         (6 << 5)
10240 +#define        ATMEL_LCDC_INVVD        (1 << 8)
10241 +#define                ATMEL_LCDC_INVVD_NORMAL         (0 << 8)
10242 +#define                ATMEL_LCDC_INVVD_INVERTED       (1 << 8)
10243 +#define        ATMEL_LCDC_INVFRAME     (1 << 9 )
10244 +#define                ATMEL_LCDC_INVFRAME_NORMAL      (0 << 9)
10245 +#define                ATMEL_LCDC_INVFRAME_INVERTED    (1 << 9)
10246 +#define        ATMEL_LCDC_INVLINE      (1 << 10)
10247 +#define                ATMEL_LCDC_INVLINE_NORMAL       (0 << 10)
10248 +#define                ATMEL_LCDC_INVLINE_INVERTED     (1 << 10)
10249 +#define        ATMEL_LCDC_INVCLK       (1 << 11)
10250 +#define                ATMEL_LCDC_INVCLK_NORMAL        (0 << 11)
10251 +#define                ATMEL_LCDC_INVCLK_INVERTED      (1 << 11)
10252 +#define        ATMEL_LCDC_INVDVAL      (1 << 12)
10253 +#define                ATMEL_LCDC_INVDVAL_NORMAL       (0 << 12)
10254 +#define                ATMEL_LCDC_INVDVAL_INVERTED     (1 << 12)
10255 +#define        ATMEL_LCDC_CLKMOD       (1 << 15)
10256 +#define                ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
10257 +#define                ATMEL_LCDC_CLKMOD_ALWAYSACTIVE  (1 << 15)
10258 +#define        ATMEL_LCDC_MEMOR        (1 << 31)
10259 +#define                ATMEL_LCDC_MEMOR_BIG            (0 << 31)
10260 +#define                ATMEL_LCDC_MEMOR_LITTLE         (1 << 31)
10261 +
10262 +#define ATMEL_LCDC_TIM1                0x0808
10263 +#define        ATMEL_LCDC_VFP          (0xff <<  0)
10264 +#define        ATMEL_LCDC_VBP_OFFSET           8
10265 +#define        ATMEL_LCDC_VBP          (0xff <<  ATMEL_LCDC_VBP_OFFSET)
10266 +#define        ATMEL_LCDC_VPW_OFFSET           16
10267 +#define        ATMEL_LCDC_VPW          (0x3f << ATMEL_LCDC_VPW_OFFSET)
10268 +#define        ATMEL_LCDC_VHDLY_OFFSET         24
10269 +#define        ATMEL_LCDC_VHDLY        (0xf  << ATMEL_LCDC_VHDLY_OFFSET)
10270 +
10271 +#define ATMEL_LCDC_TIM2                0x080c
10272 +#define        ATMEL_LCDC_HBP          (0xff  <<  0)
10273 +#define        ATMEL_LCDC_HPW_OFFSET           8
10274 +#define        ATMEL_LCDC_HPW          (0x3f  <<  ATMEL_LCDC_HPW_OFFSET)
10275 +#define        ATMEL_LCDC_HFP_OFFSET           21
10276 +#define        ATMEL_LCDC_HFP          (0x7ff << ATMEL_LCDC_HFP_OFFSET)
10277 +
10278 +#define ATMEL_LCDC_LCDFRMCFG   0x0810
10279 +#define        ATMEL_LCDC_LINEVAL      (0x7ff <<  0)
10280 +#define        ATMEL_LCDC_HOZVAL_OFFSET        21
10281 +#define        ATMEL_LCDC_HOZVAL       (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
10282 +
10283 +#define ATMEL_LCDC_FIFO                0x0814
10284 +#define        ATMEL_LCDC_FIFOTH       (0xffff)
10285 +
10286 +#define ATMEL_LCDC_MVAL                0x0818
10287 +
10288 +#define ATMEL_LCDC_DP1_2       0x081c
10289 +#define ATMEL_LCDC_DP4_7       0x0820
10290 +#define ATMEL_LCDC_DP3_5       0x0824
10291 +#define ATMEL_LCDC_DP2_3       0x0828
10292 +#define ATMEL_LCDC_DP5_7       0x082c
10293 +#define ATMEL_LCDC_DP3_4       0x0830
10294 +#define ATMEL_LCDC_DP4_5       0x0834
10295 +#define ATMEL_LCDC_DP6_7       0x0838
10296 +#define        ATMEL_LCDC_DP1_2_VAL    (0xff)
10297 +#define        ATMEL_LCDC_DP4_7_VAL    (0xfffffff)
10298 +#define        ATMEL_LCDC_DP3_5_VAL    (0xfffff)
10299 +#define        ATMEL_LCDC_DP2_3_VAL    (0xfff)
10300 +#define        ATMEL_LCDC_DP5_7_VAL    (0xfffffff)
10301 +#define        ATMEL_LCDC_DP3_4_VAL    (0xffff)
10302 +#define        ATMEL_LCDC_DP4_5_VAL    (0xfffff)
10303 +#define        ATMEL_LCDC_DP6_7_VAL    (0xfffffff)
10304 +
10305 +#define ATMEL_LCDC_PWRCON      0x083c
10306 +#define        ATMEL_LCDC_PWR          (1    <<  0)
10307 +#define        ATMEL_LCDC_GUARDT_OFFSET        1
10308 +#define        ATMEL_LCDC_GUARDT       (0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
10309 +#define        ATMEL_LCDC_BUSY         (1    << 31)
10310 +
10311 +#define ATMEL_LCDC_CONTRAST_CTR        0x0840
10312 +#define        ATMEL_LCDC_PS           (3 << 0)
10313 +#define                ATMEL_LCDC_PS_DIV1              (0 << 0)
10314 +#define                ATMEL_LCDC_PS_DIV2              (1 << 0)
10315 +#define                ATMEL_LCDC_PS_DIV4              (2 << 0)
10316 +#define                ATMEL_LCDC_PS_DIV8              (3 << 0)
10317 +#define        ATMEL_LCDC_POL          (1 << 2)
10318 +#define                ATMEL_LCDC_POL_NEGATIVE         (0 << 2)
10319 +#define                ATMEL_LCDC_POL_POSITIVE         (1 << 2)
10320 +#define        ATMEL_LCDC_ENA          (1 << 3)
10321 +#define                ATMEL_LCDC_ENA_PWMDISABLE       (0 << 3)
10322 +#define                ATMEL_LCDC_ENA_PWMENABLE        (1 << 3)
10323 +
10324 +#define ATMEL_LCDC_CONTRAST_VAL        0x0844
10325 +#define        ATMEL_LCDC_CVAL (0xff)
10326 +
10327 +#define ATMEL_LCDC_IER         0x0848
10328 +#define ATMEL_LCDC_IDR         0x084c
10329 +#define ATMEL_LCDC_IMR         0x0850
10330 +#define ATMEL_LCDC_ISR         0x0854
10331 +#define ATMEL_LCDC_ICR         0x0858
10332 +#define        ATMEL_LCDC_LNI          (1 << 0)
10333 +#define        ATMEL_LCDC_LSTLNI       (1 << 1)
10334 +#define        ATMEL_LCDC_EOFI         (1 << 2)
10335 +#define        ATMEL_LCDC_UFLWI        (1 << 4)
10336 +#define        ATMEL_LCDC_OWRI         (1 << 5)
10337 +#define        ATMEL_LCDC_MERI         (1 << 6)
10338 +
10339 +#define ATMEL_LCDC_LUT(n)      (0x0c00 + ((n)*4))
10340 +
10341 +#endif /* __ATMEL_LCDC_H__ */
10342 Index: linux-2.6.21.7/sound/soc/at91/eti_b1_wm8731.c
10343 ===================================================================
10344 --- linux-2.6.21.7.orig/sound/soc/at91/eti_b1_wm8731.c
10345 +++ linux-2.6.21.7/sound/soc/at91/eti_b1_wm8731.c
10346 @@ -34,8 +34,7 @@
10347  #include <sound/soc.h>
10348  #include <sound/soc-dapm.h>
10349
10350 -#include <asm/arch/hardware.h>
10351 -#include <asm/arch/at91_pio.h>
10352 +#include <asm/hardware.h>
10353  #include <asm/arch/gpio.h>
10354
10355  #include "../codecs/wm8731.h"
10356 @@ -48,13 +47,6 @@
10357  #define        DBG(x...)
10358  #endif
10359
10360 -#define AT91_PIO_TF1   (1 << (AT91_PIN_PB6 - PIN_BASE) % 32)
10361 -#define AT91_PIO_TK1   (1 << (AT91_PIN_PB7 - PIN_BASE) % 32)
10362 -#define AT91_PIO_TD1   (1 << (AT91_PIN_PB8 - PIN_BASE) % 32)
10363 -#define AT91_PIO_RD1   (1 << (AT91_PIN_PB9 - PIN_BASE) % 32)
10364 -#define AT91_PIO_RK1   (1 << (AT91_PIN_PB10 - PIN_BASE) % 32)
10365 -#define AT91_PIO_RF1   (1 << (AT91_PIN_PB11 - PIN_BASE) % 32)
10366 -
10367  static struct clk *pck1_clk;
10368  static struct clk *pllb_clk;
10369
10370 @@ -277,7 +269,6 @@ static struct platform_device *eti_b1_sn
10371  static int __init eti_b1_init(void)
10372  {
10373         int ret;
10374 -       u32 ssc_pio_lines;
10375         struct at91_ssc_periph *ssc = eti_b1_dai.cpu_dai->private_data;
10376
10377         if (!request_mem_region(AT91RM9200_BASE_SSC1, SZ_16K, "soc-audio")) {
10378 @@ -311,19 +302,12 @@ static int __init eti_b1_init(void)
10379                 goto fail_io_unmap;
10380         }
10381
10382 -       ssc_pio_lines = AT91_PIO_TF1 | AT91_PIO_TK1 | AT91_PIO_TD1
10383 -                       | AT91_PIO_RD1 /* | AT91_PIO_RK1 */ | AT91_PIO_RF1;
10384 -
10385 -       /* Reset all PIO registers and assign lines to peripheral A */
10386 -       at91_sys_write(AT91_PIOB + PIO_PDR,  ssc_pio_lines);
10387 -       at91_sys_write(AT91_PIOB + PIO_ODR,  ssc_pio_lines);
10388 -       at91_sys_write(AT91_PIOB + PIO_IFDR, ssc_pio_lines);
10389 -       at91_sys_write(AT91_PIOB + PIO_CODR, ssc_pio_lines);
10390 -       at91_sys_write(AT91_PIOB + PIO_IDR,  ssc_pio_lines);
10391 -       at91_sys_write(AT91_PIOB + PIO_MDDR, ssc_pio_lines);
10392 -       at91_sys_write(AT91_PIOB + PIO_PUDR, ssc_pio_lines);
10393 -       at91_sys_write(AT91_PIOB + PIO_ASR,  ssc_pio_lines);
10394 -       at91_sys_write(AT91_PIOB + PIO_OWDR, ssc_pio_lines);
10395 +       at91_set_A_periph(AT91_PIN_PB6, 0);     /* TF1 */
10396 +       at91_set_A_periph(AT91_PIN_PB7, 0);     /* TK1 */
10397 +       at91_set_A_periph(AT91_PIN_PB8, 0);     /* TD1 */
10398 +       at91_set_A_periph(AT91_PIN_PB9, 0);     /* RD1 */
10399 +/*     at91_set_A_periph(AT91_PIN_PB10, 0);*/  /* RK1 */
10400 +       at91_set_A_periph(AT91_PIN_PB11, 0);    /* RF1 */
10401
10402         /*
10403          * Set PCK1 parent to PLLB and its rate to 12 Mhz.