target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch

   1 --- a/arch/mips/ath79/mach-db120.c
   2 +++ b/arch/mips/ath79/mach-db120.c
   3 @@ -2,7 +2,7 @@
   4   * Atheros DB120 reference board support
   5   *
   6   * Copyright (c) 2011 Qualcomm Atheros
   7 - * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
   8 + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   9   *
  10   * All rights reserved.
  11   *
  12 @@ -37,17 +37,28 @@
  13   * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  14   */
  15
  16 +#include <linux/mtd/mtd.h>
  17 +#include <linux/mtd/partitions.h>
  18  #include <linux/pci.h>
  19 +#include <linux/phy.h>
  20 +#include <linux/platform_device.h>
  21  #include <linux/ath9k_platform.h>
  22 +#include <linux/ar8216_platform.h>
  23
  24 -#include "machtypes.h"
  25 +#include <asm/mach-ath79/ar71xx_regs.h>
  26 +
  27 +#include "common.h"
  28 +#include "dev-ap9x-pci.h"
  29 +#include "dev-eth.h"
  30  #include "dev-gpio-buttons.h"
  31  #include "dev-leds-gpio.h"
  32 +#include "dev-m25p80.h"
  33  #include "dev-spi.h"
  34  #include "dev-usb.h"
  35  #include "dev-wmac.h"
  36 -#include "pci.h"
  37 +#include "machtypes.h"
  38
  39 +#define DB120_GPIO_LED_USB             11
  40  #define DB120_GPIO_LED_WLAN_5G         12
  41  #define DB120_GPIO_LED_WLAN_2G         13
  42  #define DB120_GPIO_LED_STATUS          14
  43 @@ -58,8 +69,50 @@
  44  #define DB120_KEYS_POLL_INTERVAL       20      /* msecs */
  45  #define DB120_KEYS_DEBOUNCE_INTERVAL   (3 * DB120_KEYS_POLL_INTERVAL)
  46
  47 -#define DB120_WMAC_CALDATA_OFFSET 0x1000
  48 -#define DB120_PCIE_CALDATA_OFFSET 0x5000
  49 +#define DB120_MAC0_OFFSET              0
  50 +#define DB120_MAC1_OFFSET              6
  51 +#define DB120_WMAC_CALDATA_OFFSET      0x1000
  52 +#define DB120_PCIE_CALDATA_OFFSET      0x5000
  53 +
  54 +static struct mtd_partition db120_partitions[] = {
  55 +       {
  56 +               .name           = "u-boot",
  57 +               .offset         = 0,
  58 +               .size           = 0x040000,
  59 +               .mask_flags     = MTD_WRITEABLE,
  60 +       },
  61 +       {
  62 +               .name           = "u-boot-env",
  63 +               .offset         = 0x040000,
  64 +               .size           = 0x010000,
  65 +       },
  66 +       {
  67 +               .name           = "rootfs",
  68 +               .offset         = 0x050000,
  69 +               .size           = 0x630000,
  70 +       },
  71 +       {
  72 +               .name           = "uImage",
  73 +               .offset         = 0x680000,
  74 +               .size           = 0x160000,
  75 +       },
  76 +       {
  77 +               .name           = "NVRAM",
  78 +               .offset         = 0x7E0000,
  79 +               .size           = 0x010000,
  80 +       },
  81 +       {
  82 +               .name           = "ART",
  83 +               .offset         = 0x7F0000,
  84 +               .size           = 0x010000,
  85 +               .mask_flags     = MTD_WRITEABLE,
  86 +       }
  87 +};
  88 +
  89 +static struct flash_platform_data db120_flash_data = {
  90 +       .parts          = db120_partitions,
  91 +       .nr_parts       = ARRAY_SIZE(db120_partitions),
  92 +};
  93
  94  static struct gpio_led db120_leds_gpio[] __initdata = {
  95         {
  96 @@ -82,6 +135,11 @@ static struct gpio_led db120_leds_gpio[]
  97                 .gpio           = DB120_GPIO_LED_WLAN_2G,
  98                 .active_low     = 1,
  99         },
 100 +       {
 101 +               .name           = "db120:green:usb",
 102 +               .gpio           = DB120_GPIO_LED_USB,
 103 +               .active_low     = 1,
 104 +       }
 105  };
 106
 107  static struct gpio_keys_button db120_gpio_keys[] __initdata = {
 108 @@ -95,66 +153,89 @@ static struct gpio_keys_button db120_gpi
 109         },
 110  };
 111
 112 -static struct ath79_spi_controller_data db120_spi0_data = {
 113 -       .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
 114 -       .cs_line = 0,
 115 +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
 116 +       .mode = AR8327_PAD_MAC_RGMII,
 117 +       .txclk_delay_en = true,
 118 +       .rxclk_delay_en = true,
 119 +       .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
 120 +       .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
 121  };
 122
 123 -static struct spi_board_info db120_spi_info[] = {
 124 -       {
 125 -               .bus_num        = 0,
 126 -               .chip_select    = 0,
 127 -               .max_speed_hz   = 25000000,
 128 -               .modalias       = "s25sl064a",
 129 -               .controller_data = &db120_spi0_data,
 130 +static struct ar8327_platform_data db120_ar8327_data = {
 131 +       .pad0_cfg = &db120_ar8327_pad0_cfg,
 132 +       .cpuport_cfg = {
 133 +               .force_link = 1,
 134 +               .speed = AR8327_PORT_SPEED_1000,
 135 +               .duplex = 1,
 136 +               .txpause = 1,
 137 +               .rxpause = 1,
 138         }
 139  };
 140
 141 -static struct ath79_spi_platform_data db120_spi_data = {
 142 -       .bus_num        = 0,
 143 -       .num_chipselect = 1,
 144 +static struct mdio_board_info db120_mdio0_info[] = {
 145 +       {
 146 +               .bus_id = "ag71xx-mdio.0",
 147 +               .phy_addr = 0,
 148 +               .platform_data = &db120_ar8327_data,
 149 +       },
 150  };
 151
 152 -#ifdef CONFIG_PCI
 153 -static struct ath9k_platform_data db120_ath9k_data;
 154 -
 155 -static int db120_pci_plat_dev_init(struct pci_dev *dev)
 156 +static void __init db120_gmac_setup(void)
 157  {
 158 -       switch (PCI_SLOT(dev->devfn)) {
 159 -       case 0:
 160 -               dev->dev.platform_data = &db120_ath9k_data;
 161 -               break;
 162 -       }
 163 +       void __iomem *base;
 164 +       u32 t;
 165
 166 -       return 0;
 167 -}
 168 +       base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
 169
 170 -static void __init db120_pci_init(u8 *eeprom)
 171 -{
 172 -       memcpy(db120_ath9k_data.eeprom_data, eeprom,
 173 -              sizeof(db120_ath9k_data.eeprom_data));
 174 +       t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 175 +       t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
 176 +              AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
 177 +       t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
 178 +
 179 +       __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
 180
 181 -       ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
 182 -       ath79_register_pci();
 183 +       iounmap(base);
 184  }
 185 -#else
 186 -static inline void db120_pci_init(void) {}
 187 -#endif /* CONFIG_PCI */
 188
 189  static void __init db120_setup(void)
 190  {
 191         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 192
 193 +       ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
 194 +       ath79_register_m25p80(&db120_flash_data);
 195 +
 196         ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
 197                                  db120_leds_gpio);
 198         ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
 199                                         ARRAY_SIZE(db120_gpio_keys),
 200                                         db120_gpio_keys);
 201 -       ath79_register_spi(&db120_spi_data, db120_spi_info,
 202 -                          ARRAY_SIZE(db120_spi_info));
 203         ath79_register_usb();
 204         ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
 205 -       db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
 206 +       ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
 207 +
 208 +       db120_gmac_setup();
 209 +
 210 +       ath79_register_mdio(1, 0x0);
 211 +       ath79_register_mdio(0, 0x0);
 212 +
 213 +       ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
 214 +
 215 +       mdiobus_register_board_info(db120_mdio0_info,
 216 +                                   ARRAY_SIZE(db120_mdio0_info));
 217 +
 218 +       /* GMAC0 is connected to an AR8327 switch */
 219 +       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 220 +       ath79_eth0_data.phy_mask = BIT(0);
 221 +       ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 222 +       ath79_register_eth(0);
 223 +
 224 +       /* GMAC1 is connected to the internal switch */
 225 +       ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
 226 +       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
 227 +       ath79_eth1_data.speed = SPEED_1000;
 228 +       ath79_eth1_data.duplex = DUPLEX_FULL;
 229 +
 230 +       ath79_register_eth(1);
 231  }
 232
 233  MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
 234 --- a/arch/mips/ath79/Kconfig
 235 +++ b/arch/mips/ath79/Kconfig
 236 @@ -31,9 +31,11 @@ config ATH79_MACH_AP81
 237  config ATH79_MACH_DB120
 238         bool "Atheros DB120 reference board"
 239         select SOC_AR934X
 240 +       select ATH79_DEV_AP9X_PCI if PCI
 241 +       select ATH79_DEV_ETH
 242         select ATH79_DEV_GPIO_BUTTONS
 243         select ATH79_DEV_LEDS_GPIO
 244 -       select ATH79_DEV_SPI
 245 +       select ATH79_DEV_M25P80
 246         select ATH79_DEV_USB
 247         select ATH79_DEV_WMAC
 248         help