1 From 98bfbb0b3f126d93076377fcd9553a493e45e304 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Wed, 14 Mar 2012 10:45:26 +0100
4 Subject: [PATCH 31/47] MIPS: ath79: add AR934X specific glue to ath79_device_reset_{clear,set}
6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
8 Cc: linux-mips@linux-mips.org
9 Cc: mcgrof@infradead.org
10 Patchwork: https://patchwork.linux-mips.org/patch/3511/
11 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
13 arch/mips/ath79/common.c | 9 ++++++++-
14 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
15 2 files changed, 9 insertions(+), 1 deletions(-)
17 --- a/arch/mips/ath79/common.c
18 +++ b/arch/mips/ath79/common.c
21 * Atheros AR71XX/AR724X/AR913X common routines
23 - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
24 + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
25 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
26 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
28 + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
30 * This program is free software; you can redistribute it and/or modify it
31 * under the terms of the GNU General Public License version 2 as published
32 * by the Free Software Foundation.
33 @@ -67,6 +70,8 @@ void ath79_device_reset_set(u32 mask)
34 reg = AR913X_RESET_REG_RESET_MODULE;
35 else if (soc_is_ar933x())
36 reg = AR933X_RESET_REG_RESET_MODULE;
37 + else if (soc_is_ar934x())
38 + reg = AR934X_RESET_REG_RESET_MODULE;
42 @@ -91,6 +96,8 @@ void ath79_device_reset_clear(u32 mask)
43 reg = AR913X_RESET_REG_RESET_MODULE;
44 else if (soc_is_ar933x())
45 reg = AR933X_RESET_REG_RESET_MODULE;
46 + else if (soc_is_ar934x())
47 + reg = AR934X_RESET_REG_RESET_MODULE;
51 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
52 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
54 #define AR933X_RESET_REG_RESET_MODULE 0x1c
55 #define AR933X_RESET_REG_BOOTSTRAP 0xac
57 +#define AR934X_RESET_REG_RESET_MODULE 0x1c
58 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
59 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac