target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx_phy.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
  17 {
  18         switch (ag->speed) {
  19         case SPEED_1000:
  20                 return "1000";
  21         case SPEED_100:
  22                 return "100";
  23         case SPEED_10:
  24                 return "10";
  25         }
  26
  27         return "?";
  28 }
  29
  30 #define AR71XX_PLL_VAL_1000     0x00110000
  31 #define AR71XX_PLL_VAL_100      0x00001099
  32 #define AR71XX_PLL_VAL_10       0x00991099
  33
  34 #define AR91XX_PLL_VAL_1000     0x1a000000
  35 #define AR91XX_PLL_VAL_100      0x13000a44
  36 #define AR91XX_PLL_VAL_10       0x00441099
  37
  38 static void ag71xx_phy_link_update(struct ag71xx *ag)
  39 {
  40         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
  41         u32 cfg2;
  42         u32 ifctl;
  43         u32 pll;
  44         u32 fifo5;
  45         u32 mii_speed;
  46
  47         if (!ag->link) {
  48                 netif_carrier_off(ag->dev);
  49                 if (netif_msg_link(ag))
  50                         printk(KERN_INFO "%s: link down\n", ag->dev->name);
  51                 return;
  52         }
  53
  54         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
  55         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
  56         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
  57
  58         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
  59         ifctl &= ~(MAC_IFCTL_SPEED);
  60
  61         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
  62         fifo5 &= ~FIFO_CFG5_BM;
  63
  64         switch (ag->speed) {
  65         case SPEED_1000:
  66                 mii_speed =  MII_CTRL_SPEED_1000;
  67                 cfg2 |= MAC_CFG2_IF_1000;
  68                 pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_1000
  69                                        : AR71XX_PLL_VAL_1000;
  70                 fifo5 |= FIFO_CFG5_BM;
  71                 break;
  72         case SPEED_100:
  73                 mii_speed = MII_CTRL_SPEED_100;
  74                 cfg2 |= MAC_CFG2_IF_10_100;
  75                 ifctl |= MAC_IFCTL_SPEED;
  76                 pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_100
  77                                        : AR71XX_PLL_VAL_100;
  78                 break;
  79         case SPEED_10:
  80                 mii_speed = MII_CTRL_SPEED_10;
  81                 cfg2 |= MAC_CFG2_IF_10_100;
  82                 pll = pdata->is_ar91xx ? AR91XX_PLL_VAL_10
  83                                        : AR71XX_PLL_VAL_10;
  84                 break;
  85         default:
  86                 BUG();
  87                 return;
  88         }
  89
  90         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
  91                         pdata->is_ar91xx ? 0x780fff : 0x008001ff);
  92         pdata->set_pll(pll);
  93         ag71xx_mii_ctrl_set_speed(ag, mii_speed);
  94
  95         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
  96         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
  97         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
  98
  99         netif_carrier_on(ag->dev);
 100         if (netif_msg_link(ag))
 101                 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
 102                         ag->dev->name,
 103                         ag71xx_speed_str(ag),
 104                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
 105
 106         DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
 107                 ag->dev->name,
 108                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
 109                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
 110                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
 111
 112         DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
 113                 ag->dev->name,
 114                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
 115                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
 116                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
 117
 118         DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
 119                 ag->dev->name,
 120                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
 121                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
 122                 ag71xx_mii_ctrl_rr(ag));
 123 }
 124
 125 static void ag71xx_phy_link_adjust(struct net_device *dev)
 126 {
 127         struct ag71xx *ag = netdev_priv(dev);
 128         struct phy_device *phydev = ag->phy_dev;
 129         unsigned long flags;
 130         int status_change = 0;
 131
 132         spin_lock_irqsave(&ag->lock, flags);
 133
 134         if (phydev->link) {
 135                 if (ag->duplex != phydev->duplex
 136                     || ag->speed != phydev->speed) {
 137                         status_change = 1;
 138                 }
 139         }
 140
 141         if (phydev->link != ag->link) {
 142                 if (phydev->link)
 143                         netif_schedule(dev);
 144
 145                 status_change = 1;
 146         }
 147
 148         ag->link = phydev->link;
 149         ag->duplex = phydev->duplex;
 150         ag->speed = phydev->speed;
 151
 152         if (status_change)
 153                 ag71xx_phy_link_update(ag);
 154
 155         spin_unlock_irqrestore(&ag->lock, flags);
 156 }
 157
 158 void ag71xx_phy_start(struct ag71xx *ag)
 159 {
 160         if (ag->phy_dev) {
 161                 phy_start(ag->phy_dev);
 162         } else {
 163                 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 164
 165                 ag->duplex = pdata->duplex;
 166                 ag->speed = pdata->speed;
 167                 ag->link = 1;
 168                 ag71xx_phy_link_update(ag);
 169         }
 170 }
 171
 172 void ag71xx_phy_stop(struct ag71xx *ag)
 173 {
 174         if (ag->phy_dev) {
 175                 phy_stop(ag->phy_dev);
 176         } else {
 177                 ag->duplex = -1;
 178                 ag->link = 0;
 179                 ag->speed = 0;
 180                 ag71xx_phy_link_update(ag);
 181         }
 182 }
 183
 184 int ag71xx_phy_connect(struct ag71xx *ag)
 185 {
 186         struct net_device *dev = ag->dev;
 187         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 188         struct phy_device *phydev = NULL;
 189         int phy_count = 0;
 190         int phy_addr;
 191
 192         if (ag->mii_bus && pdata->phy_mask) {
 193                 /* TODO: use mutex of the mdio bus? */
 194                 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
 195                         if (!(pdata->phy_mask & (1 << phy_addr)))
 196                                 continue;
 197
 198                         if (ag->mii_bus->phy_map[phy_addr] == NULL)
 199                                 continue;
 200
 201                         DBG("%s: PHY found at %s, uid=%08x\n",
 202                                 dev->name,
 203                                 ag->mii_bus->phy_map[phy_addr]->dev.bus_id,
 204                                 ag->mii_bus->phy_map[phy_addr]->phy_id);
 205
 206                         if (phydev == NULL)
 207                                 phydev = ag->mii_bus->phy_map[phy_addr];
 208
 209                         phy_count++;
 210                 }
 211         }
 212
 213         switch (phy_count) {
 214         case 1:
 215                 ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
 216                         &ag71xx_phy_link_adjust, 0, pdata->phy_if_mode);
 217
 218                 if (IS_ERR(ag->phy_dev)) {
 219                         printk(KERN_ERR "%s: could not connect to PHY at %s\n",
 220                                 dev->name, phydev->dev.bus_id);
 221                         return PTR_ERR(ag->phy_dev);
 222                 }
 223
 224                 /* mask with MAC supported features */
 225                 if (pdata->has_gbit)
 226                         phydev->supported &= PHY_GBIT_FEATURES;
 227                 else
 228                         phydev->supported &= PHY_BASIC_FEATURES;
 229
 230                 phydev->advertising = phydev->supported;
 231
 232                 printk(KERN_DEBUG "%s: connected to PHY at %s "
 233                         "[uid=%08x, driver=%s]\n",
 234                         dev->name, phydev->dev.bus_id,
 235                         phydev->phy_id, phydev->drv->name);
 236
 237                 ag->link = 0;
 238                 ag->speed = 0;
 239                 ag->duplex = -1;
 240                 break;
 241
 242         default:
 243                 switch (pdata->speed) {
 244                 case SPEED_10:
 245                 case SPEED_100:
 246                 case SPEED_1000:
 247                         break;
 248                 default:
 249                         printk(KERN_ERR "%s: invalid speed specified\n",
 250                                 dev->name);
 251                         return -EINVAL;
 252                 }
 253
 254                 ag->phy_dev = NULL;
 255                 printk(KERN_DEBUG "%s: connected to %d PHYs\n",
 256                         dev->name, phy_count);
 257                 break;
 258         }
 259
 260         return 0;
 261 }
 262
 263 void ag71xx_phy_disconnect(struct ag71xx *ag)
 264 {
 265         if (ag->phy_dev)
 266                 phy_disconnect(ag->phy_dev);
 267 }