2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_debug = -1;
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
46 static void ag71xx_dump_regs(struct ag71xx *ag)
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
89 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
90 ring->descs, ring->descs_dma);
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
97 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
107 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
119 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
121 struct ag71xx_ring *ring = &ag->tx_ring;
122 struct net_device *dev = ag->dev;
124 while (ring->curr != ring->dirty) {
125 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
127 if (!ag71xx_desc_empty(&ring->descs[i])) {
128 ring->descs[i].ctrl = 0;
129 dev->stats.tx_errors++;
132 if (ring->buf[i].skb)
133 dev_kfree_skb_any(ring->buf[i].skb);
135 ring->buf[i].skb = NULL;
140 /* flush descriptors */
145 static void ag71xx_ring_tx_init(struct ag71xx *ag)
147 struct ag71xx_ring *ring = &ag->tx_ring;
150 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
151 ring->descs[i].next = (u32) (ring->descs_dma +
152 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
154 ring->descs[i].ctrl = DESC_EMPTY;
155 ring->buf[i].skb = NULL;
158 /* flush descriptors */
165 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
167 struct ag71xx_ring *ring = &ag->rx_ring;
173 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
174 if (ring->buf[i].skb)
175 kfree_skb(ring->buf[i].skb);
179 static int ag71xx_ring_rx_init(struct ag71xx *ag)
181 struct ag71xx_ring *ring = &ag->rx_ring;
186 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
187 ring->descs[i].next = (u32) (ring->descs_dma +
188 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
190 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
193 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
199 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
203 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
205 ring->buf[i].skb = skb;
206 ring->descs[i].data = virt_to_phys(skb->data);
207 ring->descs[i].ctrl = DESC_EMPTY;
210 /* flush descriptors */
219 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
221 struct ag71xx_ring *ring = &ag->rx_ring;
225 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
228 i = ring->dirty % AG71XX_RX_RING_SIZE;
230 if (ring->buf[i].skb == NULL) {
233 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
235 printk(KERN_ERR "%s: no memory for skb\n",
240 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
243 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
246 ring->buf[i].skb = skb;
247 ring->descs[i].data = virt_to_phys(skb->data);
250 ring->descs[i].ctrl = DESC_EMPTY;
254 /* flush descriptors */
257 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
262 static int ag71xx_rings_init(struct ag71xx *ag)
266 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
270 ag71xx_ring_tx_init(ag);
272 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
276 ret = ag71xx_ring_rx_init(ag);
280 static void ag71xx_rings_cleanup(struct ag71xx *ag)
282 ag71xx_ring_rx_clean(ag);
283 ag71xx_ring_free(&ag->rx_ring);
285 ag71xx_ring_tx_clean(ag);
286 ag71xx_ring_free(&ag->tx_ring);
289 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
293 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
294 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
296 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
298 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
299 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
302 #define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
303 MAC_CFG1_SRX | MAC_CFG1_STX)
304 #define AR71XX_FIFO_CFG5_INIT 0x0007ffef
306 #define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
307 MAC_CFG1_SRX | MAC_CFG1_STX | \
308 MAC_CFG1_TFC | MAC_CFG1_RFC)
309 #define AR91XX_FIFO_CFG5_INIT 0x0007efef
311 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
313 static void ag71xx_dma_reset(struct ag71xx *ag)
317 ag71xx_dump_dma_regs(ag);
320 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
321 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
323 /* clear descriptor addresses */
324 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
325 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
327 /* clear pending RX/TX interrupts */
328 for (i = 0; i < 256; i++) {
329 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
330 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
333 /* clear pending errors */
334 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
335 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
337 if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
338 printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
341 if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
342 printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
345 ag71xx_dump_dma_regs(ag);
348 static void ag71xx_hw_init(struct ag71xx *ag)
350 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
352 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
355 ar71xx_device_stop(pdata->reset_bit);
357 ar71xx_device_start(pdata->reset_bit);
360 /* setup MAC configuration registers */
361 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
362 pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
363 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
364 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
366 /* setup max frame length */
367 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
369 /* setup MII interface type */
370 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
372 /* setup FIFO configuration registers */
373 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
374 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
375 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
376 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
377 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
378 pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
379 : AR71XX_FIFO_CFG5_INIT);
381 ag71xx_dma_reset(ag);
384 static void ag71xx_hw_start(struct ag71xx *ag)
386 /* start RX engine */
387 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
389 /* enable interrupts */
390 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
393 static void ag71xx_hw_stop(struct ag71xx *ag)
395 /* disable all interrupts */
396 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
398 ag71xx_dma_reset(ag);
401 static int ag71xx_open(struct net_device *dev)
403 struct ag71xx *ag = netdev_priv(dev);
406 ret = ag71xx_rings_init(ag);
410 napi_enable(&ag->napi);
412 netif_carrier_off(dev);
413 ag71xx_phy_start(ag);
415 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
416 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
418 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
422 netif_start_queue(dev);
427 ag71xx_rings_cleanup(ag);
431 static int ag71xx_stop(struct net_device *dev)
433 struct ag71xx *ag = netdev_priv(dev);
436 spin_lock_irqsave(&ag->lock, flags);
438 netif_stop_queue(dev);
442 netif_carrier_off(dev);
445 napi_disable(&ag->napi);
447 spin_unlock_irqrestore(&ag->lock, flags);
449 ag71xx_rings_cleanup(ag);
454 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
456 struct ag71xx *ag = netdev_priv(dev);
457 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
458 struct ag71xx_ring *ring = &ag->tx_ring;
459 struct ag71xx_desc *desc;
463 i = ring->curr % AG71XX_TX_RING_SIZE;
464 desc = &ring->descs[i];
466 spin_lock_irqsave(&ag->lock, flags);
468 spin_unlock_irqrestore(&ag->lock, flags);
470 if (!ag71xx_desc_empty(desc))
474 DBG("%s: packet len is too small\n", ag->dev->name);
478 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
480 ring->buf[i].skb = skb;
482 /* setup descriptor fields */
483 desc->data = virt_to_phys(skb->data);
484 desc->ctrl = (skb->len & DESC_PKTLEN_M);
486 /* flush descriptor */
490 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
491 DBG("%s: tx queue full\n", ag->dev->name);
492 netif_stop_queue(dev);
495 DBG("%s: packet injected into TX queue\n", ag->dev->name);
497 /* enable TX engine */
498 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
500 dev->trans_start = jiffies;
505 dev->stats.tx_dropped++;
511 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
513 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
514 struct ag71xx *ag = netdev_priv(dev);
519 if (ag->phy_dev == NULL)
522 spin_lock_irq(&ag->lock);
523 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
524 spin_unlock_irq(&ag->lock);
529 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
535 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
542 if (ag->phy_dev == NULL)
545 return phy_mii_ioctl(ag->phy_dev, data, cmd);
554 static void ag71xx_tx_packets(struct ag71xx *ag)
556 struct ag71xx_ring *ring = &ag->tx_ring;
559 DBG("%s: processing TX ring\n", ag->dev->name);
562 while (ring->dirty != ring->curr) {
563 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
564 struct ag71xx_desc *desc = &ring->descs[i];
565 struct sk_buff *skb = ring->buf[i].skb;
567 if (!ag71xx_desc_empty(desc))
570 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
572 ag->dev->stats.tx_bytes += skb->len;
573 ag->dev->stats.tx_packets++;
575 dev_kfree_skb_any(skb);
576 ring->buf[i].skb = NULL;
582 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
584 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
585 netif_wake_queue(ag->dev);
589 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
591 struct net_device *dev = ag->dev;
592 struct ag71xx_ring *ring = &ag->rx_ring;
595 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
596 dev->name, limit, ring->curr, ring->dirty);
598 while (done < limit) {
599 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
600 struct ag71xx_desc *desc = &ring->descs[i];
604 if (ag71xx_desc_empty(desc))
607 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
612 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
614 skb = ring->buf[i].skb;
615 pktlen = ag71xx_desc_pktlen(desc);
616 pktlen -= ETH_FCS_LEN;
618 skb_put(skb, pktlen);
621 skb->protocol = eth_type_trans(skb, dev);
622 skb->ip_summed = CHECKSUM_NONE;
624 netif_receive_skb(skb);
626 dev->last_rx = jiffies;
627 dev->stats.rx_packets++;
628 dev->stats.rx_bytes += pktlen;
630 ring->buf[i].skb = NULL;
634 if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
635 ag71xx_ring_rx_refill(ag);
638 ag71xx_ring_rx_refill(ag);
640 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
641 dev->name, ring->curr, ring->dirty, done);
646 static int ag71xx_poll(struct napi_struct *napi, int limit)
648 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
649 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
650 struct net_device *dev = ag->dev;
656 ag71xx_tx_packets(ag);
658 DBG("%s: processing RX ring\n", dev->name);
659 done = ag71xx_rx_packets(ag, limit);
661 /* TODO: add OOM handler */
663 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
664 if (unlikely(status & RX_STATUS_OF)) {
665 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
666 dev->stats.rx_fifo_errors++;
669 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
672 if ((done < limit) && ((status & RX_STATUS_PR) == 0)) {
673 DBG("%s: disable polling mode, done=%d, status=%x\n",
674 dev->name, done, status);
676 netif_rx_complete(dev, napi);
678 /* enable interrupts */
679 spin_lock_irqsave(&ag->lock, flags);
680 ag71xx_int_enable(ag, AG71XX_INT_POLL);
681 spin_unlock_irqrestore(&ag->lock, flags);
685 DBG("%s: stay in polling mode, done=%d, status=%x\n",
686 dev->name, done, status);
690 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
692 struct net_device *dev = dev_id;
693 struct ag71xx *ag = netdev_priv(dev);
696 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
697 ag71xx_dump_intr(ag, "raw", status);
698 status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
699 ag71xx_dump_intr(ag, "masked", status);
701 if (unlikely(!status))
704 if (unlikely(status & AG71XX_INT_ERR)) {
705 if (status & AG71XX_INT_TX_BE) {
706 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
707 dev_err(&dev->dev, "TX BUS error\n");
709 if (status & AG71XX_INT_RX_BE) {
710 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
711 dev_err(&dev->dev, "RX BUS error\n");
716 if (unlikely(status & AG71XX_INT_TX_UR)) {
717 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_UR);
718 DBG("%s: TX underrun\n", dev->name);
722 if (likely(status & AG71XX_INT_POLL)) {
723 ag71xx_int_disable(ag, AG71XX_INT_POLL);
724 DBG("%s: enable polling mode\n", dev->name);
725 netif_rx_schedule(dev, &ag->napi);
731 static void ag71xx_set_multicast_list(struct net_device *dev)
736 static int __init ag71xx_probe(struct platform_device *pdev)
738 struct net_device *dev;
739 struct resource *res;
741 struct ag71xx_platform_data *pdata;
744 pdata = pdev->dev.platform_data;
746 dev_err(&pdev->dev, "no platform data specified\n");
751 dev = alloc_etherdev(sizeof(*ag));
753 dev_err(&pdev->dev, "alloc_etherdev failed\n");
758 SET_NETDEV_DEV(dev, &pdev->dev);
760 ag = netdev_priv(dev);
763 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
764 ag->msg_enable = netif_msg_init(ag71xx_debug,
765 AG71XX_DEFAULT_MSG_ENABLE);
766 spin_lock_init(&ag->lock);
768 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
770 dev_err(&pdev->dev, "no mac_base resource found\n");
775 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
777 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
782 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
784 dev_err(&pdev->dev, "no mac_base2 resource found\n");
786 goto err_unmap_base1;
789 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
791 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
793 goto err_unmap_base1;
796 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
798 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
800 goto err_unmap_base2;
803 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
805 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
807 goto err_unmap_base2;
810 dev->irq = platform_get_irq(pdev, 0);
811 err = request_irq(dev->irq, ag71xx_interrupt,
812 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
815 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
816 goto err_unmap_mii_ctrl;
819 dev->base_addr = (unsigned long)ag->mac_base;
820 dev->open = ag71xx_open;
821 dev->stop = ag71xx_stop;
822 dev->hard_start_xmit = ag71xx_hard_start_xmit;
823 dev->set_multicast_list = ag71xx_set_multicast_list;
824 dev->do_ioctl = ag71xx_do_ioctl;
825 dev->ethtool_ops = &ag71xx_ethtool_ops;
827 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
829 if (is_valid_ether_addr(pdata->mac_addr))
830 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
832 dev->dev_addr[0] = 0xde;
833 dev->dev_addr[1] = 0xad;
834 get_random_bytes(&dev->dev_addr[2], 3);
835 dev->dev_addr[5] = pdev->id & 0xff;
838 err = register_netdev(dev);
840 dev_err(&pdev->dev, "unable to register net device\n");
844 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
845 dev->name, dev->base_addr, dev->irq);
847 ag71xx_dump_regs(ag);
851 ag71xx_dump_regs(ag);
853 /* Reset the mdio bus explicitly */
855 mutex_lock(&ag->mii_bus->mdio_lock);
856 ag->mii_bus->reset(ag->mii_bus);
857 mutex_unlock(&ag->mii_bus->mdio_lock);
860 err = ag71xx_phy_connect(ag);
862 goto err_unregister_netdev;
864 platform_set_drvdata(pdev, dev);
868 err_unregister_netdev:
869 unregister_netdev(dev);
871 free_irq(dev->irq, dev);
873 iounmap(ag->mii_ctrl);
875 iounmap(ag->mac_base2);
877 iounmap(ag->mac_base);
881 platform_set_drvdata(pdev, NULL);
885 static int __exit ag71xx_remove(struct platform_device *pdev)
887 struct net_device *dev = platform_get_drvdata(pdev);
890 struct ag71xx *ag = netdev_priv(dev);
892 ag71xx_phy_disconnect(ag);
893 unregister_netdev(dev);
894 free_irq(dev->irq, dev);
895 iounmap(ag->mii_ctrl);
896 iounmap(ag->mac_base2);
897 iounmap(ag->mac_base);
899 platform_set_drvdata(pdev, NULL);
905 static struct platform_driver ag71xx_driver = {
906 .probe = ag71xx_probe,
907 .remove = __exit_p(ag71xx_remove),
909 .name = AG71XX_DRV_NAME,
913 static int __init ag71xx_module_init(void)
917 ret = ag71xx_mdio_driver_init();
921 ret = platform_driver_register(&ag71xx_driver);
928 ag71xx_mdio_driver_exit();
933 static void __exit ag71xx_module_exit(void)
935 platform_driver_unregister(&ag71xx_driver);
936 ag71xx_mdio_driver_exit();
939 module_init(ag71xx_module_init);
940 module_exit(ag71xx_module_exit);
942 MODULE_VERSION(AG71XX_DRV_VERSION);
943 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
944 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
945 MODULE_LICENSE("GPL v2");
946 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);