target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/serial_8250.h>
  17 #include <linux/bootmem.h>
  18
  19 #include <asm/bootinfo.h>
  20 #include <asm/time.h>           /* for mips_hpt_frequency */
  21 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  22 #include <asm/mips_machine.h>
  23
  24 #include <asm/mach-ar71xx/ar71xx.h>
  25 #include <asm/mach-ar71xx/pci.h>
  26
  27 #include "devices.h"
  28
  29 #define AR71XX_SYS_TYPE_LEN     64
  30 #define AR71XX_BASE_FREQ        40000000
  31 #define AR91XX_BASE_FREQ        5000000
  32 #define AR724X_BASE_FREQ        5000000
  33
  34 enum ar71xx_mach_type ar71xx_mach;
  35
  36 u32 ar71xx_cpu_freq;
  37 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  38
  39 u32 ar71xx_ahb_freq;
  40 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  41
  42 u32 ar71xx_ddr_freq;
  43 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  44
  45 enum ar71xx_soc_type ar71xx_soc;
  46 EXPORT_SYMBOL_GPL(ar71xx_soc);
  47
  48 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  49
  50 static void ar71xx_restart(char *command)
  51 {
  52         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  53         for (;;)
  54                 if (cpu_wait)
  55                         cpu_wait();
  56 }
  57
  58 static void ar71xx_halt(void)
  59 {
  60         while (1)
  61                 cpu_wait();
  62 }
  63
  64 static void __init ar71xx_detect_mem_size(void)
  65 {
  66         unsigned long size;
  67
  68         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  69              size <<= 1 ) {
  70                 if (!memcmp(ar71xx_detect_mem_size,
  71                             ar71xx_detect_mem_size + size, 1024))
  72                         break;
  73         }
  74
  75         add_memory_region(0, size, BOOT_MEM_RAM);
  76 }
  77
  78 static void __init ar71xx_detect_sys_type(void)
  79 {
  80         char *chip = "????";
  81         u32 id;
  82         u32 major;
  83         u32 minor;
  84         u32 rev = 0;
  85
  86         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
  87         major = id & REV_ID_MAJOR_MASK;
  88
  89         switch (major) {
  90         case REV_ID_MAJOR_AR71XX:
  91                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  92                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  93                 rev &= AR71XX_REV_ID_REVISION_MASK;
  94                 switch (minor) {
  95                 case AR71XX_REV_ID_MINOR_AR7130:
  96                         ar71xx_soc = AR71XX_SOC_AR7130;
  97                         chip = "7130";
  98                         break;
  99
 100                 case AR71XX_REV_ID_MINOR_AR7141:
 101                         ar71xx_soc = AR71XX_SOC_AR7141;
 102                         chip = "7141";
 103                         break;
 104
 105                 case AR71XX_REV_ID_MINOR_AR7161:
 106                         ar71xx_soc = AR71XX_SOC_AR7161;
 107                         chip = "7161";
 108                         break;
 109                 }
 110                 break;
 111
 112         case REV_ID_MAJOR_AR724X:
 113                 ar71xx_soc = AR71XX_SOC_AR7240;
 114                 chip = "7240";
 115                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 116                 break;
 117
 118         case REV_ID_MAJOR_AR913X:
 119                 minor = id & AR91XX_REV_ID_MINOR_MASK;
 120                 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
 121                 rev &= AR91XX_REV_ID_REVISION_MASK;
 122                 switch (minor) {
 123                 case AR91XX_REV_ID_MINOR_AR9130:
 124                         ar71xx_soc = AR71XX_SOC_AR9130;
 125                         chip = "9130";
 126                         break;
 127
 128                 case AR91XX_REV_ID_MINOR_AR9132:
 129                         ar71xx_soc = AR71XX_SOC_AR9132;
 130                         chip = "9132";
 131                         break;
 132                 }
 133                 break;
 134
 135         default:
 136                 panic("ar71xx: unknown chip id:0x%08x\n", id);
 137         }
 138
 139         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
 140 }
 141
 142 static void __init ar91xx_detect_sys_frequency(void)
 143 {
 144         u32 pll;
 145         u32 freq;
 146         u32 div;
 147
 148         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 149
 150         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 151         freq = div * AR91XX_BASE_FREQ;
 152
 153         ar71xx_cpu_freq = freq;
 154
 155         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 156         ar71xx_ddr_freq = freq / div;
 157
 158         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 159         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 160 }
 161
 162 static void __init ar71xx_detect_sys_frequency(void)
 163 {
 164         u32 pll;
 165         u32 freq;
 166         u32 div;
 167
 168         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 169
 170         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 171         freq = div * AR71XX_BASE_FREQ;
 172
 173         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 174         ar71xx_cpu_freq = freq / div;
 175
 176         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 177         ar71xx_ddr_freq = freq / div;
 178
 179         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 180         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 181 }
 182
 183 static void __init ar724x_detect_sys_frequency(void)
 184 {
 185         u32 pll;
 186         u32 freq;
 187         u32 div;
 188
 189         pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 190
 191         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
 192         freq = div * AR724X_BASE_FREQ;
 193
 194         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 195         freq *= div;
 196
 197         ar71xx_cpu_freq = freq;
 198
 199         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 200         ar71xx_ddr_freq = freq / div;
 201
 202         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 203         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 204 }
 205
 206 static void __init detect_sys_frequency(void)
 207 {
 208         switch (ar71xx_soc) {
 209         case AR71XX_SOC_AR7130:
 210         case AR71XX_SOC_AR7141:
 211         case AR71XX_SOC_AR7161:
 212                 ar71xx_detect_sys_frequency();
 213                 break;
 214
 215         case AR71XX_SOC_AR7240:
 216                 ar724x_detect_sys_frequency();
 217                 break;
 218
 219         case AR71XX_SOC_AR9130:
 220         case AR71XX_SOC_AR9132:
 221                 ar91xx_detect_sys_frequency();
 222                 break;
 223
 224         default:
 225                 BUG();
 226         }
 227 }
 228
 229 const char *get_system_type(void)
 230 {
 231         return ar71xx_sys_type;
 232 }
 233
 234 unsigned int __cpuinit get_c0_compare_irq(void)
 235 {
 236         return CP0_LEGACY_COMPARE_IRQ;
 237 }
 238
 239 void __init plat_mem_setup(void)
 240 {
 241         set_io_port_base(KSEG1);
 242
 243         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 244                                                 AR71XX_DDR_CTRL_SIZE);
 245
 246         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 247                                                 AR71XX_PLL_SIZE);
 248
 249         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 250                                                 AR71XX_RESET_SIZE);
 251
 252         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 253
 254         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 255                                                 AR71XX_USB_CTRL_SIZE);
 256
 257         ar71xx_detect_mem_size();
 258         ar71xx_detect_sys_type();
 259         detect_sys_frequency();
 260
 261         printk(KERN_INFO
 262                 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
 263                 ar71xx_sys_type,
 264                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 265                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 266                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
 267
 268         _machine_restart = ar71xx_restart;
 269         _machine_halt = ar71xx_halt;
 270         pm_power_off = ar71xx_halt;
 271 }
 272
 273 void __init plat_time_init(void)
 274 {
 275         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 276 }
 277
 278 static int __init ar71xx_machine_setup(void)
 279 {
 280         ar71xx_gpio_init();
 281
 282         ar71xx_add_device_uart();
 283         ar71xx_add_device_wdt();
 284
 285         mips_machine_setup(ar71xx_mach);
 286         return 0;
 287 }
 288
 289 arch_initcall(ar71xx_machine_setup);