target/linux/ar71xx/files/arch/mips/ar71xx/devices.c

   1 /*
   2  *  Atheros AR71xx SoC platform devices
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/serial_8250.h>
  22
  23 #include <asm/mach-ar71xx/ar71xx.h>
  24 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
  25
  26 #include "devices.h"
  27
  28 unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
  29
  30 static struct resource ar71xx_uart_resources[] = {
  31         {
  32                 .start  = AR71XX_UART_BASE,
  33                 .end    = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
  34                 .flags  = IORESOURCE_MEM,
  35         },
  36 };
  37
  38 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
  39 static struct plat_serial8250_port ar71xx_uart_data[] = {
  40         {
  41                 .mapbase        = AR71XX_UART_BASE,
  42                 .irq            = AR71XX_MISC_IRQ_UART,
  43                 .flags          = AR71XX_UART_FLAGS,
  44                 .iotype         = UPIO_MEM32,
  45                 .regshift       = 2,
  46         }, {
  47                 /* terminating entry */
  48         }
  49 };
  50
  51 static struct platform_device ar71xx_uart_device = {
  52         .name           = "serial8250",
  53         .id             = PLAT8250_DEV_PLATFORM,
  54         .resource       = ar71xx_uart_resources,
  55         .num_resources  = ARRAY_SIZE(ar71xx_uart_resources),
  56         .dev = {
  57                 .platform_data  = ar71xx_uart_data
  58         },
  59 };
  60
  61 static struct resource ar933x_uart_resources[] = {
  62         {
  63                 .start  = AR933X_UART_BASE,
  64                 .end    = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
  65                 .flags  = IORESOURCE_MEM,
  66         },
  67         {
  68                 .start  = AR71XX_MISC_IRQ_UART,
  69                 .end    = AR71XX_MISC_IRQ_UART,
  70                 .flags  = IORESOURCE_IRQ,
  71         },
  72 };
  73
  74 static struct ar933x_uart_platform_data ar933x_uart_data;
  75 static struct platform_device ar933x_uart_device = {
  76         .name           = "ar933x-uart",
  77         .id             = -1,
  78         .resource       = ar933x_uart_resources,
  79         .num_resources  = ARRAY_SIZE(ar933x_uart_resources),
  80         .dev = {
  81                 .platform_data  = &ar933x_uart_data,
  82         },
  83 };
  84
  85 void __init ar71xx_add_device_uart(void)
  86 {
  87         struct platform_device *pdev;
  88
  89         switch (ar71xx_soc) {
  90         case AR71XX_SOC_AR7130:
  91         case AR71XX_SOC_AR7141:
  92         case AR71XX_SOC_AR7161:
  93         case AR71XX_SOC_AR7240:
  94         case AR71XX_SOC_AR7241:
  95         case AR71XX_SOC_AR7242:
  96         case AR71XX_SOC_AR9130:
  97         case AR71XX_SOC_AR9132:
  98                 pdev = &ar71xx_uart_device;
  99                 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
 100                 break;
 101
 102         case AR71XX_SOC_AR9330:
 103         case AR71XX_SOC_AR9331:
 104                 pdev = &ar933x_uart_device;
 105                 ar933x_uart_data.uartclk = ar71xx_ref_freq;
 106                 break;
 107
 108         case AR71XX_SOC_AR9341:
 109         case AR71XX_SOC_AR9342:
 110         case AR71XX_SOC_AR9344:
 111                 pdev = &ar71xx_uart_device;
 112                 ar71xx_uart_data[0].uartclk = ar71xx_ref_freq;
 113                 break;
 114
 115         default:
 116                 BUG();
 117         }
 118
 119         platform_device_register(pdev);
 120 }
 121
 122 static struct resource ar71xx_mdio0_resources[] = {
 123         {
 124                 .name   = "mdio_base",
 125                 .flags  = IORESOURCE_MEM,
 126                 .start  = AR71XX_GE0_BASE,
 127                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
 128         }
 129 };
 130
 131 static struct ag71xx_mdio_platform_data ar71xx_mdio0_data;
 132
 133 struct platform_device ar71xx_mdio0_device = {
 134         .name           = "ag71xx-mdio",
 135         .id             = 0,
 136         .resource       = ar71xx_mdio0_resources,
 137         .num_resources  = ARRAY_SIZE(ar71xx_mdio0_resources),
 138         .dev = {
 139                 .platform_data = &ar71xx_mdio0_data,
 140         },
 141 };
 142
 143 static struct resource ar71xx_mdio1_resources[] = {
 144         {
 145                 .name   = "mdio_base",
 146                 .flags  = IORESOURCE_MEM,
 147                 .start  = AR71XX_GE1_BASE,
 148                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
 149         }
 150 };
 151
 152 static struct ag71xx_mdio_platform_data ar71xx_mdio1_data;
 153
 154 struct platform_device ar71xx_mdio1_device = {
 155         .name           = "ag71xx-mdio",
 156         .id             = 1,
 157         .resource       = ar71xx_mdio1_resources,
 158         .num_resources  = ARRAY_SIZE(ar71xx_mdio1_resources),
 159         .dev = {
 160                 .platform_data = &ar71xx_mdio1_data,
 161         },
 162 };
 163
 164 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
 165 {
 166         void __iomem *base;
 167         u32 t;
 168
 169         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 170
 171         t = __raw_readl(base + cfg_reg);
 172         t &= ~(3 << shift);
 173         t |=  (2 << shift);
 174         __raw_writel(t, base + cfg_reg);
 175         udelay(100);
 176
 177         __raw_writel(pll_val, base + pll_reg);
 178
 179         t |= (3 << shift);
 180         __raw_writel(t, base + cfg_reg);
 181         udelay(100);
 182
 183         t &= ~(3 << shift);
 184         __raw_writel(t, base + cfg_reg);
 185         udelay(100);
 186
 187         printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
 188                 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
 189
 190         iounmap(base);
 191 }
 192
 193 void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
 194 {
 195         struct platform_device *mdio_dev;
 196         struct ag71xx_mdio_platform_data *mdio_data;
 197
 198         if (id > 0) {
 199                 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
 200                 return;
 201         }
 202
 203         switch (ar71xx_soc) {
 204         case AR71XX_SOC_AR7241:
 205         case AR71XX_SOC_AR9330:
 206         case AR71XX_SOC_AR9331:
 207                 mdio_dev = &ar71xx_mdio1_device;
 208                 mdio_data = &ar71xx_mdio1_data;
 209                 break;
 210
 211         case AR71XX_SOC_AR7242:
 212                 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
 213                                AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
 214                                AR71XX_ETH0_PLL_SHIFT);
 215                 /* fall through */
 216         default:
 217                 mdio_dev = &ar71xx_mdio0_device;
 218                 mdio_data = &ar71xx_mdio0_data;
 219                 break;
 220         }
 221
 222         mdio_data->phy_mask = phy_mask;
 223
 224         switch (ar71xx_soc) {
 225         case AR71XX_SOC_AR7240:
 226         case AR71XX_SOC_AR7241:
 227         case AR71XX_SOC_AR9330:
 228         case AR71XX_SOC_AR9331:
 229                 mdio_data->is_ar7240 = 1;
 230                 break;
 231         default:
 232                 break;
 233         }
 234
 235         platform_device_register(mdio_dev);
 236 }
 237
 238 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
 239 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
 240
 241 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
 242 {
 243         struct ar71xx_eth_pll_data *pll_data;
 244         u32 pll_val;
 245
 246         switch (mac) {
 247         case 0:
 248                 pll_data = &ar71xx_eth0_pll_data;
 249                 break;
 250         case 1:
 251                 pll_data = &ar71xx_eth1_pll_data;
 252                 break;
 253         default:
 254                 BUG();
 255         }
 256
 257         switch (speed) {
 258         case SPEED_10:
 259                 pll_val = pll_data->pll_10;
 260                 break;
 261         case SPEED_100:
 262                 pll_val = pll_data->pll_100;
 263                 break;
 264         case SPEED_1000:
 265                 pll_val = pll_data->pll_1000;
 266                 break;
 267         default:
 268                 BUG();
 269         }
 270
 271         return pll_val;
 272 }
 273
 274 static void ar71xx_set_pll_ge0(int speed)
 275 {
 276         u32 val = ar71xx_get_eth_pll(0, speed);
 277
 278         ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
 279                         val, AR71XX_ETH0_PLL_SHIFT);
 280 }
 281
 282 static void ar71xx_set_pll_ge1(int speed)
 283 {
 284         u32 val = ar71xx_get_eth_pll(1, speed);
 285
 286         ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
 287                          val, AR71XX_ETH1_PLL_SHIFT);
 288 }
 289
 290 static void ar724x_set_pll_ge0(int speed)
 291 {
 292         /* TODO */
 293 }
 294
 295 static void ar724x_set_pll_ge1(int speed)
 296 {
 297         /* TODO */
 298 }
 299
 300 static void ar7242_set_pll_ge0(int speed)
 301 {
 302         u32 val = ar71xx_get_eth_pll(0, speed);
 303         void __iomem *base;
 304
 305         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 306         __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
 307         iounmap(base);
 308 }
 309
 310 static void ar91xx_set_pll_ge0(int speed)
 311 {
 312         u32 val = ar71xx_get_eth_pll(0, speed);
 313
 314         ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
 315                          val, AR91XX_ETH0_PLL_SHIFT);
 316 }
 317
 318 static void ar91xx_set_pll_ge1(int speed)
 319 {
 320         u32 val = ar71xx_get_eth_pll(1, speed);
 321
 322         ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
 323                          val, AR91XX_ETH1_PLL_SHIFT);
 324 }
 325
 326 static void ar933x_set_pll_ge0(int speed)
 327 {
 328         /* TODO */
 329 }
 330
 331 static void ar933x_set_pll_ge1(int speed)
 332 {
 333         /* TODO */
 334 }
 335
 336 static void ar934x_set_pll_ge0(int speed)
 337 {
 338         /* TODO */
 339 }
 340
 341 static void ar934x_set_pll_ge1(int speed)
 342 {
 343         /* TODO */
 344 }
 345
 346 static void ar71xx_ddr_flush_ge0(void)
 347 {
 348         ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
 349 }
 350
 351 static void ar71xx_ddr_flush_ge1(void)
 352 {
 353         ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
 354 }
 355
 356 static void ar724x_ddr_flush_ge0(void)
 357 {
 358         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
 359 }
 360
 361 static void ar724x_ddr_flush_ge1(void)
 362 {
 363         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
 364 }
 365
 366 static void ar91xx_ddr_flush_ge0(void)
 367 {
 368         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
 369 }
 370
 371 static void ar91xx_ddr_flush_ge1(void)
 372 {
 373         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
 374 }
 375
 376 static void ar933x_ddr_flush_ge0(void)
 377 {
 378         ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
 379 }
 380
 381 static void ar933x_ddr_flush_ge1(void)
 382 {
 383         ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
 384 }
 385
 386 static void ar934x_ddr_flush_ge0(void)
 387 {
 388         ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
 389 }
 390
 391 static void ar934x_ddr_flush_ge1(void)
 392 {
 393         ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
 394 }
 395
 396 static struct resource ar71xx_eth0_resources[] = {
 397         {
 398                 .name   = "mac_base",
 399                 .flags  = IORESOURCE_MEM,
 400                 .start  = AR71XX_GE0_BASE,
 401                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
 402         }, {
 403                 .name   = "mii_ctrl",
 404                 .flags  = IORESOURCE_MEM,
 405                 .start  = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
 406                 .end    = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
 407         }, {
 408                 .name   = "mac_irq",
 409                 .flags  = IORESOURCE_IRQ,
 410                 .start  = AR71XX_CPU_IRQ_GE0,
 411                 .end    = AR71XX_CPU_IRQ_GE0,
 412         },
 413 };
 414
 415 struct ag71xx_platform_data ar71xx_eth0_data = {
 416         .reset_bit      = RESET_MODULE_GE0_MAC,
 417 };
 418
 419 struct platform_device ar71xx_eth0_device = {
 420         .name           = "ag71xx",
 421         .id             = 0,
 422         .resource       = ar71xx_eth0_resources,
 423         .num_resources  = ARRAY_SIZE(ar71xx_eth0_resources),
 424         .dev = {
 425                 .platform_data = &ar71xx_eth0_data,
 426         },
 427 };
 428
 429 static struct resource ar71xx_eth1_resources[] = {
 430         {
 431                 .name   = "mac_base",
 432                 .flags  = IORESOURCE_MEM,
 433                 .start  = AR71XX_GE1_BASE,
 434                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
 435         }, {
 436                 .name   = "mii_ctrl",
 437                 .flags  = IORESOURCE_MEM,
 438                 .start  = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
 439                 .end    = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
 440         }, {
 441                 .name   = "mac_irq",
 442                 .flags  = IORESOURCE_IRQ,
 443                 .start  = AR71XX_CPU_IRQ_GE1,
 444                 .end    = AR71XX_CPU_IRQ_GE1,
 445         },
 446 };
 447
 448 struct ag71xx_platform_data ar71xx_eth1_data = {
 449         .reset_bit      = RESET_MODULE_GE1_MAC,
 450 };
 451
 452 struct platform_device ar71xx_eth1_device = {
 453         .name           = "ag71xx",
 454         .id             = 1,
 455         .resource       = ar71xx_eth1_resources,
 456         .num_resources  = ARRAY_SIZE(ar71xx_eth1_resources),
 457         .dev = {
 458                 .platform_data = &ar71xx_eth1_data,
 459         },
 460 };
 461
 462 #define AR71XX_PLL_VAL_1000     0x00110000
 463 #define AR71XX_PLL_VAL_100      0x00001099
 464 #define AR71XX_PLL_VAL_10       0x00991099
 465
 466 #define AR724X_PLL_VAL_1000     0x00110000
 467 #define AR724X_PLL_VAL_100      0x00001099
 468 #define AR724X_PLL_VAL_10       0x00991099
 469
 470 #define AR7242_PLL_VAL_1000     0x16000000
 471 #define AR7242_PLL_VAL_100      0x00000101
 472 #define AR7242_PLL_VAL_10       0x00001616
 473
 474 #define AR91XX_PLL_VAL_1000     0x1a000000
 475 #define AR91XX_PLL_VAL_100      0x13000a44
 476 #define AR91XX_PLL_VAL_10       0x00441099
 477
 478 #define AR933X_PLL_VAL_1000     0x00110000
 479 #define AR933X_PLL_VAL_100      0x00001099
 480 #define AR933X_PLL_VAL_10       0x00991099
 481
 482 #define AR934X_PLL_VAL_1000     0x00110000
 483 #define AR934X_PLL_VAL_100      0x00001099
 484 #define AR934X_PLL_VAL_10       0x00991099
 485
 486 static void __init ar71xx_init_eth_pll_data(unsigned int id)
 487 {
 488         struct ar71xx_eth_pll_data *pll_data;
 489         u32 pll_10, pll_100, pll_1000;
 490
 491         switch (id) {
 492         case 0:
 493                 pll_data = &ar71xx_eth0_pll_data;
 494                 break;
 495         case 1:
 496                 pll_data = &ar71xx_eth1_pll_data;
 497                 break;
 498         default:
 499                 BUG();
 500         }
 501
 502         switch (ar71xx_soc) {
 503         case AR71XX_SOC_AR7130:
 504         case AR71XX_SOC_AR7141:
 505         case AR71XX_SOC_AR7161:
 506                 pll_10 = AR71XX_PLL_VAL_10;
 507                 pll_100 = AR71XX_PLL_VAL_100;
 508                 pll_1000 = AR71XX_PLL_VAL_1000;
 509                 break;
 510
 511         case AR71XX_SOC_AR7240:
 512         case AR71XX_SOC_AR7241:
 513                 pll_10 = AR724X_PLL_VAL_10;
 514                 pll_100 = AR724X_PLL_VAL_100;
 515                 pll_1000 = AR724X_PLL_VAL_1000;
 516                 break;
 517
 518         case AR71XX_SOC_AR7242:
 519                 pll_10 = AR7242_PLL_VAL_10;
 520                 pll_100 = AR7242_PLL_VAL_100;
 521                 pll_1000 = AR7242_PLL_VAL_1000;
 522                 break;
 523
 524         case AR71XX_SOC_AR9130:
 525         case AR71XX_SOC_AR9132:
 526                 pll_10 = AR91XX_PLL_VAL_10;
 527                 pll_100 = AR91XX_PLL_VAL_100;
 528                 pll_1000 = AR91XX_PLL_VAL_1000;
 529                 break;
 530
 531         case AR71XX_SOC_AR9330:
 532         case AR71XX_SOC_AR9331:
 533                 pll_10 = AR933X_PLL_VAL_10;
 534                 pll_100 = AR933X_PLL_VAL_100;
 535                 pll_1000 = AR933X_PLL_VAL_1000;
 536                 break;
 537
 538         case AR71XX_SOC_AR9341:
 539         case AR71XX_SOC_AR9342:
 540         case AR71XX_SOC_AR9344:
 541                 pll_10 = AR934X_PLL_VAL_10;
 542                 pll_100 = AR934X_PLL_VAL_100;
 543                 pll_1000 = AR934X_PLL_VAL_1000;
 544                 break;
 545
 546         default:
 547                 BUG();
 548         }
 549
 550         if (!pll_data->pll_10)
 551                 pll_data->pll_10 = pll_10;
 552
 553         if (!pll_data->pll_100)
 554                 pll_data->pll_100 = pll_100;
 555
 556         if (!pll_data->pll_1000)
 557                 pll_data->pll_1000 = pll_1000;
 558 }
 559
 560 static int ar71xx_eth_instance __initdata;
 561 void __init ar71xx_add_device_eth(unsigned int id)
 562 {
 563         struct platform_device *pdev;
 564         struct ag71xx_platform_data *pdata;
 565
 566         ar71xx_init_eth_pll_data(id);
 567
 568         switch (id) {
 569         case 0:
 570                 switch (ar71xx_eth0_data.phy_if_mode) {
 571                 case PHY_INTERFACE_MODE_MII:
 572                         ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII;
 573                         break;
 574                 case PHY_INTERFACE_MODE_GMII:
 575                         ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII;
 576                         break;
 577                 case PHY_INTERFACE_MODE_RGMII:
 578                         ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII;
 579                         break;
 580                 case PHY_INTERFACE_MODE_RMII:
 581                         ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII;
 582                         break;
 583                 default:
 584                         printk(KERN_ERR "ar71xx: invalid PHY interface mode "
 585                                         "for eth0\n");
 586                         return;
 587                 }
 588                 pdev = &ar71xx_eth0_device;
 589                 break;
 590         case 1:
 591                 switch (ar71xx_eth1_data.phy_if_mode) {
 592                 case PHY_INTERFACE_MODE_RMII:
 593                         ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII;
 594                         break;
 595                 case PHY_INTERFACE_MODE_RGMII:
 596                         ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII;
 597                         break;
 598                 default:
 599                         printk(KERN_ERR "ar71xx: invalid PHY interface mode "
 600                                         "for eth1\n");
 601                         return;
 602                 }
 603                 pdev = &ar71xx_eth1_device;
 604                 break;
 605         default:
 606                 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
 607                 return;
 608         }
 609
 610         pdata = pdev->dev.platform_data;
 611
 612         switch (ar71xx_soc) {
 613         case AR71XX_SOC_AR7130:
 614                 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
 615                                       : ar71xx_ddr_flush_ge0;
 616                 pdata->set_pll =  id ? ar71xx_set_pll_ge1
 617                                      : ar71xx_set_pll_ge0;
 618                 break;
 619
 620         case AR71XX_SOC_AR7141:
 621         case AR71XX_SOC_AR7161:
 622                 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
 623                                       : ar71xx_ddr_flush_ge0;
 624                 pdata->set_pll =  id ? ar71xx_set_pll_ge1
 625                                      : ar71xx_set_pll_ge0;
 626                 pdata->has_gbit = 1;
 627                 break;
 628
 629         case AR71XX_SOC_AR7242:
 630                 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO |
 631                                               RESET_MODULE_GE0_PHY;
 632                 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO |
 633                                               RESET_MODULE_GE1_PHY;
 634                 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
 635                                       : ar724x_ddr_flush_ge0;
 636                 pdata->set_pll =  id ? ar724x_set_pll_ge1
 637                                      : ar7242_set_pll_ge0;
 638                 pdata->has_gbit = 1;
 639                 pdata->is_ar724x = 1;
 640
 641                 if (!pdata->fifo_cfg1)
 642                         pdata->fifo_cfg1 = 0x0010ffff;
 643                 if (!pdata->fifo_cfg2)
 644                         pdata->fifo_cfg2 = 0x015500aa;
 645                 if (!pdata->fifo_cfg3)
 646                         pdata->fifo_cfg3 = 0x01f00140;
 647                 break;
 648
 649         case AR71XX_SOC_AR7241:
 650                 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
 651                 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
 652                 /* fall through */
 653         case AR71XX_SOC_AR7240:
 654                 ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY;
 655                 ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY;
 656                 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
 657                                       : ar724x_ddr_flush_ge0;
 658                 pdata->set_pll =  id ? ar724x_set_pll_ge1
 659                                      : ar724x_set_pll_ge0;
 660                 pdata->is_ar724x = 1;
 661                 if (ar71xx_soc == AR71XX_SOC_AR7240)
 662                         pdata->is_ar7240 = 1;
 663
 664                 if (!pdata->fifo_cfg1)
 665                         pdata->fifo_cfg1 = 0x0010ffff;
 666                 if (!pdata->fifo_cfg2)
 667                         pdata->fifo_cfg2 = 0x015500aa;
 668                 if (!pdata->fifo_cfg3)
 669                         pdata->fifo_cfg3 = 0x01f00140;
 670                 break;
 671
 672         case AR71XX_SOC_AR9130:
 673                 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
 674                                       : ar91xx_ddr_flush_ge0;
 675                 pdata->set_pll =  id ? ar91xx_set_pll_ge1
 676                                      : ar91xx_set_pll_ge0;
 677                 pdata->is_ar91xx = 1;
 678                 break;
 679
 680         case AR71XX_SOC_AR9132:
 681                 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
 682                                       : ar91xx_ddr_flush_ge0;
 683                 pdata->set_pll =  id ? ar91xx_set_pll_ge1
 684                                       : ar91xx_set_pll_ge0;
 685                 pdata->is_ar91xx = 1;
 686                 pdata->has_gbit = 1;
 687                 break;
 688
 689         case AR71XX_SOC_AR9330:
 690         case AR71XX_SOC_AR9331:
 691                 ar71xx_eth0_data.reset_bit = AR933X_RESET_GE0_MAC |
 692                                              AR933X_RESET_GE0_MDIO;
 693                 ar71xx_eth1_data.reset_bit = AR933X_RESET_GE1_MAC |
 694                                              AR933X_RESET_GE1_MDIO;
 695                 pdata->ddr_flush = id ? ar933x_ddr_flush_ge1
 696                                       : ar933x_ddr_flush_ge0;
 697                 pdata->set_pll =  id ? ar933x_set_pll_ge1
 698                                      : ar933x_set_pll_ge0;
 699                 pdata->has_gbit = 1;
 700                 pdata->is_ar724x = 1;
 701
 702                 if (!pdata->fifo_cfg1)
 703                         pdata->fifo_cfg1 = 0x0010ffff;
 704                 if (!pdata->fifo_cfg2)
 705                         pdata->fifo_cfg2 = 0x015500aa;
 706                 if (!pdata->fifo_cfg3)
 707                         pdata->fifo_cfg3 = 0x01f00140;
 708                 break;
 709
 710         case AR71XX_SOC_AR9341:
 711         case AR71XX_SOC_AR9342:
 712         case AR71XX_SOC_AR9344:
 713                 ar71xx_eth0_data.reset_bit = AR934X_RESET_GE0_MAC |
 714                                              AR934X_RESET_GE0_MDIO;
 715                 ar71xx_eth1_data.reset_bit = AR934X_RESET_GE1_MAC |
 716                                              AR934X_RESET_GE1_MDIO;
 717                 pdata->ddr_flush = id ? ar934x_ddr_flush_ge1
 718                                       : ar934x_ddr_flush_ge0;
 719                 pdata->set_pll =  id ? ar934x_set_pll_ge1
 720                                      : ar934x_set_pll_ge0;
 721                 pdata->has_gbit = 1;
 722                 pdata->is_ar724x = 1;
 723
 724                 if (!pdata->fifo_cfg1)
 725                         pdata->fifo_cfg1 = 0x0010ffff;
 726                 if (!pdata->fifo_cfg2)
 727                         pdata->fifo_cfg2 = 0x015500aa;
 728                 if (!pdata->fifo_cfg3)
 729                         pdata->fifo_cfg3 = 0x01f00140;
 730                 break;
 731
 732         default:
 733                 BUG();
 734         }
 735
 736         switch (pdata->phy_if_mode) {
 737         case PHY_INTERFACE_MODE_GMII:
 738         case PHY_INTERFACE_MODE_RGMII:
 739                 if (!pdata->has_gbit) {
 740                         printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
 741                                         id);
 742                         return;
 743                 }
 744                 /* fallthrough */
 745         default:
 746                 break;
 747         }
 748
 749         if (!is_valid_ether_addr(pdata->mac_addr)) {
 750                 random_ether_addr(pdata->mac_addr);
 751                 printk(KERN_DEBUG
 752                         "ar71xx: using random MAC address for eth%d\n",
 753                         ar71xx_eth_instance);
 754         }
 755
 756         if (pdata->mii_bus_dev == NULL) {
 757                 switch (ar71xx_soc) {
 758                 case AR71XX_SOC_AR7241:
 759                 case AR71XX_SOC_AR9330:
 760                 case AR71XX_SOC_AR9331:
 761                         pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
 762                         break;
 763
 764                 default:
 765                         pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
 766                         break;
 767                 }
 768         }
 769
 770         /* Reset the device */
 771         ar71xx_device_stop(pdata->reset_bit);
 772         mdelay(100);
 773
 774         ar71xx_device_start(pdata->reset_bit);
 775         mdelay(100);
 776
 777         platform_device_register(pdev);
 778         ar71xx_eth_instance++;
 779 }
 780
 781 static struct resource ar71xx_spi_resources[] = {
 782         [0] = {
 783                 .start  = AR71XX_SPI_BASE,
 784                 .end    = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
 785                 .flags  = IORESOURCE_MEM,
 786         },
 787 };
 788
 789 static struct platform_device ar71xx_spi_device = {
 790         .name           = "ar71xx-spi",
 791         .id             = -1,
 792         .resource       = ar71xx_spi_resources,
 793         .num_resources  = ARRAY_SIZE(ar71xx_spi_resources),
 794 };
 795
 796 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
 797                                 struct spi_board_info const *info,
 798                                 unsigned n)
 799 {
 800         spi_register_board_info(info, n);
 801         ar71xx_spi_device.dev.platform_data = pdata;
 802         platform_device_register(&ar71xx_spi_device);
 803 }
 804
 805 void __init ar71xx_add_device_wdt(void)
 806 {
 807         platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
 808 }
 809
 810 void __init ar71xx_set_mac_base(unsigned char *mac)
 811 {
 812         memcpy(ar71xx_mac_base, mac, ETH_ALEN);
 813 }
 814
 815 void __init ar71xx_parse_mac_addr(char *mac_str)
 816 {
 817         u8 tmp[ETH_ALEN];
 818         int t;
 819
 820         t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
 821                         &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
 822
 823         if (t != ETH_ALEN)
 824                 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
 825                         &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
 826
 827         if (t == ETH_ALEN)
 828                 ar71xx_set_mac_base(tmp);
 829         else
 830                 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
 831                                 "\"%s\"\n", mac_str);
 832 }
 833
 834 static int __init ar71xx_ethaddr_setup(char *str)
 835 {
 836         ar71xx_parse_mac_addr(str);
 837         return 1;
 838 }
 839 __setup("ethaddr=", ar71xx_ethaddr_setup);
 840
 841 static int __init ar71xx_kmac_setup(char *str)
 842 {
 843         ar71xx_parse_mac_addr(str);
 844         return 1;
 845 }
 846 __setup("kmac=", ar71xx_kmac_setup);
 847
 848 void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
 849                             unsigned offset)
 850 {
 851         u32 t;
 852
 853         if (!is_valid_ether_addr(src)) {
 854                 memset(dst, '\0', ETH_ALEN);
 855                 return;
 856         }
 857
 858         t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
 859         t += offset;
 860
 861         dst[0] = src[0];
 862         dst[1] = src[1];
 863         dst[2] = src[2];
 864         dst[3] = (t >> 16) & 0xff;
 865         dst[4] = (t >> 8) & 0xff;
 866         dst[5] = t & 0xff;
 867 }