target/linux/ar71xx/files/arch/mips/ar71xx/devices.c

   1 /*
   2  *  Atheros AR71xx SoC platform devices
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/serial_8250.h>
  22
  23 #include <asm/mach-ar71xx/ar71xx.h>
  24 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
  25
  26 #include "devices.h"
  27
  28 unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
  29
  30 static struct resource ar71xx_uart_resources[] = {
  31         {
  32                 .start  = AR71XX_UART_BASE,
  33                 .end    = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
  34                 .flags  = IORESOURCE_MEM,
  35         },
  36 };
  37
  38 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
  39 static struct plat_serial8250_port ar71xx_uart_data[] = {
  40         {
  41                 .mapbase        = AR71XX_UART_BASE,
  42                 .irq            = AR71XX_MISC_IRQ_UART,
  43                 .flags          = AR71XX_UART_FLAGS,
  44                 .iotype         = UPIO_MEM32,
  45                 .regshift       = 2,
  46         }, {
  47                 /* terminating entry */
  48         }
  49 };
  50
  51 static struct platform_device ar71xx_uart_device = {
  52         .name           = "serial8250",
  53         .id             = PLAT8250_DEV_PLATFORM,
  54         .resource       = ar71xx_uart_resources,
  55         .num_resources  = ARRAY_SIZE(ar71xx_uart_resources),
  56         .dev = {
  57                 .platform_data  = ar71xx_uart_data
  58         },
  59 };
  60
  61 static struct resource ar933x_uart_resources[] = {
  62         {
  63                 .start  = AR933X_UART_BASE,
  64                 .end    = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
  65                 .flags  = IORESOURCE_MEM,
  66         },
  67         {
  68                 .start  = AR71XX_MISC_IRQ_UART,
  69                 .end    = AR71XX_MISC_IRQ_UART,
  70                 .flags  = IORESOURCE_IRQ,
  71         },
  72 };
  73
  74 static struct ar933x_uart_platform_data ar933x_uart_data;
  75 static struct platform_device ar933x_uart_device = {
  76         .name           = "ar933x-uart",
  77         .id             = -1,
  78         .resource       = ar933x_uart_resources,
  79         .num_resources  = ARRAY_SIZE(ar933x_uart_resources),
  80         .dev = {
  81                 .platform_data  = &ar933x_uart_data,
  82         },
  83 };
  84
  85 void __init ar71xx_add_device_uart(void)
  86 {
  87         struct platform_device *pdev;
  88
  89         switch (ar71xx_soc) {
  90         case AR71XX_SOC_AR7130:
  91         case AR71XX_SOC_AR7141:
  92         case AR71XX_SOC_AR7161:
  93         case AR71XX_SOC_AR7240:
  94         case AR71XX_SOC_AR7241:
  95         case AR71XX_SOC_AR7242:
  96         case AR71XX_SOC_AR9130:
  97         case AR71XX_SOC_AR9132:
  98                 pdev = &ar71xx_uart_device;
  99                 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
 100                 break;
 101
 102         case AR71XX_SOC_AR9330:
 103         case AR71XX_SOC_AR9331:
 104                 pdev = &ar933x_uart_device;
 105                 ar933x_uart_data.uartclk = ar71xx_ref_freq;
 106                 break;
 107
 108         case AR71XX_SOC_AR9341:
 109         case AR71XX_SOC_AR9342:
 110         case AR71XX_SOC_AR9344:
 111                 pdev = &ar71xx_uart_device;
 112                 ar71xx_uart_data[0].uartclk = ar71xx_ref_freq;
 113                 break;
 114
 115         default:
 116                 BUG();
 117         }
 118
 119         platform_device_register(pdev);
 120 }
 121
 122 static struct resource ar71xx_mdio0_resources[] = {
 123         {
 124                 .name   = "mdio_base",
 125                 .flags  = IORESOURCE_MEM,
 126                 .start  = AR71XX_GE0_BASE,
 127                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
 128         }
 129 };
 130
 131 static struct ag71xx_mdio_platform_data ar71xx_mdio0_data;
 132
 133 struct platform_device ar71xx_mdio0_device = {
 134         .name           = "ag71xx-mdio",
 135         .id             = 0,
 136         .resource       = ar71xx_mdio0_resources,
 137         .num_resources  = ARRAY_SIZE(ar71xx_mdio0_resources),
 138         .dev = {
 139                 .platform_data = &ar71xx_mdio0_data,
 140         },
 141 };
 142
 143 static struct resource ar71xx_mdio1_resources[] = {
 144         {
 145                 .name   = "mdio_base",
 146                 .flags  = IORESOURCE_MEM,
 147                 .start  = AR71XX_GE1_BASE,
 148                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
 149         }
 150 };
 151
 152 static struct ag71xx_mdio_platform_data ar71xx_mdio1_data;
 153
 154 struct platform_device ar71xx_mdio1_device = {
 155         .name           = "ag71xx-mdio",
 156         .id             = 1,
 157         .resource       = ar71xx_mdio1_resources,
 158         .num_resources  = ARRAY_SIZE(ar71xx_mdio1_resources),
 159         .dev = {
 160                 .platform_data = &ar71xx_mdio1_data,
 161         },
 162 };
 163
 164 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
 165 {
 166         void __iomem *base;
 167         u32 t;
 168
 169         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 170
 171         t = __raw_readl(base + cfg_reg);
 172         t &= ~(3 << shift);
 173         t |=  (2 << shift);
 174         __raw_writel(t, base + cfg_reg);
 175         udelay(100);
 176
 177         __raw_writel(pll_val, base + pll_reg);
 178
 179         t |= (3 << shift);
 180         __raw_writel(t, base + cfg_reg);
 181         udelay(100);
 182
 183         t &= ~(3 << shift);
 184         __raw_writel(t, base + cfg_reg);
 185         udelay(100);
 186
 187         printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
 188                 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
 189
 190         iounmap(base);
 191 }
 192
 193 static void __init ar71xx_mii_ctrl_set_if(unsigned int reg,
 194                                           unsigned int mii_if)
 195 {
 196         void __iomem *base;
 197         u32 t;
 198
 199         base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
 200
 201         t = __raw_readl(base + reg);
 202         t &= ~(MII_CTRL_IF_MASK);
 203         t |= (mii_if & MII_CTRL_IF_MASK);
 204         __raw_writel(t, base + reg);
 205
 206         iounmap(base);
 207 }
 208
 209 static void ar71xx_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
 210 {
 211         void __iomem *base;
 212         unsigned int mii_speed;
 213         u32 t;
 214
 215         switch (speed) {
 216         case SPEED_10:
 217                 mii_speed =  MII_CTRL_SPEED_10;
 218                 break;
 219         case SPEED_100:
 220                 mii_speed =  MII_CTRL_SPEED_100;
 221                 break;
 222         case SPEED_1000:
 223                 mii_speed =  MII_CTRL_SPEED_1000;
 224                 break;
 225         default:
 226                 BUG();
 227         }
 228
 229         base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
 230
 231         t = __raw_readl(base + reg);
 232         t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
 233         t |= mii_speed  << MII_CTRL_SPEED_SHIFT;
 234         __raw_writel(t, base + reg);
 235
 236         iounmap(base);
 237 }
 238
 239 void __init ar71xx_add_device_mdio(unsigned int id, u32 phy_mask)
 240 {
 241         struct platform_device *mdio_dev;
 242         struct ag71xx_mdio_platform_data *mdio_data;
 243         unsigned int max_id;
 244
 245         if (ar71xx_soc == AR71XX_SOC_AR9341 ||
 246             ar71xx_soc == AR71XX_SOC_AR9342 ||
 247             ar71xx_soc == AR71XX_SOC_AR9344)
 248                 max_id = 1;
 249         else
 250                 max_id = 0;
 251
 252         if (id > max_id) {
 253                 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
 254                 return;
 255         }
 256
 257         switch (ar71xx_soc) {
 258         case AR71XX_SOC_AR7241:
 259         case AR71XX_SOC_AR9330:
 260         case AR71XX_SOC_AR9331:
 261                 mdio_dev = &ar71xx_mdio1_device;
 262                 mdio_data = &ar71xx_mdio1_data;
 263                 break;
 264
 265         case AR71XX_SOC_AR9341:
 266         case AR71XX_SOC_AR9342:
 267         case AR71XX_SOC_AR9344:
 268                 if (id == 0) {
 269                         mdio_dev = &ar71xx_mdio0_device;
 270                         mdio_data = &ar71xx_mdio0_data;
 271                 } else {
 272                         mdio_dev = &ar71xx_mdio1_device;
 273                         mdio_data = &ar71xx_mdio1_data;
 274                 }
 275                 break;
 276
 277         case AR71XX_SOC_AR7242:
 278                 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
 279                                AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
 280                                AR71XX_ETH0_PLL_SHIFT);
 281                 /* fall through */
 282         default:
 283                 mdio_dev = &ar71xx_mdio0_device;
 284                 mdio_data = &ar71xx_mdio0_data;
 285                 break;
 286         }
 287
 288         mdio_data->phy_mask = phy_mask;
 289
 290         switch (ar71xx_soc) {
 291         case AR71XX_SOC_AR7240:
 292         case AR71XX_SOC_AR7241:
 293         case AR71XX_SOC_AR9330:
 294         case AR71XX_SOC_AR9331:
 295                 mdio_data->is_ar7240 = 1;
 296                 break;
 297
 298         case AR71XX_SOC_AR9341:
 299         case AR71XX_SOC_AR9342:
 300         case AR71XX_SOC_AR9344:
 301                 if (id == 1)
 302                         mdio_data->is_ar7240 = 1;
 303                 break;
 304
 305         default:
 306                 break;
 307         }
 308
 309         platform_device_register(mdio_dev);
 310 }
 311
 312 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
 313 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
 314
 315 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
 316 {
 317         struct ar71xx_eth_pll_data *pll_data;
 318         u32 pll_val;
 319
 320         switch (mac) {
 321         case 0:
 322                 pll_data = &ar71xx_eth0_pll_data;
 323                 break;
 324         case 1:
 325                 pll_data = &ar71xx_eth1_pll_data;
 326                 break;
 327         default:
 328                 BUG();
 329         }
 330
 331         switch (speed) {
 332         case SPEED_10:
 333                 pll_val = pll_data->pll_10;
 334                 break;
 335         case SPEED_100:
 336                 pll_val = pll_data->pll_100;
 337                 break;
 338         case SPEED_1000:
 339                 pll_val = pll_data->pll_1000;
 340                 break;
 341         default:
 342                 BUG();
 343         }
 344
 345         return pll_val;
 346 }
 347
 348 static void ar71xx_set_speed_ge0(int speed)
 349 {
 350         u32 val = ar71xx_get_eth_pll(0, speed);
 351
 352         ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
 353                         val, AR71XX_ETH0_PLL_SHIFT);
 354         ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
 355 }
 356
 357 static void ar71xx_set_speed_ge1(int speed)
 358 {
 359         u32 val = ar71xx_get_eth_pll(1, speed);
 360
 361         ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
 362                          val, AR71XX_ETH1_PLL_SHIFT);
 363         ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
 364 }
 365
 366 static void ar724x_set_speed_ge0(int speed)
 367 {
 368         /* TODO */
 369 }
 370
 371 static void ar724x_set_speed_ge1(int speed)
 372 {
 373         /* TODO */
 374 }
 375
 376 static void ar7242_set_speed_ge0(int speed)
 377 {
 378         u32 val = ar71xx_get_eth_pll(0, speed);
 379         void __iomem *base;
 380
 381         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 382         __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
 383         iounmap(base);
 384 }
 385
 386 static void ar91xx_set_speed_ge0(int speed)
 387 {
 388         u32 val = ar71xx_get_eth_pll(0, speed);
 389
 390         ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
 391                          val, AR91XX_ETH0_PLL_SHIFT);
 392         ar71xx_mii_ctrl_set_speed(MII_REG_MII0_CTRL, speed);
 393 }
 394
 395 static void ar91xx_set_speed_ge1(int speed)
 396 {
 397         u32 val = ar71xx_get_eth_pll(1, speed);
 398
 399         ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
 400                          val, AR91XX_ETH1_PLL_SHIFT);
 401         ar71xx_mii_ctrl_set_speed(MII_REG_MII1_CTRL, speed);
 402 }
 403
 404 static void ar933x_set_speed_ge0(int speed)
 405 {
 406         /* TODO */
 407 }
 408
 409 static void ar933x_set_speed_ge1(int speed)
 410 {
 411         /* TODO */
 412 }
 413
 414 static void ar934x_set_speed_ge0(int speed)
 415 {
 416         /* TODO */
 417 }
 418
 419 static void ar934x_set_speed_ge1(int speed)
 420 {
 421         /* TODO */
 422 }
 423
 424 static void ar71xx_ddr_flush_ge0(void)
 425 {
 426         ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
 427 }
 428
 429 static void ar71xx_ddr_flush_ge1(void)
 430 {
 431         ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
 432 }
 433
 434 static void ar724x_ddr_flush_ge0(void)
 435 {
 436         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
 437 }
 438
 439 static void ar724x_ddr_flush_ge1(void)
 440 {
 441         ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
 442 }
 443
 444 static void ar91xx_ddr_flush_ge0(void)
 445 {
 446         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
 447 }
 448
 449 static void ar91xx_ddr_flush_ge1(void)
 450 {
 451         ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
 452 }
 453
 454 static void ar933x_ddr_flush_ge0(void)
 455 {
 456         ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
 457 }
 458
 459 static void ar933x_ddr_flush_ge1(void)
 460 {
 461         ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
 462 }
 463
 464 static void ar934x_ddr_flush_ge0(void)
 465 {
 466         ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
 467 }
 468
 469 static void ar934x_ddr_flush_ge1(void)
 470 {
 471         ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
 472 }
 473
 474 static struct resource ar71xx_eth0_resources[] = {
 475         {
 476                 .name   = "mac_base",
 477                 .flags  = IORESOURCE_MEM,
 478                 .start  = AR71XX_GE0_BASE,
 479                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
 480         }, {
 481                 .name   = "mac_irq",
 482                 .flags  = IORESOURCE_IRQ,
 483                 .start  = AR71XX_CPU_IRQ_GE0,
 484                 .end    = AR71XX_CPU_IRQ_GE0,
 485         },
 486 };
 487
 488 struct ag71xx_platform_data ar71xx_eth0_data = {
 489         .reset_bit      = RESET_MODULE_GE0_MAC,
 490 };
 491
 492 struct platform_device ar71xx_eth0_device = {
 493         .name           = "ag71xx",
 494         .id             = 0,
 495         .resource       = ar71xx_eth0_resources,
 496         .num_resources  = ARRAY_SIZE(ar71xx_eth0_resources),
 497         .dev = {
 498                 .platform_data = &ar71xx_eth0_data,
 499         },
 500 };
 501
 502 static struct resource ar71xx_eth1_resources[] = {
 503         {
 504                 .name   = "mac_base",
 505                 .flags  = IORESOURCE_MEM,
 506                 .start  = AR71XX_GE1_BASE,
 507                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
 508         }, {
 509                 .name   = "mac_irq",
 510                 .flags  = IORESOURCE_IRQ,
 511                 .start  = AR71XX_CPU_IRQ_GE1,
 512                 .end    = AR71XX_CPU_IRQ_GE1,
 513         },
 514 };
 515
 516 struct ag71xx_platform_data ar71xx_eth1_data = {
 517         .reset_bit      = RESET_MODULE_GE1_MAC,
 518 };
 519
 520 struct platform_device ar71xx_eth1_device = {
 521         .name           = "ag71xx",
 522         .id             = 1,
 523         .resource       = ar71xx_eth1_resources,
 524         .num_resources  = ARRAY_SIZE(ar71xx_eth1_resources),
 525         .dev = {
 526                 .platform_data = &ar71xx_eth1_data,
 527         },
 528 };
 529
 530 #define AR71XX_PLL_VAL_1000     0x00110000
 531 #define AR71XX_PLL_VAL_100      0x00001099
 532 #define AR71XX_PLL_VAL_10       0x00991099
 533
 534 #define AR724X_PLL_VAL_1000     0x00110000
 535 #define AR724X_PLL_VAL_100      0x00001099
 536 #define AR724X_PLL_VAL_10       0x00991099
 537
 538 #define AR7242_PLL_VAL_1000     0x16000000
 539 #define AR7242_PLL_VAL_100      0x00000101
 540 #define AR7242_PLL_VAL_10       0x00001616
 541
 542 #define AR91XX_PLL_VAL_1000     0x1a000000
 543 #define AR91XX_PLL_VAL_100      0x13000a44
 544 #define AR91XX_PLL_VAL_10       0x00441099
 545
 546 #define AR933X_PLL_VAL_1000     0x00110000
 547 #define AR933X_PLL_VAL_100      0x00001099
 548 #define AR933X_PLL_VAL_10       0x00991099
 549
 550 #define AR934X_PLL_VAL_1000     0x00110000
 551 #define AR934X_PLL_VAL_100      0x00001099
 552 #define AR934X_PLL_VAL_10       0x00991099
 553
 554 static void __init ar71xx_init_eth_pll_data(unsigned int id)
 555 {
 556         struct ar71xx_eth_pll_data *pll_data;
 557         u32 pll_10, pll_100, pll_1000;
 558
 559         switch (id) {
 560         case 0:
 561                 pll_data = &ar71xx_eth0_pll_data;
 562                 break;
 563         case 1:
 564                 pll_data = &ar71xx_eth1_pll_data;
 565                 break;
 566         default:
 567                 BUG();
 568         }
 569
 570         switch (ar71xx_soc) {
 571         case AR71XX_SOC_AR7130:
 572         case AR71XX_SOC_AR7141:
 573         case AR71XX_SOC_AR7161:
 574                 pll_10 = AR71XX_PLL_VAL_10;
 575                 pll_100 = AR71XX_PLL_VAL_100;
 576                 pll_1000 = AR71XX_PLL_VAL_1000;
 577                 break;
 578
 579         case AR71XX_SOC_AR7240:
 580         case AR71XX_SOC_AR7241:
 581                 pll_10 = AR724X_PLL_VAL_10;
 582                 pll_100 = AR724X_PLL_VAL_100;
 583                 pll_1000 = AR724X_PLL_VAL_1000;
 584                 break;
 585
 586         case AR71XX_SOC_AR7242:
 587                 pll_10 = AR7242_PLL_VAL_10;
 588                 pll_100 = AR7242_PLL_VAL_100;
 589                 pll_1000 = AR7242_PLL_VAL_1000;
 590                 break;
 591
 592         case AR71XX_SOC_AR9130:
 593         case AR71XX_SOC_AR9132:
 594                 pll_10 = AR91XX_PLL_VAL_10;
 595                 pll_100 = AR91XX_PLL_VAL_100;
 596                 pll_1000 = AR91XX_PLL_VAL_1000;
 597                 break;
 598
 599         case AR71XX_SOC_AR9330:
 600         case AR71XX_SOC_AR9331:
 601                 pll_10 = AR933X_PLL_VAL_10;
 602                 pll_100 = AR933X_PLL_VAL_100;
 603                 pll_1000 = AR933X_PLL_VAL_1000;
 604                 break;
 605
 606         case AR71XX_SOC_AR9341:
 607         case AR71XX_SOC_AR9342:
 608         case AR71XX_SOC_AR9344:
 609                 pll_10 = AR934X_PLL_VAL_10;
 610                 pll_100 = AR934X_PLL_VAL_100;
 611                 pll_1000 = AR934X_PLL_VAL_1000;
 612                 break;
 613
 614         default:
 615                 BUG();
 616         }
 617
 618         if (!pll_data->pll_10)
 619                 pll_data->pll_10 = pll_10;
 620
 621         if (!pll_data->pll_100)
 622                 pll_data->pll_100 = pll_100;
 623
 624         if (!pll_data->pll_1000)
 625                 pll_data->pll_1000 = pll_1000;
 626 }
 627
 628 static int __init ar71xx_setup_phy_if_mode(unsigned int id,
 629                                            struct ag71xx_platform_data *pdata)
 630 {
 631         unsigned int mii_if;
 632
 633         switch (id) {
 634         case 0:
 635                 switch (ar71xx_soc) {
 636                 case AR71XX_SOC_AR7130:
 637                 case AR71XX_SOC_AR7141:
 638                 case AR71XX_SOC_AR7161:
 639                 case AR71XX_SOC_AR9130:
 640                 case AR71XX_SOC_AR9132:
 641                         switch (pdata->phy_if_mode) {
 642                         case PHY_INTERFACE_MODE_MII:
 643                                 mii_if = MII0_CTRL_IF_MII;
 644                                 break;
 645                         case PHY_INTERFACE_MODE_GMII:
 646                                 mii_if = MII0_CTRL_IF_GMII;
 647                                 break;
 648                         case PHY_INTERFACE_MODE_RGMII:
 649                                 mii_if = MII0_CTRL_IF_RGMII;
 650                                 break;
 651                         case PHY_INTERFACE_MODE_RMII:
 652                                 mii_if = MII0_CTRL_IF_RMII;
 653                                 break;
 654                         default:
 655                                 return -EINVAL;
 656                         }
 657                         ar71xx_mii_ctrl_set_if(MII_REG_MII0_CTRL, mii_if);
 658                         break;
 659
 660                 case AR71XX_SOC_AR7240:
 661                 case AR71XX_SOC_AR7241:
 662                 case AR71XX_SOC_AR9330:
 663                 case AR71XX_SOC_AR9331:
 664                         pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
 665                         break;
 666
 667                 case AR71XX_SOC_AR7242:
 668                         /* FIXME */
 669
 670                 case AR71XX_SOC_AR9341:
 671                 case AR71XX_SOC_AR9342:
 672                 case AR71XX_SOC_AR9344:
 673                         switch (pdata->phy_if_mode) {
 674                         case PHY_INTERFACE_MODE_MII:
 675                         case PHY_INTERFACE_MODE_GMII:
 676                         case PHY_INTERFACE_MODE_RGMII:
 677                         case PHY_INTERFACE_MODE_RMII:
 678                                 break;
 679                         default:
 680                                 return -EINVAL;
 681                         }
 682                         break;
 683
 684                 default:
 685                         BUG();
 686                 }
 687                 break;
 688         case 1:
 689                 switch (ar71xx_soc) {
 690                 case AR71XX_SOC_AR7130:
 691                 case AR71XX_SOC_AR7141:
 692                 case AR71XX_SOC_AR7161:
 693                 case AR71XX_SOC_AR9130:
 694                 case AR71XX_SOC_AR9132:
 695                         switch (pdata->phy_if_mode) {
 696                         case PHY_INTERFACE_MODE_RMII:
 697                                 mii_if = MII1_CTRL_IF_RMII;
 698                                 break;
 699                         case PHY_INTERFACE_MODE_RGMII:
 700                                 mii_if = MII1_CTRL_IF_RGMII;
 701                                 break;
 702                         default:
 703                                 return -EINVAL;
 704                         }
 705                         ar71xx_mii_ctrl_set_if(MII_REG_MII1_CTRL, mii_if);
 706                         break;
 707
 708                 case AR71XX_SOC_AR7240:
 709                 case AR71XX_SOC_AR7241:
 710                 case AR71XX_SOC_AR9330:
 711                 case AR71XX_SOC_AR9331:
 712                         pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
 713                         break;
 714
 715                 case AR71XX_SOC_AR7242:
 716                         /* FIXME */
 717
 718                 case AR71XX_SOC_AR9341:
 719                 case AR71XX_SOC_AR9342:
 720                 case AR71XX_SOC_AR9344:
 721                         switch (pdata->phy_if_mode) {
 722                         case PHY_INTERFACE_MODE_MII:
 723                         case PHY_INTERFACE_MODE_GMII:
 724                                 break;
 725                         default:
 726                                 return -EINVAL;
 727                         }
 728                         break;
 729
 730                 default:
 731                         BUG();
 732                 }
 733                 break;
 734         }
 735
 736         return 0;
 737 }
 738
 739 static int ar71xx_eth_instance __initdata;
 740 void __init ar71xx_add_device_eth(unsigned int id)
 741 {
 742         struct platform_device *pdev;
 743         struct ag71xx_platform_data *pdata;
 744         int err;
 745
 746         if (id > 1) {
 747                 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
 748                 return;
 749         }
 750
 751         ar71xx_init_eth_pll_data(id);
 752
 753         if (id == 0)
 754                 pdev = &ar71xx_eth0_device;
 755         else
 756                 pdev = &ar71xx_eth1_device;
 757
 758         pdata = pdev->dev.platform_data;
 759
 760         err = ar71xx_setup_phy_if_mode(id, pdata);
 761         if (err) {
 762                 printk(KERN_ERR
 763                        "ar71xx: invalid PHY interface mode for GE%u\n", id);
 764                 return;
 765         }
 766
 767         switch (ar71xx_soc) {
 768         case AR71XX_SOC_AR7130:
 769                 if (id == 0) {
 770                         pdata->ddr_flush = ar71xx_ddr_flush_ge0;
 771                         pdata->set_speed = ar71xx_set_speed_ge0;
 772                 } else {
 773                         pdata->ddr_flush = ar71xx_ddr_flush_ge1;
 774                         pdata->set_speed = ar71xx_set_speed_ge1;
 775                 }
 776                 break;
 777
 778         case AR71XX_SOC_AR7141:
 779         case AR71XX_SOC_AR7161:
 780                 if (id == 0) {
 781                         pdata->ddr_flush = ar71xx_ddr_flush_ge0;
 782                         pdata->set_speed = ar71xx_set_speed_ge0;
 783                 } else {
 784                         pdata->ddr_flush = ar71xx_ddr_flush_ge1;
 785                         pdata->set_speed = ar71xx_set_speed_ge1;
 786                 }
 787                 pdata->has_gbit = 1;
 788                 break;
 789
 790         case AR71XX_SOC_AR7242:
 791                 if (id == 0) {
 792                         pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
 793                                             RESET_MODULE_GE0_PHY;
 794                         pdata->ddr_flush = ar724x_ddr_flush_ge0;
 795                         pdata->set_speed = ar7242_set_speed_ge0;
 796                 } else {
 797                         pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
 798                                             RESET_MODULE_GE1_PHY;
 799                         pdata->ddr_flush = ar724x_ddr_flush_ge1;
 800                         pdata->set_speed = ar724x_set_speed_ge1;
 801                 }
 802                 pdata->has_gbit = 1;
 803                 pdata->is_ar724x = 1;
 804
 805                 if (!pdata->fifo_cfg1)
 806                         pdata->fifo_cfg1 = 0x0010ffff;
 807                 if (!pdata->fifo_cfg2)
 808                         pdata->fifo_cfg2 = 0x015500aa;
 809                 if (!pdata->fifo_cfg3)
 810                         pdata->fifo_cfg3 = 0x01f00140;
 811                 break;
 812
 813         case AR71XX_SOC_AR7241:
 814                 if (id == 0)
 815                         pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
 816                 else
 817                         pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
 818                 /* fall through */
 819         case AR71XX_SOC_AR7240:
 820                 if (id == 0) {
 821                         pdata->reset_bit |= RESET_MODULE_GE0_PHY;
 822                         pdata->ddr_flush = ar724x_ddr_flush_ge0;
 823                         pdata->set_speed = ar724x_set_speed_ge0;
 824
 825                         pdata->phy_mask = BIT(4);
 826                 } else {
 827                         pdata->reset_bit |= RESET_MODULE_GE1_PHY;
 828                         pdata->ddr_flush = ar724x_ddr_flush_ge1;
 829                         pdata->set_speed = ar724x_set_speed_ge1;
 830
 831                         pdata->speed = SPEED_1000;
 832                         pdata->duplex = DUPLEX_FULL;
 833                         pdata->has_ar7240_switch = 1;
 834                 }
 835                 pdata->has_gbit = 1;
 836                 pdata->is_ar724x = 1;
 837                 if (ar71xx_soc == AR71XX_SOC_AR7240)
 838                         pdata->is_ar7240 = 1;
 839
 840                 if (!pdata->fifo_cfg1)
 841                         pdata->fifo_cfg1 = 0x0010ffff;
 842                 if (!pdata->fifo_cfg2)
 843                         pdata->fifo_cfg2 = 0x015500aa;
 844                 if (!pdata->fifo_cfg3)
 845                         pdata->fifo_cfg3 = 0x01f00140;
 846                 break;
 847
 848         case AR71XX_SOC_AR9130:
 849                 if (id == 0) {
 850                         pdata->ddr_flush = ar91xx_ddr_flush_ge0;
 851                         pdata->set_speed = ar91xx_set_speed_ge0;
 852                 } else {
 853                         pdata->ddr_flush = ar91xx_ddr_flush_ge1;
 854                         pdata->set_speed = ar91xx_set_speed_ge1;
 855                 }
 856                 pdata->is_ar91xx = 1;
 857                 break;
 858
 859         case AR71XX_SOC_AR9132:
 860                 if (id == 0) {
 861                         pdata->ddr_flush = ar91xx_ddr_flush_ge0;
 862                         pdata->set_speed = ar91xx_set_speed_ge0;
 863                 } else {
 864                         pdata->ddr_flush = ar91xx_ddr_flush_ge1;
 865                         pdata->set_speed = ar91xx_set_speed_ge1;
 866                 }
 867                 pdata->is_ar91xx = 1;
 868                 pdata->has_gbit = 1;
 869                 break;
 870
 871         case AR71XX_SOC_AR9330:
 872         case AR71XX_SOC_AR9331:
 873                 if (id == 0) {
 874                         pdata->reset_bit = AR933X_RESET_GE0_MAC |
 875                                            AR933X_RESET_GE0_MDIO;
 876                         pdata->ddr_flush = ar933x_ddr_flush_ge0;
 877                         pdata->set_speed = ar933x_set_speed_ge0;
 878
 879                         pdata->phy_mask = BIT(4);
 880                 } else {
 881                         pdata->reset_bit = AR933X_RESET_GE1_MAC |
 882                                            AR933X_RESET_GE1_MDIO;
 883                         pdata->ddr_flush = ar933x_ddr_flush_ge1;
 884                         pdata->set_speed = ar933x_set_speed_ge1;
 885
 886                         pdata->speed = SPEED_1000;
 887                         pdata->duplex = DUPLEX_FULL;
 888                         pdata->has_ar7240_switch = 1;
 889                 }
 890
 891                 pdata->has_gbit = 1;
 892                 pdata->is_ar724x = 1;
 893
 894                 if (!pdata->fifo_cfg1)
 895                         pdata->fifo_cfg1 = 0x0010ffff;
 896                 if (!pdata->fifo_cfg2)
 897                         pdata->fifo_cfg2 = 0x015500aa;
 898                 if (!pdata->fifo_cfg3)
 899                         pdata->fifo_cfg3 = 0x01f00140;
 900                 break;
 901
 902         case AR71XX_SOC_AR9341:
 903         case AR71XX_SOC_AR9342:
 904         case AR71XX_SOC_AR9344:
 905                 if (id == 0) {
 906                         pdata->reset_bit = AR934X_RESET_GE0_MAC |
 907                                            AR934X_RESET_GE0_MDIO;
 908                         pdata->ddr_flush =ar934x_ddr_flush_ge0;
 909                         pdata->set_speed = ar934x_set_speed_ge0;
 910                 } else {
 911                         pdata->reset_bit = AR934X_RESET_GE1_MAC |
 912                                            AR934X_RESET_GE1_MDIO;
 913                         pdata->ddr_flush = ar934x_ddr_flush_ge1;
 914                         pdata->set_speed = ar934x_set_speed_ge1;
 915                 }
 916
 917                 pdata->has_gbit = 1;
 918                 pdata->is_ar724x = 1;
 919
 920                 if (!pdata->fifo_cfg1)
 921                         pdata->fifo_cfg1 = 0x0010ffff;
 922                 if (!pdata->fifo_cfg2)
 923                         pdata->fifo_cfg2 = 0x015500aa;
 924                 if (!pdata->fifo_cfg3)
 925                         pdata->fifo_cfg3 = 0x01f00140;
 926                 break;
 927
 928         default:
 929                 BUG();
 930         }
 931
 932         switch (pdata->phy_if_mode) {
 933         case PHY_INTERFACE_MODE_GMII:
 934         case PHY_INTERFACE_MODE_RGMII:
 935                 if (!pdata->has_gbit) {
 936                         printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
 937                                         id);
 938                         return;
 939                 }
 940                 /* fallthrough */
 941         default:
 942                 break;
 943         }
 944
 945         if (!is_valid_ether_addr(pdata->mac_addr)) {
 946                 random_ether_addr(pdata->mac_addr);
 947                 printk(KERN_DEBUG
 948                         "ar71xx: using random MAC address for eth%d\n",
 949                         ar71xx_eth_instance);
 950         }
 951
 952         if (pdata->mii_bus_dev == NULL) {
 953                 switch (ar71xx_soc) {
 954                 case AR71XX_SOC_AR9341:
 955                 case AR71XX_SOC_AR9342:
 956                 case AR71XX_SOC_AR9344:
 957                         if (id == 0)
 958                                 pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
 959                         else
 960                                 pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
 961                         break;
 962
 963                 case AR71XX_SOC_AR7241:
 964                 case AR71XX_SOC_AR9330:
 965                 case AR71XX_SOC_AR9331:
 966                         pdata->mii_bus_dev = &ar71xx_mdio1_device.dev;
 967                         break;
 968
 969                 default:
 970                         pdata->mii_bus_dev = &ar71xx_mdio0_device.dev;
 971                         break;
 972                 }
 973         }
 974
 975         /* Reset the device */
 976         ar71xx_device_stop(pdata->reset_bit);
 977         mdelay(100);
 978
 979         ar71xx_device_start(pdata->reset_bit);
 980         mdelay(100);
 981
 982         platform_device_register(pdev);
 983         ar71xx_eth_instance++;
 984 }
 985
 986 static struct resource ar71xx_spi_resources[] = {
 987         [0] = {
 988                 .start  = AR71XX_SPI_BASE,
 989                 .end    = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
 990                 .flags  = IORESOURCE_MEM,
 991         },
 992 };
 993
 994 static struct platform_device ar71xx_spi_device = {
 995         .name           = "ar71xx-spi",
 996         .id             = -1,
 997         .resource       = ar71xx_spi_resources,
 998         .num_resources  = ARRAY_SIZE(ar71xx_spi_resources),
 999 };
1000
1001 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
1002                                 struct spi_board_info const *info,
1003                                 unsigned n)
1004 {
1005         spi_register_board_info(info, n);
1006         ar71xx_spi_device.dev.platform_data = pdata;
1007         platform_device_register(&ar71xx_spi_device);
1008 }
1009
1010 void __init ar71xx_add_device_wdt(void)
1011 {
1012         platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
1013 }
1014
1015 void __init ar71xx_set_mac_base(unsigned char *mac)
1016 {
1017         memcpy(ar71xx_mac_base, mac, ETH_ALEN);
1018 }
1019
1020 void __init ar71xx_parse_mac_addr(char *mac_str)
1021 {
1022         u8 tmp[ETH_ALEN];
1023         int t;
1024
1025         t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1026                         &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1027
1028         if (t != ETH_ALEN)
1029                 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1030                         &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1031
1032         if (t == ETH_ALEN)
1033                 ar71xx_set_mac_base(tmp);
1034         else
1035                 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
1036                                 "\"%s\"\n", mac_str);
1037 }
1038
1039 static int __init ar71xx_ethaddr_setup(char *str)
1040 {
1041         ar71xx_parse_mac_addr(str);
1042         return 1;
1043 }
1044 __setup("ethaddr=", ar71xx_ethaddr_setup);
1045
1046 static int __init ar71xx_kmac_setup(char *str)
1047 {
1048         ar71xx_parse_mac_addr(str);
1049         return 1;
1050 }
1051 __setup("kmac=", ar71xx_kmac_setup);
1052
1053 void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
1054                             unsigned offset)
1055 {
1056         u32 t;
1057
1058         if (!is_valid_ether_addr(src)) {
1059                 memset(dst, '\0', ETH_ALEN);
1060                 return;
1061         }
1062
1063         t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1064         t += offset;
1065
1066         dst[0] = src[0];
1067         dst[1] = src[1];
1068         dst[2] = src[2];
1069         dst[3] = (t >> 16) & 0xff;
1070         dst[4] = (t >> 8) & 0xff;
1071         dst[5] = t & 0xff;
1072 }