2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ahcd fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
18 * This file is licenced under the GPL.
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
41 #include <asm/system.h>
42 #include <asm/unaligned.h>
43 #include <asm/byteorder.h>
45 #include "../core/hcd.h"
46 #include "../core/hub.h"
48 #define DRIVER_VERSION "v0.10.1"
49 #define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
50 #define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
52 /*-------------------------------------------------------------------------*/
54 #undef ADMHC_VERBOSE_DEBUG /* not always helpful */
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
59 #define ADMHC_INTR_INIT \
60 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
61 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
63 /*-------------------------------------------------------------------------*/
65 static const char hcd_name [] = "admhc-hcd";
67 #define STATECHANGE_DELAY msecs_to_jiffies(300)
71 static void admhc_dump(struct admhcd *ahcd, int verbose);
72 static int admhc_init(struct admhcd *ahcd);
73 static void admhc_stop(struct usb_hcd *hcd);
75 #include "adm5120-dbg.c"
76 #include "adm5120-mem.c"
77 #include "adm5120-pm.c"
78 #include "adm5120-hub.c"
79 #include "adm5120-q.c"
81 /*-------------------------------------------------------------------------*/
84 * queue up an urb for anything except the root hub
86 static int admhc_urb_enqueue(struct usb_hcd *hcd, struct usb_host_endpoint *ep,
87 struct urb *urb, gfp_t mem_flags)
89 struct admhcd *ahcd = hcd_to_admhcd(hcd);
91 struct urb_priv *urb_priv;
92 unsigned int pipe = urb->pipe;
97 #ifdef ADMHC_VERBOSE_DEBUG
98 spin_lock_irqsave(&ahcd->lock, flags);
99 urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe));
100 spin_unlock_irqrestore(&ahcd->lock, flags);
103 /* every endpoint has an ed, locate and maybe (re)initialize it */
104 ed = ed_get(ahcd, ep, urb->dev, pipe, urb->interval);
108 /* for the private part of the URB we need the number of TDs */
111 if (urb->transfer_buffer_length > TD_DATALEN_MAX)
112 /* td_submit_urb() doesn't yet handle these */
115 /* 1 TD for setup, 1 for ACK, plus ... */
119 /* one TD for every 4096 Bytes (can be upto 8K) */
120 td_cnt += urb->transfer_buffer_length / TD_DATALEN_MAX;
121 /* ... and for any remaining bytes ... */
122 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
124 /* ... and maybe a zero length packet to wrap it up */
127 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
128 && (urb->transfer_buffer_length
129 % usb_maxpacket(urb->dev, pipe,
130 usb_pipeout (pipe))) == 0)
135 * for Interrupt IN/OUT transactions, each ED contains
137 * TODO: check transfer_buffer_length?
141 case PIPE_ISOCHRONOUS:
142 /* number of packets from URB */
143 td_cnt = urb->number_of_packets;
147 admhc_err(ahcd, "bad EP type %d", ed->type);
151 urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
157 spin_lock_irqsave(&ahcd->lock, flags);
158 /* don't submit to a dead HC */
159 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
163 if (!HC_IS_RUNNING(hcd->state)) {
168 /* in case of unlink-during-submit */
169 spin_lock(&urb->lock);
170 if (urb->status != -EINPROGRESS) {
171 spin_unlock(&urb->lock);
172 urb->hcpriv = urb_priv;
173 finish_urb(ahcd, urb);
178 /* schedule the ed if needed */
179 if (ed->state == ED_IDLE) {
180 ret = ed_schedule(ahcd, ed);
184 if (ed->type == PIPE_ISOCHRONOUS) {
185 u16 frame = admhc_frame_no(ahcd);
187 /* delay a few frames before the first TD */
188 frame += max_t (u16, 8, ed->interval);
189 frame &= ~(ed->interval - 1);
191 urb->start_frame = frame;
193 /* yes, only URB_ISO_ASAP is supported, and
194 * urb->start_frame is never used as input.
197 } else if (ed->type == PIPE_ISOCHRONOUS)
198 urb->start_frame = ed->last_iso + ed->interval;
200 /* fill the TDs and link them to the ed; and
201 * enable that part of the schedule, if needed
202 * and update count of queued periodic urbs
204 urb->hcpriv = urb_priv;
205 td_submit_urb(ahcd, urb);
207 #ifdef ADMHC_VERBOSE_DEBUG
208 admhc_dump_ed(ahcd, "admhc_urb_enqueue", urb_priv->ed, 1);
211 spin_unlock(&urb->lock);
214 urb_priv_free(ahcd, urb_priv);
216 spin_unlock_irqrestore(&ahcd->lock, flags);
221 * decouple the URB from the HC queues (TDs, urb_priv); it's
222 * already marked using urb->status. reporting is always done
223 * asynchronously, and we might be dealing with an urb that's
224 * partially transferred, or an ED with other urbs being unlinked.
226 static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
228 struct admhcd *ahcd = hcd_to_admhcd(hcd);
231 spin_lock_irqsave(&ahcd->lock, flags);
233 #ifdef ADMHC_VERBOSE_DEBUG
234 urb_print(ahcd, urb, "DEQUEUE", 1);
237 if (HC_IS_RUNNING(hcd->state)) {
238 struct urb_priv *urb_priv;
240 /* Unless an IRQ completed the unlink while it was being
241 * handed to us, flag it for unlink and giveback, and force
242 * some upcoming INTR_SF to call finish_unlinks()
244 urb_priv = urb->hcpriv;
246 if (urb_priv->ed->state == ED_OPER)
247 start_ed_unlink(ahcd, urb_priv->ed);
251 * with HC dead, we won't respect hc queue pointers
252 * any more ... just clean up every urb's memory.
255 finish_urb(ahcd, urb);
257 spin_unlock_irqrestore(&ahcd->lock, flags);
262 /*-------------------------------------------------------------------------*/
264 /* frees config/altsetting state for endpoints,
265 * including ED memory, dummy TD, and bulk/intr data toggle
268 static void admhc_endpoint_disable(struct usb_hcd *hcd,
269 struct usb_host_endpoint *ep)
271 struct admhcd *ahcd = hcd_to_admhcd(hcd);
273 struct ed *ed = ep->hcpriv;
274 unsigned limit = 1000;
276 /* ASSERT: any requests/urbs are being unlinked */
277 /* ASSERT: nobody can be submitting urbs for this any more */
282 #ifdef ADMHC_VERBOSE_DEBUG
283 spin_lock_irqsave(&ahcd->lock, flags);
284 admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
285 spin_unlock_irqrestore(&ahcd->lock, flags);
289 spin_lock_irqsave(&ahcd->lock, flags);
291 if (!HC_IS_RUNNING(hcd->state)) {
294 finish_unlinks(ahcd, 0);
298 case ED_UNLINK: /* wait for hw to finish? */
299 /* major IRQ delivery trouble loses INTR_SOFI too... */
301 admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
304 spin_unlock_irqrestore(&ahcd->lock, flags);
305 schedule_timeout_uninterruptible(1);
307 case ED_IDLE: /* fully unlinked */
308 if (list_empty(&ed->td_list)) {
309 td_free (ahcd, ed->dummy);
313 /* else FALL THROUGH */
315 /* caller was supposed to have unlinked any requests;
316 * that's not our job. can't recover; must leak ed.
318 admhc_err(ahcd, "leak ed %p (#%02x) state %d%s\n",
319 ed, ep->desc.bEndpointAddress, ed->state,
320 list_empty(&ed->td_list) ? "" : " (has tds)");
321 td_free(ahcd, ed->dummy);
327 spin_unlock_irqrestore(&ahcd->lock, flags);
331 static int admhc_get_frame_number(struct usb_hcd *hcd)
333 struct admhcd *ahcd = hcd_to_admhcd(hcd);
335 return admhc_frame_no(ahcd);
338 static void admhc_usb_reset(struct admhcd *ahcd)
341 ahcd->hc_control = admhc_readl(ahcd, &ahcd->regs->control);
342 ahcd->hc_control &= OHCI_CTRL_RWC;
343 admhc_writel(ahcd, ahcd->hc_control, &ahcd->regs->control);
346 ahcd->host_control = ADMHC_BUSS_RESET;
347 admhc_writel(ahcd, ahcd->host_control ,&ahcd->regs->host_control);
351 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
352 * other cases where the next software may expect clean state from the
353 * "firmware". this is bus-neutral, unlike shutdown() methods.
356 admhc_shutdown(struct usb_hcd *hcd)
360 ahcd = hcd_to_admhcd(hcd);
361 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
362 admhc_dma_disable(ahcd);
363 admhc_usb_reset(ahcd);
364 /* flush the writes */
365 admhc_writel_flush(ahcd);
368 /*-------------------------------------------------------------------------*
370 *-------------------------------------------------------------------------*/
372 static void admhc_eds_cleanup(struct admhcd *ahcd)
374 if (ahcd->ed_tails[PIPE_INTERRUPT]) {
375 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
376 ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
379 if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
380 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
381 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
384 if (ahcd->ed_tails[PIPE_CONTROL]) {
385 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
386 ahcd->ed_tails[PIPE_CONTROL] = NULL;
389 if (ahcd->ed_tails[PIPE_BULK]) {
390 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
391 ahcd->ed_tails[PIPE_BULK] = NULL;
394 ahcd->ed_head = NULL;
397 #define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
399 static int admhc_eds_init(struct admhcd *ahcd)
403 ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
407 ahcd->ed_tails[PIPE_INTERRUPT] = ed;
409 ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
413 ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
414 ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
415 ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
416 ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
418 ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
422 ahcd->ed_tails[PIPE_CONTROL] = ed;
423 ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
424 ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
425 ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
427 ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
431 ahcd->ed_tails[PIPE_BULK] = ed;
432 ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
433 ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
434 ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
436 ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
438 #ifdef ADMHC_VERBOSE_DEBUG
439 admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
440 admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
441 admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
442 admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
448 admhc_eds_cleanup(ahcd);
452 /* init memory, and kick BIOS/SMM off */
454 static int admhc_init(struct admhcd *ahcd)
456 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
460 ahcd->regs = hcd->regs;
462 /* Disable HC interrupts */
463 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
465 /* Read the number of ports unless overridden */
466 if (ahcd->num_ports == 0)
467 ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
469 ret = admhc_mem_init(ahcd);
473 /* init dummy endpoints */
474 ret = admhc_eds_init(ahcd);
478 create_debug_files(ahcd);
487 /*-------------------------------------------------------------------------*/
489 /* Start an OHCI controller, set the BUS operational
490 * resets USB and controller
493 static int admhc_run(struct admhcd *ahcd)
496 int first = ahcd->fminterval == 0;
497 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
501 /* boot firmware should have set this up (5.1.1.3.1) */
503 temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
504 ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
505 if (ahcd->fminterval != FI)
506 admhc_dbg(ahcd, "fminterval delta %d\n",
507 ahcd->fminterval - FI);
509 (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
510 /* also: power/overcurrent flags in rhdesc */
513 #if 0 /* TODO: not applicable */
514 /* Reset USB nearly "by the book". RemoteWakeupConnected was
515 * saved if boot firmware (BIOS/SMM/...) told us it's connected,
516 * or if bus glue did the same (e.g. for PCI add-in cards with
519 if ((ahcd->hc_control & OHCI_CTRL_RWC) != 0
520 && !device_may_wakeup(hcd->self.controller))
521 device_init_wakeup(hcd->self.controller, 1);
524 switch (ahcd->host_control & ADMHC_HC_BUSS) {
525 case ADMHC_BUSS_OPER:
528 case ADMHC_BUSS_SUSPEND:
530 case ADMHC_BUSS_RESUME:
531 ahcd->host_control = ADMHC_BUSS_RESUME;
532 temp = 10 /* msec wait */;
534 /* case ADMHC_BUSS_RESET: */
536 ahcd->host_control = ADMHC_BUSS_RESET;
537 temp = 50 /* msec wait */;
540 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
542 /* flush the writes */
543 admhc_writel_flush(ahcd);
546 temp = admhc_read_rhdesc(ahcd);
547 if (!(temp & ADMHC_RH_NPS)) {
548 /* power down each port */
549 for (temp = 0; temp < ahcd->num_ports; temp++)
550 admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
552 /* flush those writes */
553 admhc_writel_flush(ahcd);
555 /* 2msec timelimit here means no irqs/preempt */
556 spin_lock_irq(&ahcd->lock);
558 admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
559 temp = 30; /* ... allow extra time */
560 while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
562 spin_unlock_irq(&ahcd->lock);
563 admhc_err(ahcd, "USB HC reset timed out!\n");
569 /* enable HOST mode, before access any host specific register */
570 admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
572 /* Tell the controller where the descriptor list is */
573 admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
575 periodic_reinit(ahcd);
577 /* use rhsc irqs after khubd is fully initialized */
579 hcd->uses_new_polling = 1;
582 /* wake on ConnectStatusChange, matching external hubs */
583 admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
585 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
588 /* Choose the interrupts we care about now, others later on demand */
589 admhc_intr_ack(ahcd, ~0);
590 admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
592 admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
594 /* flush those writes */
595 admhc_writel_flush(ahcd);
597 /* start controller operations */
598 ahcd->host_control = ADMHC_BUSS_OPER;
599 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
602 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
603 & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
605 spin_unlock_irq(&ahcd->lock);
606 admhc_err(ahcd, "unable to setup operational mode!\n");
612 hcd->state = HC_STATE_RUNNING;
614 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
617 /* FIXME: enabling DMA is always failed here for an unknown reason */
618 admhc_dma_enable(ahcd);
621 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
622 & ADMHC_HC_DMAE) != ADMHC_HC_DMAE) {
624 spin_unlock_irq(&ahcd->lock);
625 admhc_err(ahcd, "unable to enable DMA!\n");
634 spin_unlock_irq(&ahcd->lock);
636 mdelay(ADMHC_POTPGT);
641 /*-------------------------------------------------------------------------*/
643 /* an interrupt happens */
645 static irqreturn_t admhc_irq(struct usb_hcd *hcd)
647 struct admhcd *ahcd = hcd_to_admhcd(hcd);
648 struct admhcd_regs __iomem *regs = ahcd->regs;
651 ints = admhc_readl(ahcd, ®s->int_status);
652 if ((ints & ADMHC_INTR_INTA) == 0) {
653 /* no unmasked interrupt status is set */
657 ints &= admhc_readl(ahcd, ®s->int_enable);
659 if (ints & ADMHC_INTR_FATI) {
660 /* e.g. due to PCI Master/Target Abort */
662 admhc_err(ahcd, "Fatal Error, controller disabled\n");
664 admhc_usb_reset(ahcd);
667 if (ints & ADMHC_INTR_BABI) {
668 admhc_intr_disable(ahcd, ADMHC_INTR_BABI);
669 admhc_intr_ack(ahcd, ADMHC_INTR_BABI);
670 admhc_err(ahcd, "Babble Detected\n");
673 if (ints & ADMHC_INTR_INSM) {
674 admhc_vdbg(ahcd, "Root Hub Status Change\n");
675 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
676 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
678 /* NOTE: Vendors didn't always make the same implementation
679 * choices for RHSC. Many followed the spec; RHSC triggers
680 * on an edge, like setting and maybe clearing a port status
681 * change bit. With others it's level-triggered, active
682 * until khubd clears all the port status change bits. We'll
683 * always disable it here and rely on polling until khubd
686 admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
687 usb_hcd_poll_rh_status(hcd);
688 } else if (ints & ADMHC_INTR_RESI) {
689 /* For connect and disconnect events, we expect the controller
690 * to turn on RHSC along with RD. But for remote wakeup events
691 * this might not happen.
693 admhc_vdbg(ahcd, "Resume Detect\n");
694 admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
696 if (ahcd->autostop) {
697 spin_lock(&ahcd->lock);
698 admhc_rh_resume(ahcd);
699 spin_unlock(&ahcd->lock);
701 usb_hcd_resume_root_hub(hcd);
704 if (ints & ADMHC_INTR_TDC) {
705 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
706 admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
707 if (HC_IS_RUNNING(hcd->state))
708 admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
709 spin_lock(&ahcd->lock);
710 admhc_td_complete(ahcd);
711 spin_unlock(&ahcd->lock);
712 if (HC_IS_RUNNING(hcd->state))
713 admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
716 if (ints & ADMHC_INTR_SO) {
717 /* could track INTR_SO to reduce available PCI/... bandwidth */
718 admhc_vdbg(ahcd, "Schedule Overrun\n");
722 spin_lock(&ahcd->lock);
723 if (ahcd->ed_rm_list)
724 finish_unlinks(ahcd, admhc_frame_no(ahcd));
726 if ((ints & ADMHC_INTR_SOFI) != 0 && !ahcd->ed_rm_list
727 && HC_IS_RUNNING(hcd->state))
728 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
729 spin_unlock(&ahcd->lock);
731 if (ints & ADMHC_INTR_SOFI) {
732 admhc_vdbg(ahcd, "Start Of Frame\n");
733 spin_lock(&ahcd->lock);
735 /* handle any pending ED removes */
736 finish_unlinks(ahcd, admhc_frameno(ahcd));
738 /* leaving INTR_SOFI enabled when there's still unlinking
739 * to be done in the (next frame).
741 if ((ahcd->ed_rm_list == NULL) ||
742 HC_IS_RUNNING(hcd->state) == 0)
744 * disable INTR_SOFI if there are no unlinking to be
745 * done (in the next frame)
747 admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
749 spin_unlock(&ahcd->lock);
753 if (HC_IS_RUNNING(hcd->state)) {
754 admhc_intr_ack(ahcd, ints);
755 admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
756 admhc_writel_flush(ahcd);
762 /*-------------------------------------------------------------------------*/
764 static void admhc_stop(struct usb_hcd *hcd)
766 struct admhcd *ahcd = hcd_to_admhcd(hcd);
770 flush_scheduled_work();
772 admhc_usb_reset(ahcd);
773 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
775 free_irq(hcd->irq, hcd);
778 remove_debug_files(ahcd);
779 admhc_eds_cleanup(ahcd);
780 admhc_mem_cleanup(ahcd);
783 /*-------------------------------------------------------------------------*/
785 #ifdef CONFIG_MIPS_ADM5120
786 #include "adm5120-drv.c"
787 #define PLATFORM_DRIVER usb_hcd_adm5120_driver
790 #if !defined(PLATFORM_DRIVER)
791 #error "missing bus glue for admhc-hcd"
794 #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
796 static int __init admhc_hcd_mod_init(void)
803 pr_info("%s: " DRIVER_INFO "\n", hcd_name);
804 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
805 sizeof (struct ed), sizeof (struct td));
807 #ifdef PLATFORM_DRIVER
808 ret = platform_driver_register(&PLATFORM_DRIVER);
815 #ifdef PLATFORM_DRIVER
816 platform_driver_unregister(&PLATFORM_DRIVER);
821 module_init(admhc_hcd_mod_init);
823 static void __exit admhc_hcd_mod_exit(void)
825 platform_driver_unregister(&PLATFORM_DRIVER);
827 module_exit(admhc_hcd_mod_exit);
829 MODULE_AUTHOR(DRIVER_AUTHOR);
830 MODULE_DESCRIPTION(DRIVER_INFO);
831 MODULE_LICENSE("GPL");