1 /*****************************************************************************
2 ** FILE NAME : ifxusb_cif.c
3 ** PROJECT : IFX USB sub-system V3
4 ** MODULES : IFX USB sub-system Host and Device driver
8 ** DESCRIPTION : The Core Interface provides basic services for accessing and
9 ** managing the IFX USB hardware. These services are used by both the
10 ** Host Controller Driver and the Peripheral Controller Driver.
13 ** REFERENCE : Synopsys DWC-OTG Driver 2.7
14 ** COPYRIGHT : Copyright (c) 2010
15 ** LANTIQ DEUTSCHLAND GMBH,
16 ** Am Campeon 3, 85579 Neubiberg, Germany
18 ** This program is free software; you can redistribute it and/or modify
19 ** it under the terms of the GNU General Public License as published by
20 ** the Free Software Foundation; either version 2 of the License, or
21 ** (at your option) any later version.
23 ** Version Control Section **
27 ** $Log$ Revision history
28 *****************************************************************************/
31 * This file contains code fragments from Synopsys HS OTG Linux Software Driver.
32 * For this code the following notice is applicable:
34 * ==========================================================================
36 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
37 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
38 * otherwise expressly agreed to in writing between Synopsys and you.
40 * The Software IS NOT an item of Licensed Software or Licensed Product under
41 * any End User Software License Agreement or Agreement for Licensed Product
42 * with Synopsys or any supplement thereto. You are permitted to use and
43 * redistribute this Software in source and binary forms, with or without
44 * modification, provided that redistributions of source code must retain this
45 * notice. You may not view, use, disclose, copy or distribute this file or
46 * any information contained herein except pursuant to this license grant from
47 * Synopsys. If you do not agree with this notice, including the disclaimer
48 * below, then you are not authorized to use the Software.
50 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
51 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
54 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
55 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
56 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
57 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
58 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
59 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
61 * ========================================================================== */
65 \ingroup IFXUSB_DRIVER_V3
66 \brief This file contains the interface to the IFX USB Core.
69 #include <linux/version.h>
70 #include "ifxusb_version.h"
72 #include <asm/byteorder.h>
73 #include <asm/unaligned.h>
76 #include <linux/jiffies.h>
77 #include <linux/platform_device.h>
78 #include <linux/kernel.h>
79 #include <linux/ioport.h>
83 #include "ifxusb_plat.h"
84 #include "ifxusb_regs.h"
85 #include "ifxusb_cif.h"
98 #include <linux/gfp.h>
100 #include <lantiq_soc.h>
102 #if defined(__UEIP__)
103 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
104 #ifndef USB_CTRL_PMU_SETUP
105 #define USB_CTRL_PMU_SETUP(__x) USB0_CTRL_PMU_SETUP(__x)
107 #ifndef USB_PHY_PMU_SETUP
108 #define USB_PHY_PMU_SETUP(__x) USB0_PHY_PMU_SETUP(__x)
110 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
111 #endif // defined(__UEIP__)
114 \brief This function is called to allocate buffer of specified size.
115 The allocated buffer is mapped into DMA accessable address.
116 \param size Size in BYTE to be allocated
117 \param clear 0: don't do clear after buffer allocated, other: do clear to zero
118 \return 0/NULL: Fail; uncached pointer of allocated buffer
121 void *ifxusb_alloc_buf_h(size_t size, int clear)
123 void *ifxusb_alloc_buf_d(size_t size, int clear)
126 uint32_t *cached,*uncached;
127 uint32_t totalsize,page;
132 size=(size+3)&0xFFFFFFFC;
134 page=get_order(totalsize);
136 cached = (void *) __get_free_pages(( GFP_ATOMIC | GFP_DMA), page);
140 IFX_PRINT("%s Allocation Failed size:%d\n",__func__,size);
144 uncached = (uint32_t *)(KSEG1ADDR(cached));
146 memset(uncached, 0, totalsize);
148 *(uncached+0)=totalsize;
150 *(uncached+2)=(uint32_t)cached;
151 return (void *)(uncached+3);
156 \brief This function is called to free allocated buffer.
157 \param vaddr the uncached pointer of the buffer
160 void ifxusb_free_buf_h(void *vaddr)
162 void ifxusb_free_buf_d(void *vaddr)
165 uint32_t totalsize,page;
166 uint32_t *cached,*uncached;
172 totalsize=*(uncached+0);
174 cached=(uint32_t *)(*(uncached+2));
175 if(totalsize && page==get_order(totalsize) && cached==(uint32_t *)(KSEG0ADDR(uncached)))
177 free_pages((unsigned long)cached, page);
180 // the memory is not allocated by ifxusb_alloc_buf. Allowed but must be careful.
188 \brief This function is called to initialize the IFXUSB CSR data
189 structures. The register addresses in the device and host
190 structures are initialized from the base address supplied by the
191 caller. The calling function must make the OS calls to get the
192 base address of the IFXUSB controller registers.
194 \param _core_if Pointer of core_if structure
195 \param _irq irq number
196 \param _reg_base_addr Base address of IFXUSB core registers
197 \param _fifo_base_addr Fifo base address
198 \param _fifo_dbg_addr Fifo debug address
202 int ifxusb_core_if_init_h(ifxusb_core_if_t *_core_if,
204 int ifxusb_core_if_init_d(ifxusb_core_if_t *_core_if,
207 uint32_t _reg_base_addr,
208 uint32_t _fifo_base_addr,
209 uint32_t _fifo_dbg_addr)
212 uint32_t *reg_base =NULL;
213 uint32_t *fifo_base =NULL;
214 uint32_t *fifo_dbg =NULL;
218 IFX_DEBUGPL(DBG_CILV, "%s(%p,%d,0x%08X,0x%08X,0x%08X)\n", __func__,
225 if( _core_if == NULL)
227 IFX_ERROR("%s() invalid _core_if\n", __func__);
232 //memset(_core_if, 0, sizeof(ifxusb_core_if_t));
236 reg_base =ioremap_nocache(_reg_base_addr , IFXUSB_IOMEM_SIZE );
237 fifo_base =ioremap_nocache(_fifo_base_addr, IFXUSB_FIFOMEM_SIZE);
238 fifo_dbg =ioremap_nocache(_fifo_dbg_addr , IFXUSB_FIFODBG_SIZE);
239 if( reg_base == NULL || fifo_base == NULL || fifo_dbg == NULL)
241 IFX_ERROR("%s() usb ioremap() failed\n", __func__);
246 _core_if->core_global_regs = (ifxusb_core_global_regs_t *)reg_base;
249 * Attempt to ensure this device is really a IFXUSB Controller.
250 * Read and verify the SNPSID register contents. The value should be
255 snpsid = ifxusb_rreg(&_core_if->core_global_regs->gsnpsid);
256 if ((snpsid & 0xFFFFF000) != 0x4F542000)
258 IFX_ERROR("%s() snpsid error(0x%08x) failed\n", __func__,snpsid);
262 _core_if->snpsid=snpsid;
266 _core_if->host_global_regs = (ifxusb_host_global_regs_t *)
267 ((uint32_t)reg_base + IFXUSB_HOST_GLOBAL_REG_OFFSET);
268 _core_if->hprt0 = (uint32_t*)((uint32_t)reg_base + IFXUSB_HOST_PORT_REGS_OFFSET);
270 for (i=0; i<MAX_EPS_CHANNELS; i++)
272 _core_if->hc_regs[i] = (ifxusb_hc_regs_t *)
273 ((uint32_t)reg_base + IFXUSB_HOST_CHAN_REGS_OFFSET +
274 (i * IFXUSB_CHAN_REGS_OFFSET));
275 IFX_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
276 i, &_core_if->hc_regs[i]->hcchar);
281 _core_if->dev_global_regs =
282 (ifxusb_device_global_regs_t *)((uint32_t)reg_base + IFXUSB_DEV_GLOBAL_REG_OFFSET);
284 for (i=0; i<MAX_EPS_CHANNELS; i++)
286 _core_if->in_ep_regs[i] = (ifxusb_dev_in_ep_regs_t *)
287 ((uint32_t)reg_base + IFXUSB_DEV_IN_EP_REG_OFFSET +
288 (i * IFXUSB_EP_REG_OFFSET));
289 _core_if->out_ep_regs[i] = (ifxusb_dev_out_ep_regs_t *)
290 ((uint32_t)reg_base + IFXUSB_DEV_OUT_EP_REG_OFFSET +
291 (i * IFXUSB_EP_REG_OFFSET));
292 IFX_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p/%p %p/0x%08X/0x%08X\n",
293 i, &_core_if->in_ep_regs[i]->diepctl, _core_if->in_ep_regs[i],
294 reg_base,IFXUSB_DEV_IN_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET)
296 IFX_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p/%p %p/0x%08X/0x%08X\n",
297 i, &_core_if->out_ep_regs[i]->doepctl, _core_if->out_ep_regs[i],
298 reg_base,IFXUSB_DEV_OUT_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET)
301 #endif //__IS_DEVICE__
303 /* Setting the FIFO and other Address. */
304 for (i=0; i<MAX_EPS_CHANNELS; i++)
306 _core_if->data_fifo[i] = fifo_base + (i * IFXUSB_DATA_FIFO_SIZE);
307 IFX_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
308 i, (unsigned)_core_if->data_fifo[i]);
311 _core_if->data_fifo_dbg = fifo_dbg;
312 _core_if->pcgcctl = (uint32_t*)(((uint32_t)reg_base) + IFXUSB_PCGCCTL_OFFSET);
315 * Store the contents of the hardware configuration registers here for
318 _core_if->hwcfg1.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg1);
319 _core_if->hwcfg2.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg2);
320 _core_if->hwcfg3.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg3);
321 _core_if->hwcfg4.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg4);
323 IFX_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",_core_if->hwcfg1.d32);
324 IFX_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",_core_if->hwcfg2.d32);
325 IFX_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",_core_if->hwcfg3.d32);
326 IFX_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",_core_if->hwcfg4.d32);
331 unsigned int countdown=0xFFFF;
332 IFX_PRINT("Waiting for PHY Clock Lock!\n");
333 while(--countdown && !( ifxusb_rreg(&_core_if->core_global_regs->grxfsiz) & (1<<9)))
338 IFX_PRINT("PHY Clock Locked!\n");
340 IFX_PRINT("PHY Clock Not Locked! %08X\n",ifxusb_rreg(&_core_if->core_global_regs->grxfsiz));
344 /* Create new workqueue and init works */
346 _core_if->wq_usb = create_singlethread_workqueue(_core_if->core_name);
348 if(_core_if->wq_usb == 0)
350 IFX_DEBUGPL(DBG_CIL, "Creation of wq_usb failed\n");
355 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
356 INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if);
357 INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if);
359 INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change);
360 INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected);
366 if( reg_base != NULL) iounmap(reg_base );
367 if( fifo_base != NULL) iounmap(fifo_base);
368 if( fifo_dbg != NULL) iounmap(fifo_dbg );
373 \brief This function free the mapped address in the IFXUSB CSR data structures.
374 \param _core_if Pointer of core_if structure
377 void ifxusb_core_if_remove_h(ifxusb_core_if_t *_core_if)
379 void ifxusb_core_if_remove_d(ifxusb_core_if_t *_core_if)
382 /* Disable all interrupts */
383 if( _core_if->core_global_regs != NULL)
385 gusbcfg_data_t usbcfg ={.d32 = 0};
386 usbcfg.d32 = ifxusb_rreg( &_core_if->core_global_regs->gusbcfg);
387 usbcfg.b.ForceDevMode=0;
388 usbcfg.b.ForceHstMode=0;
389 ifxusb_wreg( &_core_if->core_global_regs->gusbcfg,usbcfg.d32);
390 ifxusb_mreg( &_core_if->core_global_regs->gahbcfg, 1, 0);
391 ifxusb_wreg( &_core_if->core_global_regs->gintmsk, 0);
394 if( _core_if->core_global_regs != NULL) iounmap(_core_if->core_global_regs );
395 if( _core_if->data_fifo[0] != NULL) iounmap(_core_if->data_fifo[0] );
396 if( _core_if->data_fifo_dbg != NULL) iounmap(_core_if->data_fifo_dbg );
399 if (_core_if->wq_usb)
400 destroy_workqueue(_core_if->wq_usb);
402 memset(_core_if, 0, sizeof(ifxusb_core_if_t));
409 \brief This function enbles the controller's Global Interrupt in the AHB Config register.
410 \param _core_if Pointer of core_if structure
413 void ifxusb_enable_global_interrupts_h( ifxusb_core_if_t *_core_if )
415 void ifxusb_enable_global_interrupts_d( ifxusb_core_if_t *_core_if )
418 gahbcfg_data_t ahbcfg ={ .d32 = 0};
419 ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
420 ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
424 \brief This function disables the controller's Global Interrupt in the AHB Config register.
425 \param _core_if Pointer of core_if structure
428 void ifxusb_disable_global_interrupts_h( ifxusb_core_if_t *_core_if )
430 void ifxusb_disable_global_interrupts_d( ifxusb_core_if_t *_core_if )
433 gahbcfg_data_t ahbcfg ={ .d32 = 0};
434 ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
435 ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
442 \brief Flush Tx and Rx FIFO.
443 \param _core_if Pointer of core_if structure
446 void ifxusb_flush_both_fifo_h( ifxusb_core_if_t *_core_if )
448 void ifxusb_flush_both_fifo_d( ifxusb_core_if_t *_core_if )
451 ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
452 volatile grstctl_t greset ={ .d32 = 0};
455 IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
456 greset.b.rxfflsh = 1;
457 greset.b.txfflsh = 1;
458 greset.b.txfnum = 0x10;
459 greset.b.intknqflsh=1;
461 ifxusb_wreg( &global_regs->grstctl, greset.d32 );
465 greset.d32 = ifxusb_rreg( &global_regs->grstctl);
468 IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32);
471 } while (greset.b.rxfflsh == 1 || greset.b.txfflsh == 1);
472 /* Wait for 3 PHY Clocks*/
477 \brief Flush a Tx FIFO.
478 \param _core_if Pointer of core_if structure
479 \param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO )
482 void ifxusb_flush_tx_fifo_h( ifxusb_core_if_t *_core_if, const int _num )
484 void ifxusb_flush_tx_fifo_d( ifxusb_core_if_t *_core_if, const int _num )
487 ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
488 volatile grstctl_t greset ={ .d32 = 0};
491 IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num);
493 greset.b.intknqflsh=1;
494 greset.b.txfflsh = 1;
495 greset.b.txfnum = _num;
496 ifxusb_wreg( &global_regs->grstctl, greset.d32 );
500 greset.d32 = ifxusb_rreg( &global_regs->grstctl);
501 if (++count > 10000&&(_num==0 ||_num==0x10))
503 IFX_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
504 __func__, greset.d32,
505 ifxusb_rreg( &global_regs->gnptxsts));
508 } while (greset.b.txfflsh == 1);
509 /* Wait for 3 PHY Clocks*/
515 \brief Flush Rx FIFO.
516 \param _core_if Pointer of core_if structure
519 void ifxusb_flush_rx_fifo_h( ifxusb_core_if_t *_core_if )
521 void ifxusb_flush_rx_fifo_d( ifxusb_core_if_t *_core_if )
524 ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
525 volatile grstctl_t greset ={ .d32 = 0};
528 IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__);
529 greset.b.rxfflsh = 1;
530 ifxusb_wreg( &global_regs->grstctl, greset.d32 );
534 greset.d32 = ifxusb_rreg( &global_regs->grstctl);
537 IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32);
540 } while (greset.b.rxfflsh == 1);
541 /* Wait for 3 PHY Clocks*/
546 #define SOFT_RESET_DELAY 100 /*!< Delay in msec of detection after soft-reset of usb core */
549 \brief Do a soft reset of the core. Be careful with this because it
550 resets all the internal state machines of the core.
551 \param _core_if Pointer of core_if structure
554 int ifxusb_core_soft_reset_h(ifxusb_core_if_t *_core_if)
556 int ifxusb_core_soft_reset_d(ifxusb_core_if_t *_core_if)
559 ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs;
560 volatile grstctl_t greset ={ .d32 = 0};
563 IFX_DEBUGPL(DBG_CILV, "%s\n", __func__);
564 /* Wait for AHB master IDLE state. */
568 greset.d32 = ifxusb_rreg( &global_regs->grstctl);
569 if (++count > 100000)
571 IFX_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__,
572 greset.d32, greset.b.ahbidle);
575 } while (greset.b.ahbidle == 0);
579 /* Core Soft Reset */
581 greset.b.csftrst = 1;
582 ifxusb_wreg( &global_regs->grstctl, greset.d32 );
584 #ifdef SOFT_RESET_DELAY
585 MDELAY(SOFT_RESET_DELAY);
591 greset.d32 = ifxusb_rreg( &global_regs->grstctl);
592 if (++count > 100000)
594 IFX_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, greset.d32);
597 } while (greset.b.csftrst == 1);
599 #ifdef SOFT_RESET_DELAY
600 MDELAY(SOFT_RESET_DELAY);
603 // This is to reset the PHY of VR9
604 #if defined(__IS_VR9__)
605 if(_core_if->core_no==0)
607 set_bit (4, VR9_RCU_USBRESET2);
609 clear_bit (4, VR9_RCU_USBRESET2);
613 set_bit (5, VR9_RCU_USBRESET2);
615 clear_bit (5, VR9_RCU_USBRESET2);
618 #endif //defined(__IS_VR9__)
620 IFX_PRINT("USB core #%d soft-reset\n",_core_if->core_no);
626 \brief Turn on the USB Core Power
627 \param _core_if Pointer of core_if structure
630 void ifxusb_power_on_h (ifxusb_core_if_t *_core_if)
632 void ifxusb_power_on_d (ifxusb_core_if_t *_core_if)
635 IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ );
636 #if defined(__UEIP__)
639 #if defined(__IS_TWINPASS) || defined(__IS_DANUBE__)
640 set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR);
641 set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR);
642 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
643 #if defined(__IS_AMAZON_SE__)
644 // clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
645 clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
646 #endif //defined(__IS_AMAZON_SE__)
647 #if defined(__IS_AR9__)
648 set_bit (0, (volatile unsigned long *)AR9_CGU_IFCCR);
649 set_bit (1, (volatile unsigned long *)AR9_CGU_IFCCR);
650 #endif //defined(__IS_AR9__)
651 #if defined(__IS_VR9__)
652 // set_bit (0, (volatile unsigned long *)VR9_CGU_IFCCR);
653 // set_bit (1, (volatile unsigned long *)VR9_CGU_IFCCR);
654 #endif //defined(__IS_VR9__)
655 #if defined(__IS_AR10__)
656 // set_bit (0, (volatile unsigned long *)VR9_CGU_IFCCR);
657 // set_bit (1, (volatile unsigned long *)VR9_CGU_IFCCR);
658 #endif //defined(__IS_AR10__)
661 #define PMU_AHBM BIT(15)
662 #define PMU_USB0 BIT(6)
663 #define PMU_USB1 BIT(27)
664 #define PMU_USB0_P BIT(0)
665 #define PMU_USB1_P BIT(26)
667 ltq_pmu_enable(PMU_AHBM);
668 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
669 ltq_pmu_enable(PMU_USB0);
670 //#if defined(__IS_TWINPASS__)
671 // ifxusb_enable_afe_oc();
673 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
674 #if defined(__IS_AR9__) || defined(__IS_VR9__)
675 if(_core_if->core_no==0)
676 ltq_pmu_enable(PMU_USB0);
678 ltq_pmu_enable(PMU_USB1);
679 #endif //defined(__IS_AR9__) || defined(__IS_VR9__)
680 #if defined(__IS_AR10__)
681 //if(_core_if->core_no==0)
682 // USB0_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
684 // USB1_CTRL_PMU_SETUP(IFX_PMU_ENABLE);
685 #endif //defined(__IS_AR10__)
689 if(_core_if->pcgcctl)
691 pcgcctl_data_t pcgcctl = {.d32=0};
692 pcgcctl.b.gatehclk = 1;
693 ifxusb_mreg(_core_if->pcgcctl, pcgcctl.d32, 0);
697 if(_core_if->core_global_regs)
699 // PHY configurations.
700 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
701 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
702 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
703 #if defined(__IS_AMAZON_SE__)
704 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
705 #endif //defined(__IS_AMAZON_SE__)
706 #if defined(__IS_AR9__)
707 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
708 #endif //defined(__IS_AR9__)
709 #if defined(__IS_VR9__)
710 //ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
711 #endif //defined(__IS_VR9__)
712 #if defined(__IS_AR10__)
713 //ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
714 #endif //defined(__IS_AR10__)
716 #else //defined(__UEIP__)
718 #if defined(__IS_TWINPASS) || defined(__IS_DANUBE__)
719 set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR);
720 set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR);
721 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
722 #if defined(__IS_AMAZON_SE__)
723 // clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
724 clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR);
725 #endif //defined(__IS_AMAZON_SE__)
726 #if defined(__IS_AR9__)
727 set_bit (0, (volatile unsigned long *)AMAZON_S_CGU_IFCCR);
728 set_bit (1, (volatile unsigned long *)AMAZON_S_CGU_IFCCR);
729 #endif //defined(__IS_AR9__)
734 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
735 clear_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB
736 clear_bit (9, (volatile unsigned long *)DANUBE_PMU_PWDCR);//DSL
737 clear_bit (15, (volatile unsigned long *)DANUBE_PMU_PWDCR);//AHB
738 #if defined(__IS_TWINPASS__)
739 ifxusb_enable_afe_oc();
741 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
742 #if defined(__IS_AMAZON_SE__)
743 clear_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
744 clear_bit (9, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
745 clear_bit (15, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
746 #endif //defined(__IS_AMAZON_SE__)
747 #if defined(__IS_AR9__)
748 if(_core_if->core_no==0)
749 clear_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
751 clear_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
752 clear_bit (9, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//DSL
753 clear_bit (15, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//AHB
754 #endif //defined(__IS_AR9__)
756 if(_core_if->core_global_regs)
758 // PHY configurations.
759 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
760 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
761 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
762 #if defined(__IS_AMAZON_SE__)
763 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
764 #endif //defined(__IS_AMAZON_SE__)
765 #if defined(__IS_AR9__)
766 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
767 #endif //defined(__IS_AR9__)
770 #endif //defined(__UEIP__)
774 \brief Turn off the USB Core Power
775 \param _core_if Pointer of core_if structure
778 void ifxusb_power_off_h (ifxusb_core_if_t *_core_if)
780 void ifxusb_power_off_d (ifxusb_core_if_t *_core_if)
785 ifxusb_phy_power_off_h (_core_if);
787 ifxusb_phy_power_off_d (_core_if);
790 #if defined(__UEIP__)
791 //AHBM_PMU_SETUP(IFX_PMU_DISABLE);
793 if(_core_if->pcgcctl)
795 pcgcctl_data_t pcgcctl = {.d32=0};
796 pcgcctl.b.gatehclk = 1;
797 pcgcctl.b.stoppclk = 1;
798 ifxusb_mreg(_core_if->pcgcctl, 0, pcgcctl.d32);
800 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
801 //USB_CTRL_PMU_SETUP(IFX_PMU_DISABLE);
802 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
803 #if defined(__IS_AR9__) || defined(__IS_VR9__)
804 /* if(_core_if->core_no==0)
805 USB0_CTRL_PMU_SETUP(IFX_PMU_DISABLE);
807 USB1_CTRL_PMU_SETUP(IFX_PMU_DISABLE);*/
808 #endif //defined(__IS_AR9__) || defined(__IS_VR9__)
809 #if defined(__IS_AR10__)
810 //if(_core_if->core_no==0)
811 // USB0_CTRL_PMU_SETUP(IFX_PMU_DISABLE);
813 // USB1_CTRL_PMU_SETUP(IFX_PMU_DISABLE);
814 #endif //defined(__IS_AR10__)
815 #else //defined(__UEIP__)
817 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
818 set_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB
819 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
820 #if defined(__IS_AMAZON_SE__)
821 set_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//USB
822 #endif //defined(__IS_AMAZON_SE__)
823 #if defined(__IS_AR9__)
824 if(_core_if->core_no==0)
825 set_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
827 set_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB
828 #endif //defined(__IS_AR9__)
829 #endif //defined(__UEIP__)
833 \brief Turn on the USB PHY Power
834 \param _core_if Pointer of core_if structure
837 void ifxusb_phy_power_on_h (ifxusb_core_if_t *_core_if)
839 void ifxusb_phy_power_on_d (ifxusb_core_if_t *_core_if)
842 #if defined(__UEIP__)
843 if(_core_if->core_global_regs)
845 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
846 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
847 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
848 #if defined(__IS_AMAZON_SE__)
849 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
850 #endif //defined(__IS_AMAZON_SE__)
851 #if defined(__IS_AR9__)
852 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
853 #endif //defined(__IS_AR9__)
854 #if ( defined(__IS_VR9__) || defined(__IS_AR10__)) && defined(__PHY_LONG_PREEMP__)
855 if(_core_if->core_no==0)
856 set_bit (0, VR9_RCU_USB_ANA_CFG1A);
858 set_bit (0, VR9_RCU_USB_ANA_CFG1B);
859 #endif //( defined(__IS_VR9__) || defined(__IS_AR10__)) && defined(__PHY_LONG_PREEMP__)
861 if(_core_if->pcgcctl)
863 pcgcctl_data_t pcgcctl = {.d32=0};
864 pcgcctl.b.stoppclk = 1;
865 ifxusb_mreg(_core_if->pcgcctl, pcgcctl.d32, 0);
869 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
870 ltq_pmu_enable(PMU_USB0_P);
871 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
872 #if defined(__IS_AR9__) || defined(__IS_VR9__) || defined(__IS_AR10__)
873 if(_core_if->core_no==0)
874 ltq_pmu_enable(PMU_USB0_P);
876 ltq_pmu_enable(PMU_USB1_P);
877 #endif //defined(__IS_AR9__) || defined(__IS_VR9__)
879 // PHY configurations.
880 if(_core_if->core_global_regs)
882 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
883 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
884 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
885 #if defined(__IS_AMAZON_SE__)
886 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
887 #endif //defined(__IS_AMAZON_SE__)
888 #if defined(__IS_AR9__)
889 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
890 #endif //defined(__IS_AR9__)
891 #if ( defined(__IS_VR9__) || defined(__IS_AR10__)) && defined(__PHY_LONG_PREEMP__)
892 if(_core_if->core_no==0)
893 set_bit (0, VR9_RCU_USB_ANA_CFG1A);
895 set_bit (0, VR9_RCU_USB_ANA_CFG1B);
896 #endif //( defined(__IS_VR9__) || defined(__IS_AR10__)) && defined(__PHY_LONG_PREEMP__)
898 #else //defined(__UEIP__)
899 // PHY configurations.
900 if(_core_if->core_global_regs)
902 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
903 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
904 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
905 #if defined(__IS_AMAZON_SE__)
906 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
907 #endif //defined(__IS_AMAZON_SE__)
908 #if defined(__IS_AR9__)
909 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
910 #endif //defined(__IS_AR9__)
913 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
914 clear_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY
915 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
916 #if defined(__IS_AMAZON_SE__)
917 clear_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);
918 #endif //defined(__IS_AMAZON_SE__)
919 #if defined(__IS_AR9__)
920 if(_core_if->core_no==0)
921 clear_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
923 clear_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
924 #endif //defined(__IS_AR9__)
926 // PHY configurations.
927 if(_core_if->core_global_regs)
929 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
930 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
931 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
932 #if defined(__IS_AMAZON_SE__)
933 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
934 #endif //defined(__IS_AMAZON_SE__)
935 #if defined(__IS_AR9__)
936 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
937 #endif //defined(__IS_AR9__)
939 #endif //defined(__UEIP__)
944 \brief Turn off the USB PHY Power
945 \param _core_if Pointer of core_if structure
948 void ifxusb_phy_power_off_h (ifxusb_core_if_t *_core_if)
950 void ifxusb_phy_power_off_d (ifxusb_core_if_t *_core_if)
953 #if defined(__UEIP__)
954 if(_core_if->pcgcctl)
956 pcgcctl_data_t pcgcctl = {.d32=0};
957 pcgcctl.b.stoppclk = 1;
958 ifxusb_mreg(_core_if->pcgcctl, 0, pcgcctl.d32);
960 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
961 //USB_PHY_PMU_SETUP(IFX_PMU_DISABLE);
962 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__)
963 #if defined(__IS_AR9__) || defined(__IS_VR9__) || defined(__IS_AR10__)
964 /* if(_core_if->core_no==0)
965 USB0_PHY_PMU_SETUP(IFX_PMU_DISABLE);
967 USB1_PHY_PMU_SETUP(IFX_PMU_DISABLE);*/
968 #endif // defined(__IS_AR9__) || defined(__IS_VR9__)
969 #else //defined(__UEIP__)
970 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
971 set_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY
972 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
973 #if defined(__IS_AMAZON_SE__)
974 set_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//PHY
975 #endif //defined(__IS_AMAZON_SE__)
976 #if defined(__IS_AR9__)
977 if(_core_if->core_no==0)
978 set_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
980 set_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY
981 #endif //defined(__IS_AR9__)
982 #endif //defined(__UEIP__)
987 \brief Reset on the USB Core RCU
988 \param _core_if Pointer of core_if structure
990 #if defined(__IS_VR9__) || defined(__IS_AR10__)
991 static int CheckAlready(void)
993 gusbcfg_data_t usbcfg ={.d32 = 0};
994 usbcfg.d32 = ifxusb_rreg((volatile uint32_t *)0xBE10100C);
995 if(usbcfg.b.ForceDevMode)
997 if(usbcfg.b.ForceHstMode)
999 usbcfg.d32 = ifxusb_rreg((volatile uint32_t *)0xBE10600C);
1000 if(usbcfg.b.ForceDevMode)
1002 if(usbcfg.b.ForceHstMode)
1009 void ifxusb_hard_reset_h(ifxusb_core_if_t *_core_if)
1011 void ifxusb_hard_reset_d(ifxusb_core_if_t *_core_if)
1014 #if defined(__UEIP__)
1015 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1016 #if defined (__IS_HOST__)
1017 clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
1018 #elif defined (__IS_DEVICE__)
1019 set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
1021 #endif //defined(__IS_AMAZON_SE__)
1023 #if defined(__IS_AMAZON_SE__)
1024 #if defined (__IS_HOST__)
1025 clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
1026 #elif defined (__IS_DEVICE__)
1027 set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
1029 #endif //defined(__IS_AMAZON_SE__)
1031 #if defined(__IS_AR9__)
1032 if(_core_if->core_no==0)
1034 #if defined (__IS_HOST__)
1035 clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
1036 #elif defined (__IS_DEVICE__)
1037 set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
1042 #if defined (__IS_HOST__)
1043 clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
1044 #elif defined (__IS_DEVICE__)
1045 set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
1048 #endif //defined(__IS_AR9__)
1050 #if defined(__IS_VR9__)
1053 #if defined (__IS_HOST__)
1054 #if defined (__IS_DUAL__)
1055 clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
1056 clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
1057 #elif defined (__IS_FIRST__)
1058 clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
1059 set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
1060 #elif defined (__IS_SECOND__)
1061 set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
1062 clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
1065 #if defined (__IS_DEVICE__)
1066 #if defined (__IS_FIRST__)
1067 set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
1068 clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
1069 #elif defined (__IS_SECOND__)
1070 clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
1071 set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
1075 #endif //defined(__IS_VR9__)
1077 #if defined(__IS_AR10__)
1080 #if defined (__IS_HOST__)
1081 #if defined (__IS_DUAL__)
1082 clear_bit (AR10_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR10_RCU_USB1CFG);
1083 clear_bit (AR10_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR10_RCU_USB2CFG);
1084 #elif defined (__IS_FIRST__)
1085 clear_bit (AR10_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR10_RCU_USB1CFG);
1086 set_bit (AR10_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR10_RCU_USB2CFG);
1087 #elif defined (__IS_SECOND__)
1088 set_bit (AR10_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR10_RCU_USB1CFG);
1089 clear_bit (AR10_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR10_RCU_USB2CFG);
1092 #if defined (__IS_DEVICE__)
1093 #if defined (__IS_FIRST__)
1094 set_bit (AR10_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR10_RCU_USB1CFG);
1095 clear_bit (AR10_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR10_RCU_USB2CFG);
1096 #elif defined (__IS_SECOND__)
1097 clear_bit (AR10_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR10_RCU_USB1CFG);
1098 set_bit (AR10_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR10_RCU_USB2CFG);
1102 #endif //defined(__IS_AR10__)
1104 // set the HC's byte-order to big-endian
1105 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1106 set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
1107 clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
1108 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1109 #if defined(__IS_AMAZON_SE__)
1110 set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
1111 clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
1112 #endif //defined(__IS_AMAZON_SE__)
1113 #if defined(__IS_AR9__)
1114 if(_core_if->core_no==0)
1116 set_bit (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
1117 clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG);
1121 set_bit (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
1122 clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG);
1124 #endif //defined(__IS_AR9__)
1125 #if defined(__IS_VR9__)
1126 if(_core_if->core_no==0)
1128 set_bit (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
1129 clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG);
1133 set_bit (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
1134 clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG);
1136 #endif //defined(__IS_VR9__)
1137 #if defined(__IS_AR10__)
1138 if(_core_if->core_no==0)
1140 set_bit (AR10_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR10_RCU_USB1CFG);
1141 clear_bit (AR10_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR10_RCU_USB1CFG);
1145 set_bit (AR10_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR10_RCU_USB2CFG);
1146 clear_bit (AR10_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR10_RCU_USB2CFG);
1148 #endif //defined(__IS_AR10__)
1150 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1151 set_bit (4, DANUBE_RCU_RESET);
1153 clear_bit (4, DANUBE_RCU_RESET);
1155 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1157 #if defined(__IS_AMAZON_SE__)
1158 set_bit (4, AMAZON_SE_RCU_RESET);
1160 clear_bit (4, AMAZON_SE_RCU_RESET);
1162 #endif //defined(__IS_AMAZON_SE__)
1164 #if defined(__IS_AR9__)
1165 if(_core_if->core_no==0)
1167 set_bit (4, AR9_RCU_USBRESET);
1169 clear_bit (4, AR9_RCU_USBRESET);
1173 set_bit (28, AR9_RCU_USBRESET);
1175 clear_bit (28, AR9_RCU_USBRESET);
1178 #endif //defined(__IS_AR9__)
1179 #if defined(__IS_VR9__)
1182 set_bit (4, VR9_RCU_USBRESET);
1184 clear_bit (4, VR9_RCU_USBRESET);
1187 #endif //defined(__IS_VR9__)
1188 #if defined(__IS_AR10__)
1191 set_bit (4, AR10_RCU_USBRESET);
1193 clear_bit (4, AR10_RCU_USBRESET);
1196 #endif //defined(__IS_AR10__)
1198 #if defined(__IS_TWINPASS__)
1199 ifxusb_enable_afe_oc();
1202 if(_core_if->core_global_regs)
1204 // PHY configurations.
1205 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1206 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
1207 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1208 #if defined(__IS_AMAZON_SE__)
1209 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
1210 #endif //defined(__IS_AMAZON_SE__)
1211 #if defined(__IS_AR9__)
1212 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
1213 #endif //defined(__IS_AR9__)
1214 #if defined(__IS_VR9__)
1215 // ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
1216 #endif //defined(__IS_VR9__)
1217 #if defined(__IS_AR10__)
1218 // ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
1219 #endif //defined(__IS_AR10__)
1221 #else //defined(__UEIP__)
1222 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1223 #if defined (__IS_HOST__)
1224 clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
1225 #elif defined (__IS_DEVICE__)
1226 set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
1228 #endif //defined(__IS_AMAZON_SE__)
1230 #if defined(__IS_AMAZON_SE__)
1231 #if defined (__IS_HOST__)
1232 clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
1233 #elif defined (__IS_DEVICE__)
1234 set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
1236 #endif //defined(__IS_AMAZON_SE__)
1238 #if defined(__IS_AR9__)
1239 if(_core_if->core_no==0)
1241 #if defined (__IS_HOST__)
1242 clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
1243 #elif defined (__IS_DEVICE__)
1244 set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
1249 #if defined (__IS_HOST__)
1250 clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
1251 #elif defined (__IS_DEVICE__)
1252 set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
1255 #endif //defined(__IS_AR9__)
1257 // set the HC's byte-order to big-endian
1258 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1259 set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
1260 clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG);
1261 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1262 #if defined(__IS_AMAZON_SE__)
1263 set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
1264 clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG);
1265 #endif //defined(__IS_AMAZON_SE__)
1266 #if defined(__IS_AR9__)
1267 if(_core_if->core_no==0)
1269 set_bit (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
1270 clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG);
1274 set_bit (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
1275 clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG);
1277 #endif //defined(__IS_AR9__)
1279 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1280 set_bit (4, DANUBE_RCU_RESET);
1281 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1282 #if defined(__IS_AMAZON_SE__)
1283 set_bit (4, AMAZON_SE_RCU_RESET);
1284 #endif //defined(__IS_AMAZON_SE__)
1285 #if defined(__IS_AR9__)
1286 if(_core_if->core_no==0)
1288 set_bit (4, AMAZON_S_RCU_USBRESET);
1292 set_bit (28, AMAZON_S_RCU_USBRESET);
1294 #endif //defined(__IS_AR9__)
1298 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1299 clear_bit (4, DANUBE_RCU_RESET);
1300 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1301 #if defined(__IS_AMAZON_SE__)
1302 clear_bit (4, AMAZON_SE_RCU_RESET);
1303 #endif //defined(__IS_AMAZON_SE__)
1304 #if defined(__IS_AR9__)
1305 if(_core_if->core_no==0)
1307 clear_bit (4, AMAZON_S_RCU_USBRESET);
1311 clear_bit (28, AMAZON_S_RCU_USBRESET);
1313 #endif //defined(__IS_AR9__)
1317 #if defined(__IS_TWINPASS__)
1318 ifxusb_enable_afe_oc();
1321 if(_core_if->core_global_regs)
1323 // PHY configurations.
1324 #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1325 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
1326 #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__)
1327 #if defined(__IS_AMAZON_SE__)
1328 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
1329 #endif //defined(__IS_AMAZON_SE__)
1330 #if defined(__IS_AR9__)
1331 ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014);
1332 #endif //defined(__IS_AR9__)
1334 #endif //defined(__UEIP__)
1337 #if defined(__GADGET_LED__) || defined(__HOST_LED__)
1338 #if defined(__UEIP__)
1339 static void *g_usb_led_trigger = NULL;
1342 void ifxusb_led_init(ifxusb_core_if_t *_core_if)
1344 #if defined(__UEIP__)
1345 #if defined(IFX_LEDGPIO_USB_LED) || defined(IFX_LEDLED_USB_LED)
1346 if ( !g_usb_led_trigger )
1348 ifx_led_trigger_register("usb_link", &g_usb_led_trigger);
1349 if ( g_usb_led_trigger != NULL )
1351 struct ifx_led_trigger_attrib attrib = {0};
1352 attrib.delay_on = 250;
1353 attrib.delay_off = 250;
1354 attrib.timeout = 2000;
1355 attrib.def_value = 1;
1356 attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE;
1357 IFX_DEBUGP("Reg USB LED!!\n");
1358 ifx_led_trigger_set_attrib(g_usb_led_trigger, &attrib);
1362 #endif //defined(__UEIP__)
1365 void ifxusb_led_free(ifxusb_core_if_t *_core_if)
1367 #if defined(__UEIP__)
1368 if ( g_usb_led_trigger )
1370 ifx_led_trigger_deregister(g_usb_led_trigger);
1371 g_usb_led_trigger = NULL;
1373 #endif //defined(__UEIP__)
1377 \brief Turn off the USB 5V VBus Power
1378 \param _core_if Pointer of core_if structure
1380 void ifxusb_led(ifxusb_core_if_t *_core_if)
1382 #if defined(__UEIP__)
1383 if(g_usb_led_trigger)
1384 ifx_led_trigger_activate(g_usb_led_trigger);
1386 #endif //defined(__UEIP__)
1388 #endif // defined(__GADGET_LED__) || defined(__HOST_LED__)
1393 \brief internal routines for debugging
1396 void ifxusb_dump_msg_h(const u8 *buf, unsigned int length)
1398 void ifxusb_dump_msg_d(const u8 *buf, unsigned int length)
1402 unsigned int start, num, i;
1410 num = min(length, 16u);
1412 for (i = 0; i < num; ++i)
1416 sprintf(p, " %02x", buf[i]);
1420 IFX_PRINT( "%6x: %s\n", start, line);
1429 \brief internal routines for debugging, reads the SPRAM and prints its content
1432 void ifxusb_dump_spram_h(ifxusb_core_if_t *_core_if)
1434 void ifxusb_dump_spram_d(ifxusb_core_if_t *_core_if)
1437 #ifdef __ENABLE_DUMP__
1438 volatile uint8_t *addr, *start_addr, *end_addr;
1440 IFX_PRINT("SPRAM Data:\n");
1441 start_addr = (void*)_core_if->core_global_regs;
1442 IFX_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr);
1444 start_addr = (void*)_core_if->data_fifo_dbg;
1445 IFX_PRINT("Starting Address: 0x%8X\n", (uint32_t)start_addr);
1447 size=_core_if->hwcfg3.b.dfifo_depth;
1452 end_addr = (void*)_core_if->data_fifo_dbg;
1455 for(addr = start_addr; addr < end_addr; addr+=16)
1457 IFX_PRINT("0x%8X: %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X \n", (uint32_t)addr,
1458 addr[ 0], addr[ 1], addr[ 2], addr[ 3],
1459 addr[ 4], addr[ 5], addr[ 6], addr[ 7],
1460 addr[ 8], addr[ 9], addr[10], addr[11],
1461 addr[12], addr[13], addr[14], addr[15]
1465 #endif //__ENABLE_DUMP__
1469 \brief internal routines for debugging, reads the core global registers and prints them
1472 void ifxusb_dump_registers_h(ifxusb_core_if_t *_core_if)
1474 void ifxusb_dump_registers_d(ifxusb_core_if_t *_core_if)
1477 #ifdef __ENABLE_DUMP__
1479 volatile uint32_t *addr;
1480 #ifdef __IS_DEVICE__
1481 volatile uint32_t *addri,*addro;
1484 IFX_PRINT("Core #%d\n",_core_if->core_no);
1485 IFX_PRINT("========================================\n");
1486 IFX_PRINT("Core Global Registers\n");
1487 addr=&_core_if->core_global_regs->gotgctl;
1488 IFX_PRINT(" GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1489 addr=&_core_if->core_global_regs->gotgint;
1490 IFX_PRINT(" GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1491 addr=&_core_if->core_global_regs->gahbcfg;
1492 IFX_PRINT(" GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1493 addr=&_core_if->core_global_regs->gusbcfg;
1494 IFX_PRINT(" GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1495 addr=&_core_if->core_global_regs->grstctl;
1496 IFX_PRINT(" GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1497 addr=&_core_if->core_global_regs->gintsts;
1498 IFX_PRINT(" GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1499 addr=&_core_if->core_global_regs->gintmsk;
1500 IFX_PRINT(" GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1501 addr=&_core_if->core_global_regs->gi2cctl;
1502 IFX_PRINT(" GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1503 addr=&_core_if->core_global_regs->gpvndctl;
1504 IFX_PRINT(" GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1505 addr=&_core_if->core_global_regs->ggpio;
1506 IFX_PRINT(" GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1507 addr=&_core_if->core_global_regs->guid;
1508 IFX_PRINT(" GUID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1509 addr=&_core_if->core_global_regs->gsnpsid;
1510 IFX_PRINT(" GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1511 addr=&_core_if->core_global_regs->ghwcfg1;
1512 IFX_PRINT(" GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1513 addr=&_core_if->core_global_regs->ghwcfg2;
1514 IFX_PRINT(" GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1515 addr=&_core_if->core_global_regs->ghwcfg3;
1516 IFX_PRINT(" GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1517 addr=&_core_if->core_global_regs->ghwcfg4;
1518 IFX_PRINT(" GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1520 addr=_core_if->pcgcctl;
1521 IFX_PRINT(" PCGCCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1523 addr=&_core_if->core_global_regs->grxfsiz;
1524 IFX_PRINT(" GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1527 addr=&_core_if->core_global_regs->gnptxfsiz;
1528 IFX_PRINT(" GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1529 addr=&_core_if->core_global_regs->hptxfsiz;
1530 IFX_PRINT(" HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1531 #endif //__IS_HOST__
1533 #ifdef __IS_DEVICE__
1535 addr=&_core_if->core_global_regs->gnptxfsiz;
1536 IFX_PRINT(" GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1537 for (i=0; i<= _core_if->hwcfg4.b.num_in_eps; i++)
1539 addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i];
1540 IFX_PRINT(" DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,ifxusb_rreg(addr));
1543 addr=&_core_if->core_global_regs->gnptxfsiz;
1544 IFX_PRINT(" TXFSIZ[00] @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1545 for (i=0; i< _core_if->hwcfg4.b.num_dev_perio_in_ep; i++)
1547 addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i];
1548 IFX_PRINT(" TXFSIZ[%02d] @0x%08X : 0x%08X\n",i+1,(uint32_t)addr,ifxusb_rreg(addr));
1551 #endif //__IS_DEVICE__
1554 IFX_PRINT(" Host Global Registers\n");
1555 addr=&_core_if->host_global_regs->hcfg;
1556 IFX_PRINT(" HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1557 addr=&_core_if->host_global_regs->hfir;
1558 IFX_PRINT(" HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1559 addr=&_core_if->host_global_regs->hfnum;
1560 IFX_PRINT(" HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1561 addr=&_core_if->host_global_regs->hptxsts;
1562 IFX_PRINT(" HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1563 addr=&_core_if->host_global_regs->haint;
1564 IFX_PRINT(" HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1565 addr=&_core_if->host_global_regs->haintmsk;
1566 IFX_PRINT(" HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1567 addr= _core_if->hprt0;
1568 IFX_PRINT(" HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1570 for (i=0; i<MAX_EPS_CHANNELS; i++)
1572 addr=&_core_if->hc_regs[i]->hcchar;
1573 IFX_PRINT(" Host Channel %d Specific Registers\n", i);
1574 IFX_PRINT(" HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1575 addr=&_core_if->hc_regs[i]->hcsplt;
1576 IFX_PRINT(" HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1577 addr=&_core_if->hc_regs[i]->hcint;
1578 IFX_PRINT(" HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1579 addr=&_core_if->hc_regs[i]->hcintmsk;
1580 IFX_PRINT(" HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1581 addr=&_core_if->hc_regs[i]->hctsiz;
1582 IFX_PRINT(" HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1583 addr=&_core_if->hc_regs[i]->hcdma;
1584 IFX_PRINT(" HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1586 #endif //__IS_HOST__
1588 #ifdef __IS_DEVICE__
1589 IFX_PRINT(" Device Global Registers\n");
1590 addr=&_core_if->dev_global_regs->dcfg;
1591 IFX_PRINT(" DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1592 addr=&_core_if->dev_global_regs->dctl;
1593 IFX_PRINT(" DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1594 addr=&_core_if->dev_global_regs->dsts;
1595 IFX_PRINT(" DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1596 addr=&_core_if->dev_global_regs->diepmsk;
1597 IFX_PRINT(" DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1598 addr=&_core_if->dev_global_regs->doepmsk;
1599 IFX_PRINT(" DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1600 addr=&_core_if->dev_global_regs->daintmsk;
1601 IFX_PRINT(" DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1602 addr=&_core_if->dev_global_regs->daint;
1603 IFX_PRINT(" DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1604 addr=&_core_if->dev_global_regs->dvbusdis;
1605 IFX_PRINT(" DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1606 addr=&_core_if->dev_global_regs->dvbuspulse;
1607 IFX_PRINT(" DVBUSPULS @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr));
1609 addr=&_core_if->dev_global_regs->dtknqr1;
1610 IFX_PRINT(" DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr));
1611 if (_core_if->hwcfg2.b.dev_token_q_depth > 6) {
1612 addr=&_core_if->dev_global_regs->dtknqr2;
1613 IFX_PRINT(" DTKNQR2 @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr));
1616 if (_core_if->hwcfg2.b.dev_token_q_depth > 14)
1618 addr=&_core_if->dev_global_regs->dtknqr3_dthrctl;
1619 IFX_PRINT(" DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr));
1622 if (_core_if->hwcfg2.b.dev_token_q_depth > 22)
1624 addr=&_core_if->dev_global_regs->dtknqr4_fifoemptymsk;
1625 IFX_PRINT(" DTKNQR4 @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr));
1628 //for (i=0; i<= MAX_EPS_CHANNELS; i++)
1629 //for (i=0; i<= 10; i++)
1630 for (i=0; i<= 3; i++)
1632 IFX_PRINT(" Device EP %d Registers\n", i);
1633 addri=&_core_if->in_ep_regs[i]->diepctl;addro=&_core_if->out_ep_regs[i]->doepctl;
1634 IFX_PRINT(" DEPCTL I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
1635 addro=&_core_if->out_ep_regs[i]->doepfn;
1636 IFX_PRINT(" DEPFN I: O: 0x%08X\n",ifxusb_rreg(addro));
1637 addri=&_core_if->in_ep_regs[i]->diepint;addro=&_core_if->out_ep_regs[i]->doepint;
1638 IFX_PRINT(" DEPINT I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
1639 addri=&_core_if->in_ep_regs[i]->dieptsiz;addro=&_core_if->out_ep_regs[i]->doeptsiz;
1640 IFX_PRINT(" DETSIZ I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
1641 addri=&_core_if->in_ep_regs[i]->diepdma;addro=&_core_if->out_ep_regs[i]->doepdma;
1642 IFX_PRINT(" DEPDMA I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
1643 addri=&_core_if->in_ep_regs[i]->dtxfsts;
1644 IFX_PRINT(" DTXFSTS I: 0x%08X\n",ifxusb_rreg(addri) );
1645 addri=&_core_if->in_ep_regs[i]->diepdmab;addro=&_core_if->out_ep_regs[i]->doepdmab;
1646 IFX_PRINT(" DEPDMAB I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro));
1648 #endif //__IS_DEVICE__
1649 #endif //__ENABLE_DUMP__
1653 void do_suspend_h(ifxusb_core_if_t *core_if)
1655 ifxusb_vbus_off(core_if);
1657 ifxusb_power_off_h(core_if);
1659 void do_resume_h(ifxusb_core_if_t *core_if)
1661 ifxusb_vbus_on(core_if);
1663 ifxusb_power_on_h(core_if);
1664 ifxusb_phy_power_on_h(core_if);
1667 #ifdef __IS_DEVICE__
1668 void do_suspend_d(ifxusb_core_if_t *core_if)
1670 ifxusb_power_off_d(core_if);
1672 void do_resume_d(ifxusb_core_if_t *core_if)
1674 dctl_data_t dctl = {.d32=0};
1676 ifxusb_power_on_d(core_if);
1677 ifxusb_phy_power_on_d(core_if);
1678 dctl.d32=ifxusb_rreg(&core_if->dev_global_regs->dctl);
1680 ifxusb_wreg(&core_if->dev_global_regs->dctl,dctl.d32);
1683 ifxusb_wreg(&core_if->dev_global_regs->dctl,dctl.d32);