package/mac80211/patches/319-rt2x00-More-register-fixes-rt2800pci.patch

   1 From de75c463ca06352ac36c4a28440d10d5523bd6d9 Mon Sep 17 00:00:00 2001
   2 From: Ivo van Doorn <IvDoorn@gmail.com>
   3 Date: Sat, 17 Jan 2009 20:27:10 +0100
   4 Subject: [PATCH] rt2x00: More register fixes (rt2800pci)
   5
   6 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
   7 ---
   8  drivers/net/wireless/rt2x00/rt2800pci.c |   59 +++++++++++++++----------------
   9  drivers/net/wireless/rt2x00/rt2800pci.h |    8 ++--
  10  2 files changed, 33 insertions(+), 34 deletions(-)
  11
  12 --- a/drivers/net/wireless/rt2x00/rt2800pci.c
  13 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
  14 @@ -2506,33 +2506,34 @@ static int rt2800pci_set_rts_threshold(s
  15  {
  16         struct rt2x00_dev *rt2x00dev = hw->priv;
  17         u32 reg;
  18 +       bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
  19
  20         rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
  21         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
  22         rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
  23
  24         rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
  25 -       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
  26 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
  27         rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
  28
  29         rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  30 -       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
  31 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
  32         rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  33
  34         rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
  35 -       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
  36 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
  37         rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
  38
  39         rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
  40 -       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
  41 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
  42         rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
  43
  44         rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
  45 -       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
  46 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
  47         rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
  48
  49         rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
  50 -       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
  51 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
  52         rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
  53
  54         return 0;
  55 @@ -2558,24 +2559,23 @@ static int rt2800pci_conf_tx(struct ieee
  56         if (retval)
  57                 return retval;
  58
  59 +       /*
  60 +        * We only need to perform additional register initialization
  61 +        * for WMM queues/
  62 +        */
  63 +       if (queue_idx >= 4)
  64 +               return 0;
  65 +
  66         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
  67
  68         /* Update WMM TXOP register */
  69 -       if (queue_idx < 2) {
  70 -               field.bit_offset = queue_idx * 16;
  71 -               field.bit_mask = 0xffff << field.bit_offset;
  72 -
  73 -               rt2x00pci_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
  74 -               rt2x00_set_field32(&reg, field, queue->txop);
  75 -               rt2x00pci_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
  76 -       } else if (queue_idx < 4) {
  77 -               field.bit_offset = (queue_idx - 2) * 16;
  78 -               field.bit_mask = 0xffff << field.bit_offset;
  79 -
  80 -               rt2x00pci_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
  81 -               rt2x00_set_field32(&reg, field, queue->txop);
  82 -               rt2x00pci_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
  83 -       }
  84 +       offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
  85 +       field.bit_offset = (queue_idx & 1) * 16;
  86 +       field.bit_mask = 0xffff << field.bit_offset;
  87 +
  88 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
  89 +       rt2x00_set_field32(&reg, field, queue->txop);
  90 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
  91
  92         /* Update WMM registers */
  93         field.bit_offset = queue_idx * 4;
  94 @@ -2594,15 +2594,14 @@ static int rt2800pci_conf_tx(struct ieee
  95         rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
  96
  97         /* Update EDCA registers */
  98 -       if (queue_idx < 4) {
  99 -               offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
 100 +       offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
 101
 102 -               rt2x00pci_register_read(rt2x00dev, offset, &reg);
 103 -               rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
 104 -               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
 105 -               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
 106 -               rt2x00pci_register_write(rt2x00dev, offset, reg);
 107 -       }
 108 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
 109 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
 110 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
 111 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
 112 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
 113 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 114
 115         return 0;
 116  }
 117 --- a/drivers/net/wireless/rt2x00/rt2800pci.h
 118 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
 119 @@ -667,7 +667,7 @@
 120   * EDCA_AC0_CFG:
 121   */
 122  #define EDCA_AC0_CFG                   0x1300
 123 -#define EDCA_AC0_CFG_AC_TX_OP          FIELD32(0x000000ff)
 124 +#define EDCA_AC0_CFG_TX_OP             FIELD32(0x000000ff)
 125  #define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
 126  #define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
 127  #define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
 128 @@ -676,7 +676,7 @@
 129   * EDCA_AC1_CFG:
 130   */
 131  #define EDCA_AC1_CFG                   0x1304
 132 -#define EDCA_AC1_CFG_AC_TX_OP          FIELD32(0x000000ff)
 133 +#define EDCA_AC1_CFG_TX_OP             FIELD32(0x000000ff)
 134  #define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
 135  #define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
 136  #define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
 137 @@ -685,7 +685,7 @@
 138   * EDCA_AC2_CFG:
 139   */
 140  #define EDCA_AC2_CFG                   0x1308
 141 -#define EDCA_AC2_CFG_AC_TX_OP          FIELD32(0x000000ff)
 142 +#define EDCA_AC2_CFG_TX_OP             FIELD32(0x000000ff)
 143  #define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
 144  #define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
 145  #define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
 146 @@ -694,7 +694,7 @@
 147   * EDCA_AC3_CFG:
 148   */
 149  #define EDCA_AC3_CFG                   0x130c
 150 -#define EDCA_AC3_CFG_AC_TX_OP          FIELD32(0x000000ff)
 151 +#define EDCA_AC3_CFG_TX_OP             FIELD32(0x000000ff)
 152  #define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
 153  #define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
 154  #define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)