package/mac80211/patches/303-rt2x00-Implement-support-for-rt2800usb.patch

   1 From b249bc450f982cd2491448c91faf797ed37b69b8 Mon Sep 17 00:00:00 2001
   2 From: Ivo van Doorn <IvDoorn@gmail.com>
   3 Date: Tue, 3 Mar 2009 19:25:49 +0100
   4 Subject: [PATCH] rt2x00: Implement support for rt2800usb
   5
   6 Add support for the rt2800usb chipset.
   7
   8 Includes various patches from Mattias, Felix, Xose and Axel.
   9
  10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
  11 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  12 Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
  13 Signed-off-by: Axel Kollhofer <rain_maker@root-forum.org>
  14 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
  15 ---
  16  drivers/net/wireless/rt2x00/Kconfig     |   14 +
  17  drivers/net/wireless/rt2x00/Makefile    |    1 +
  18  drivers/net/wireless/rt2x00/rt2800usb.c | 3032 +++++++++++++++++++++++++++++++
  19  drivers/net/wireless/rt2x00/rt2800usb.h | 1932 ++++++++++++++++++++
  20  drivers/net/wireless/rt2x00/rt2x00.h    |    7 +
  21  5 files changed, 4986 insertions(+), 0 deletions(-)
  22  create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.c
  23  create mode 100644 drivers/net/wireless/rt2x00/rt2800usb.h
  24
  25  config RT2X00_LIB_PCI
  26         tristate
  27         select RT2X00_LIB
  28 --- a/drivers/net/wireless/rt2x00/Makefile
  29 +++ b/drivers/net/wireless/rt2x00/Makefile
  30 @@ -19,3 +19,4 @@ obj-$(CONFIG_RT61PCI)                 += rt61pci.o
  31  obj-$(CONFIG_RT2800PCI)                        += rt2800pci.o
  32  obj-$(CONFIG_RT2500USB)                        += rt2500usb.o
  33  obj-$(CONFIG_RT73USB)                  += rt73usb.o
  34 +obj-$(CONFIG_RT2800USB)                        += rt2800usb.o
  35 --- /dev/null
  36 +++ b/drivers/net/wireless/rt2x00/rt2800usb.c
  37 @@ -0,0 +1,3032 @@
  38 +/*
  39 +       Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
  40 +       <http://rt2x00.serialmonkey.com>
  41 +
  42 +       This program is free software; you can redistribute it and/or modify
  43 +       it under the terms of the GNU General Public License as published by
  44 +       the Free Software Foundation; either version 2 of the License, or
  45 +       (at your option) any later version.
  46 +
  47 +       This program is distributed in the hope that it will be useful,
  48 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
  49 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  50 +       GNU General Public License for more details.
  51 +
  52 +       You should have received a copy of the GNU General Public License
  53 +       along with this program; if not, write to the
  54 +       Free Software Foundation, Inc.,
  55 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  56 + */
  57 +
  58 +/*
  59 +       Module: rt2800usb
  60 +       Abstract: rt2800usb device specific routines.
  61 +       Supported chipsets: RT2800U.
  62 + */
  63 +
  64 +#include <linux/crc-ccitt.h>
  65 +#include <linux/delay.h>
  66 +#include <linux/etherdevice.h>
  67 +#include <linux/init.h>
  68 +#include <linux/kernel.h>
  69 +#include <linux/module.h>
  70 +#include <linux/usb.h>
  71 +
  72 +#include "rt2x00.h"
  73 +#include "rt2x00usb.h"
  74 +#include "rt2800usb.h"
  75 +
  76 +/*
  77 + * Allow hardware encryption to be disabled.
  78 + */
  79 +static int modparam_nohwcrypt = 0;
  80 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  81 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  82 +
  83 +/*
  84 + * Register access.
  85 + * All access to the CSR registers will go through the methods
  86 + * rt2x00usb_register_read and rt2x00usb_register_write.
  87 + * BBP and RF register require indirect register access,
  88 + * and use the CSR registers BBPCSR and RFCSR to achieve this.
  89 + * These indirect registers work with busy bits,
  90 + * and we will try maximal REGISTER_BUSY_COUNT times to access
  91 + * the register while taking a REGISTER_BUSY_DELAY us delay
  92 + * between each attampt. When the busy bit is still set at that time,
  93 + * the access attempt is considered to have failed,
  94 + * and we will print an error.
  95 + * The _lock versions must be used if you already hold the csr_mutex
  96 + */
  97 +#define WAIT_FOR_BBP(__dev, __reg) \
  98 +       rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  99 +#define WAIT_FOR_RFCSR(__dev, __reg) \
 100 +       rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
 101 +#define WAIT_FOR_RF(__dev, __reg) \
 102 +       rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
 103 +#define WAIT_FOR_MCU(__dev, __reg) \
 104 +       rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
 105 +                              H2M_MAILBOX_CSR_OWNER, (__reg))
 106 +
 107 +static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
 108 +                               const unsigned int word, const u8 value)
 109 +{
 110 +       u32 reg;
 111 +
 112 +       mutex_lock(&rt2x00dev->csr_mutex);
 113 +
 114 +       /*
 115 +        * Wait until the BBP becomes available, afterwards we
 116 +        * can safely write the new data into the register.
 117 +        */
 118 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 119 +               reg = 0;
 120 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 121 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 122 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 123 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 124 +
 125 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 126 +       }
 127 +
 128 +       mutex_unlock(&rt2x00dev->csr_mutex);
 129 +}
 130 +
 131 +static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
 132 +                              const unsigned int word, u8 *value)
 133 +{
 134 +       u32 reg;
 135 +
 136 +       mutex_lock(&rt2x00dev->csr_mutex);
 137 +
 138 +       /*
 139 +        * Wait until the BBP becomes available, afterwards we
 140 +        * can safely write the read request into the register.
 141 +        * After the data has been written, we wait until hardware
 142 +        * returns the correct value, if at any time the register
 143 +        * doesn't become available in time, reg will be 0xffffffff
 144 +        * which means we return 0xff to the caller.
 145 +        */
 146 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 147 +               reg = 0;
 148 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 149 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 150 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 151 +
 152 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 153 +
 154 +               WAIT_FOR_BBP(rt2x00dev, &reg);
 155 +       }
 156 +
 157 +       *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 158 +
 159 +       mutex_unlock(&rt2x00dev->csr_mutex);
 160 +}
 161 +
 162 +static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 163 +                                 const unsigned int word, const u8 value)
 164 +{
 165 +       u32 reg;
 166 +
 167 +       mutex_lock(&rt2x00dev->csr_mutex);
 168 +
 169 +       /*
 170 +        * Wait until the RFCSR becomes available, afterwards we
 171 +        * can safely write the new data into the register.
 172 +        */
 173 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 174 +               reg = 0;
 175 +               rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 176 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 177 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 178 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 179 +
 180 +               rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 181 +       }
 182 +
 183 +       mutex_unlock(&rt2x00dev->csr_mutex);
 184 +}
 185 +
 186 +static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 187 +                                const unsigned int word, u8 *value)
 188 +{
 189 +       u32 reg;
 190 +
 191 +       mutex_lock(&rt2x00dev->csr_mutex);
 192 +
 193 +       /*
 194 +        * Wait until the RFCSR becomes available, afterwards we
 195 +        * can safely write the read request into the register.
 196 +        * After the data has been written, we wait until hardware
 197 +        * returns the correct value, if at any time the register
 198 +        * doesn't become available in time, reg will be 0xffffffff
 199 +        * which means we return 0xff to the caller.
 200 +        */
 201 +       if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 202 +               reg = 0;
 203 +               rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 204 +               rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 205 +               rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 206 +
 207 +               rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 208 +
 209 +               WAIT_FOR_RFCSR(rt2x00dev, &reg);
 210 +       }
 211 +
 212 +       *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 213 +
 214 +       mutex_unlock(&rt2x00dev->csr_mutex);
 215 +}
 216 +
 217 +static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
 218 +                              const unsigned int word, const u32 value)
 219 +{
 220 +       u32 reg;
 221 +
 222 +       mutex_lock(&rt2x00dev->csr_mutex);
 223 +
 224 +       /*
 225 +        * Wait until the RF becomes available, afterwards we
 226 +        * can safely write the new data into the register.
 227 +        */
 228 +       if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 229 +               reg = 0;
 230 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 231 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 232 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 233 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 234 +
 235 +               rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 236 +               rt2x00_rf_write(rt2x00dev, word, value);
 237 +       }
 238 +
 239 +       mutex_unlock(&rt2x00dev->csr_mutex);
 240 +}
 241 +
 242 +static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
 243 +                                 const u8 command, const u8 token,
 244 +                                 const u8 arg0, const u8 arg1)
 245 +{
 246 +       u32 reg;
 247 +
 248 +       mutex_lock(&rt2x00dev->csr_mutex);
 249 +
 250 +       /*
 251 +        * Wait until the MCU becomes available, afterwards we
 252 +        * can safely write the new data into the register.
 253 +        */
 254 +       if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 255 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 256 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 257 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 258 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 259 +               rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 260 +
 261 +               reg = 0;
 262 +               rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 263 +               rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 264 +       }
 265 +
 266 +       mutex_unlock(&rt2x00dev->csr_mutex);
 267 +}
 268 +
 269 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 270 +static const struct rt2x00debug rt2800usb_rt2x00debug = {
 271 +       .owner  = THIS_MODULE,
 272 +       .csr    = {
 273 +               .read           = rt2x00usb_register_read,
 274 +               .write          = rt2x00usb_register_write,
 275 +               .flags          = RT2X00DEBUGFS_OFFSET,
 276 +               .word_base      = CSR_REG_BASE,
 277 +               .word_size      = sizeof(u32),
 278 +               .word_count     = CSR_REG_SIZE / sizeof(u32),
 279 +       },
 280 +       .eeprom = {
 281 +               .read           = rt2x00_eeprom_read,
 282 +               .write          = rt2x00_eeprom_write,
 283 +               .word_base      = EEPROM_BASE,
 284 +               .word_size      = sizeof(u16),
 285 +               .word_count     = EEPROM_SIZE / sizeof(u16),
 286 +       },
 287 +       .bbp    = {
 288 +               .read           = rt2800usb_bbp_read,
 289 +               .write          = rt2800usb_bbp_write,
 290 +               .word_base      = BBP_BASE,
 291 +               .word_size      = sizeof(u8),
 292 +               .word_count     = BBP_SIZE / sizeof(u8),
 293 +       },
 294 +       .rf     = {
 295 +               .read           = rt2x00_rf_read,
 296 +               .write          = rt2800usb_rf_write,
 297 +               .word_base      = RF_BASE,
 298 +               .word_size      = sizeof(u32),
 299 +               .word_count     = RF_SIZE / sizeof(u32),
 300 +       },
 301 +};
 302 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 303 +
 304 +#ifdef CONFIG_RT2X00_LIB_RFKILL
 305 +static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 306 +{
 307 +       u32 reg;
 308 +
 309 +       rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 310 +       return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 311 +}
 312 +#else
 313 +#define rt2800usb_rfkill_poll  NULL
 314 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
 315 +
 316 +#ifdef CONFIG_RT2X00_LIB_LEDS
 317 +static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
 318 +                                    enum led_brightness brightness)
 319 +{
 320 +       struct rt2x00_led *led =
 321 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 322 +       unsigned int enabled = brightness != LED_OFF;
 323 +       unsigned int bg_mode =
 324 +           (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 325 +       unsigned int polarity =
 326 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 327 +                                  EEPROM_FREQ_LED_POLARITY);
 328 +       unsigned int ledmode =
 329 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 330 +                                  EEPROM_FREQ_LED_MODE);
 331 +
 332 +       if (led->type == LED_TYPE_RADIO) {
 333 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 334 +                                     enabled ? 0x20 : 0);
 335 +       } else if (led->type == LED_TYPE_ASSOC) {
 336 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 337 +                                     enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 338 +       } else if (led->type == LED_TYPE_QUALITY) {
 339 +               /*
 340 +                * The brightness is divided into 6 levels (0 - 5),
 341 +                * The specs tell us the following levels:
 342 +                *      0, 1 ,3, 7, 15, 31
 343 +                * to determine the level in a simple way we can simply
 344 +                * work with bitshifting:
 345 +                *      (1 << level) - 1
 346 +                */
 347 +               rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 348 +                                     (1 << brightness / (LED_FULL / 6)) - 1,
 349 +                                     polarity);
 350 +       }
 351 +}
 352 +
 353 +static int rt2800usb_blink_set(struct led_classdev *led_cdev,
 354 +                              unsigned long *delay_on,
 355 +                              unsigned long *delay_off)
 356 +{
 357 +       struct rt2x00_led *led =
 358 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 359 +       u32 reg;
 360 +
 361 +       rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
 362 +       rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 363 +       rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 364 +       rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 365 +       rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 366 +       rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 367 +       rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 368 +       rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 369 +       rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
 370 +
 371 +       return 0;
 372 +}
 373 +
 374 +static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
 375 +                              struct rt2x00_led *led,
 376 +                              enum led_type type)
 377 +{
 378 +       led->rt2x00dev = rt2x00dev;
 379 +       led->type = type;
 380 +       led->led_dev.brightness_set = rt2800usb_brightness_set;
 381 +       led->led_dev.blink_set = rt2800usb_blink_set;
 382 +       led->flags = LED_INITIALIZED;
 383 +}
 384 +#endif /* CONFIG_RT2X00_LIB_LEDS */
 385 +
 386 +/*
 387 + * Configuration handlers.
 388 + */
 389 +static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 390 +                                      struct rt2x00lib_crypto *crypto,
 391 +                                      struct ieee80211_key_conf *key)
 392 +{
 393 +       struct mac_wcid_entry wcid_entry;
 394 +       struct mac_iveiv_entry iveiv_entry;
 395 +       u32 offset;
 396 +       u32 reg;
 397 +
 398 +       offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 399 +
 400 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
 401 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 402 +                          !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 403 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, crypto->cipher);
 404 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 405 +                          (crypto->cmd == SET_KEY) * crypto->bssidx);
 406 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
 407 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
 408 +
 409 +       offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 410 +
 411 +       memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 412 +       if ((crypto->cipher == CIPHER_TKIP) ||
 413 +           (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 414 +           (crypto->cipher == CIPHER_AES))
 415 +               iveiv_entry.iv[3] |= 0x20;
 416 +       iveiv_entry.iv[3] |= key->keyidx << 6;
 417 +       rt2x00usb_register_multiwrite(rt2x00dev, offset,
 418 +                                     &iveiv_entry, sizeof(iveiv_entry));
 419 +
 420 +       offset = MAC_WCID_ENTRY(key->hw_key_idx);
 421 +
 422 +       memset(&wcid_entry, 0, sizeof(wcid_entry));
 423 +       if (crypto->cmd == SET_KEY)
 424 +               memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 425 +       rt2x00usb_register_multiwrite(rt2x00dev, offset,
 426 +                                     &wcid_entry, sizeof(wcid_entry));
 427 +}
 428 +
 429 +static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 430 +                                      struct rt2x00lib_crypto *crypto,
 431 +                                      struct ieee80211_key_conf *key)
 432 +{
 433 +       struct hw_key_entry key_entry;
 434 +       struct rt2x00_field32 field;
 435 +       int timeout;
 436 +       u32 offset;
 437 +       u32 reg;
 438 +
 439 +       if (crypto->cmd == SET_KEY) {
 440 +               key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 441 +
 442 +               memcpy(key_entry.key, crypto->key,
 443 +                      sizeof(key_entry.key));
 444 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 445 +                      sizeof(key_entry.tx_mic));
 446 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 447 +                      sizeof(key_entry.rx_mic));
 448 +
 449 +               offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 450 +               timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 451 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 452 +                                                   USB_VENDOR_REQUEST_OUT,
 453 +                                                   offset, &key_entry,
 454 +                                                   sizeof(key_entry),
 455 +                                                   timeout);
 456 +       }
 457 +
 458 +       /*
 459 +        * The cipher types are stored over multiple registers
 460 +        * starting with SHARED_KEY_MODE_BASE each word will have
 461 +        * 32 bits and contains the cipher types for 2 bssidx each.
 462 +        * Using the correct defines correctly will cause overhead,
 463 +        * so just calculate the correct offset.
 464 +        */
 465 +       field.bit_offset = (4 * key->keyidx) + (16 * (crypto->bssidx & 1));
 466 +       field.bit_mask = 0x7 << field.bit_offset;
 467 +
 468 +       offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 2);
 469 +
 470 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
 471 +       rt2x00_set_field32(&reg, field,
 472 +                          (crypto->cmd == SET_KEY) * crypto->cipher);
 473 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
 474 +
 475 +       /*
 476 +        * Update WCID information
 477 +        */
 478 +       rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 479 +
 480 +       return 0;
 481 +}
 482 +
 483 +static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 484 +                                        struct rt2x00lib_crypto *crypto,
 485 +                                        struct ieee80211_key_conf *key)
 486 +{
 487 +       struct hw_key_entry key_entry;
 488 +       int timeout;
 489 +       u32 offset;
 490 +
 491 +       if (crypto->cmd == SET_KEY) {
 492 +               /*
 493 +                * 1 pairwise key is possible per AID, this means that the AID
 494 +                * equals our hw_key_idx.
 495 +                */
 496 +               key->hw_key_idx = crypto->aid;
 497 +
 498 +               memcpy(key_entry.key, crypto->key,
 499 +                      sizeof(key_entry.key));
 500 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 501 +                      sizeof(key_entry.tx_mic));
 502 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 503 +                      sizeof(key_entry.rx_mic));
 504 +
 505 +               offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 506 +               timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 507 +               rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 508 +                                                   USB_VENDOR_REQUEST_OUT,
 509 +                                                   offset, &key_entry,
 510 +                                                   sizeof(key_entry),
 511 +                                                   timeout);
 512 +       }
 513 +
 514 +       /*
 515 +        * Update WCID information
 516 +        */
 517 +       rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 518 +
 519 +       return 0;
 520 +}
 521 +
 522 +static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
 523 +                                   const unsigned int filter_flags)
 524 +{
 525 +       u32 reg;
 526 +
 527 +       /*
 528 +        * Start configuration steps.
 529 +        * Note that the version error will always be dropped
 530 +        * and broadcast frames will always be accepted since
 531 +        * there is no filter for it at this time.
 532 +        */
 533 +       rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 534 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 535 +                          !(filter_flags & FIF_FCSFAIL));
 536 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 537 +                          !(filter_flags & FIF_PLCPFAIL));
 538 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 539 +                          !(filter_flags & FIF_PROMISC_IN_BSS));
 540 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 541 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 542 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 543 +                          !(filter_flags & FIF_ALLMULTI));
 544 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 545 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 546 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 547 +                          !(filter_flags & FIF_CONTROL));
 548 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 549 +                          !(filter_flags & FIF_CONTROL));
 550 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 551 +                          !(filter_flags & FIF_CONTROL));
 552 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 553 +                          !(filter_flags & FIF_CONTROL));
 554 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 555 +                          !(filter_flags & FIF_CONTROL));
 556 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 557 +                          !(filter_flags & FIF_CONTROL));
 558 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 559 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 560 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 561 +                          !(filter_flags & FIF_CONTROL));
 562 +       rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 563 +}
 564 +
 565 +static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
 566 +                                 struct rt2x00_intf *intf,
 567 +                                 struct rt2x00intf_conf *conf,
 568 +                                 const unsigned int flags)
 569 +{
 570 +       unsigned int beacon_base;
 571 +       u32 reg;
 572 +
 573 +       if (flags & CONFIG_UPDATE_TYPE) {
 574 +               /*
 575 +                * Clear current synchronisation setup.
 576 +                * For the Beacon base registers we only need to clear
 577 +                * the first byte since that byte contains the VALID and OWNER
 578 +                * bits which (when set to 0) will invalidate the entire beacon.
 579 +                */
 580 +               beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 581 +               rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
 582 +
 583 +               /*
 584 +                * Enable synchronisation.
 585 +                */
 586 +               rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 587 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 588 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 589 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 590 +               rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 591 +       }
 592 +
 593 +       if (flags & CONFIG_UPDATE_MAC) {
 594 +               reg = le32_to_cpu(conf->mac[1]);
 595 +               rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 596 +               conf->mac[1] = cpu_to_le32(reg);
 597 +
 598 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 599 +                                             conf->mac, sizeof(conf->mac));
 600 +       }
 601 +
 602 +       if (flags & CONFIG_UPDATE_BSSID) {
 603 +               reg = le32_to_cpu(conf->bssid[1]);
 604 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 605 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 606 +               conf->bssid[1] = cpu_to_le32(reg);
 607 +
 608 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 609 +                                             conf->bssid, sizeof(conf->bssid));
 610 +       }
 611 +}
 612 +
 613 +static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
 614 +                                struct rt2x00lib_erp *erp)
 615 +{
 616 +       u32 reg;
 617 +
 618 +       rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 619 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
 620 +                          DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
 621 +       rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 622 +
 623 +       rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 624 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 625 +                          !!erp->short_preamble);
 626 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 627 +                          !!erp->short_preamble);
 628 +       rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 629 +
 630 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 631 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 632 +                          erp->cts_protection ? 2 : 0);
 633 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 634 +
 635 +       rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 636 +                                erp->basic_rates);
 637 +       rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 638 +
 639 +       rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 640 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 641 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 642 +       rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 643 +
 644 +       rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 645 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 646 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 647 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 648 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 649 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 650 +       rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 651 +}
 652 +
 653 +static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
 654 +                                struct antenna_setup *ant)
 655 +{
 656 +       u16 eeprom;
 657 +       u8 r1;
 658 +       u8 r3;
 659 +
 660 +       /*
 661 +        * FIXME: Use requested antenna configuration.
 662 +        */
 663 +
 664 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 665 +
 666 +       rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 667 +       rt2800usb_bbp_read(rt2x00dev, 3, &r3);
 668 +
 669 +       /*
 670 +        * Configure the TX antenna.
 671 +        */
 672 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
 673 +       case 1:
 674 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 675 +               break;
 676 +       case 2:
 677 +               rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 678 +               break;
 679 +       case 3:
 680 +               /* Do nothing */
 681 +               break;
 682 +       }
 683 +
 684 +       /*
 685 +        * Configure the RX antenna.
 686 +        */
 687 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
 688 +       case 1:
 689 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 690 +               break;
 691 +       case 2:
 692 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 693 +               break;
 694 +       case 3:
 695 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 696 +               break;
 697 +       }
 698 +
 699 +       rt2800usb_bbp_write(rt2x00dev, 3, r3);
 700 +       rt2800usb_bbp_write(rt2x00dev, 1, r1);
 701 +}
 702 +
 703 +static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 704 +                                     struct rt2x00lib_conf *libconf)
 705 +{
 706 +       u16 eeprom;
 707 +       short lna_gain;
 708 +
 709 +       if (libconf->rf.channel <= 14) {
 710 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 711 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 712 +       } else if (libconf->rf.channel <= 64) {
 713 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 714 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 715 +       } else if (libconf->rf.channel <= 128) {
 716 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 717 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 718 +       } else {
 719 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 720 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 721 +       }
 722 +
 723 +       rt2x00dev->lna_gain = lna_gain;
 724 +}
 725 +
 726 +static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 727 +                                         struct ieee80211_conf *conf,
 728 +                                         struct rf_channel *rf,
 729 +                                         struct channel_info *info)
 730 +{
 731 +       u16 eeprom;
 732 +
 733 +       rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 734 +
 735 +       /*
 736 +        * Determine antenna settings from EEPROM
 737 +        */
 738 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 739 +
 740 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
 741 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 742 +
 743 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
 744 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 745 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 746 +       } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
 747 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 748 +
 749 +       if (rf->channel > 14) {
 750 +               /*
 751 +                * When TX power is below 0, we should increase it by 7 to
 752 +                * make it a positive value (Minumum value is -7).
 753 +                * However this means that values between 0 and 7 have
 754 +                * double meaning, and we should set a 7DBm boost flag.
 755 +                */
 756 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 757 +                                  (info->tx_power1 >= 0));
 758 +
 759 +               if (info->tx_power1 < 0)
 760 +                       info->tx_power1 += 7;
 761 +
 762 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 763 +                                  TXPOWER_A_TO_DEV(info->tx_power1));
 764 +
 765 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 766 +                                  (info->tx_power2 >= 0));
 767 +
 768 +               if (info->tx_power2 < 0)
 769 +                       info->tx_power2 += 7;
 770 +
 771 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 772 +                                  TXPOWER_A_TO_DEV(info->tx_power2));
 773 +       } else {
 774 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 775 +                                  TXPOWER_G_TO_DEV(info->tx_power1));
 776 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 777 +                                  TXPOWER_G_TO_DEV(info->tx_power2));
 778 +       }
 779 +
 780 +       rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 781 +
 782 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 783 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 784 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 785 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 786 +
 787 +       udelay(200);
 788 +
 789 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 790 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 791 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 792 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 793 +
 794 +       udelay(200);
 795 +
 796 +       rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 797 +       rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 798 +       rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 799 +       rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 800 +}
 801 +
 802 +static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 803 +                                         struct ieee80211_conf *conf,
 804 +                                         struct rf_channel *rf,
 805 +                                         struct channel_info *info)
 806 +{
 807 +       u8 rfcsr;
 808 +
 809 +       rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
 810 +       rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
 811 +
 812 +       rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
 813 +       rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 814 +       rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
 815 +
 816 +       rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
 817 +       rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 818 +                         TXPOWER_G_TO_DEV(info->tx_power1));
 819 +       rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
 820 +
 821 +       rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 822 +       rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 823 +       rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 824 +
 825 +       if (conf_is_ht40(conf))
 826 +               rt2800usb_rfcsr_write(rt2x00dev, 24,
 827 +                                     rt2x00dev->calibration_bw40);
 828 +       else
 829 +               rt2800usb_rfcsr_write(rt2x00dev, 24,
 830 +                                     rt2x00dev->calibration_bw20);
 831 +
 832 +       rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 833 +       rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 834 +       rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 835 +}
 836 +
 837 +static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
 838 +                                    struct ieee80211_conf *conf,
 839 +                                    struct rf_channel *rf,
 840 +                                    struct channel_info *info)
 841 +{
 842 +       u32 reg;
 843 +       unsigned int tx_pin;
 844 +       u16 eeprom;
 845 +       u8 bbp;
 846 +
 847 +       /*
 848 +        * Determine antenna settings from EEPROM
 849 +        */
 850 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 851 +
 852 +       if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 853 +               rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
 854 +       else
 855 +               rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
 856 +
 857 +       /*
 858 +        * Change BBP settings
 859 +        */
 860 +       rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 861 +       rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 862 +       rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 863 +       rt2800usb_bbp_write(rt2x00dev, 86, 0);
 864 +
 865 +       if (rf->channel <= 14) {
 866 +               if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 867 +                       rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
 868 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 869 +               } else {
 870 +                       rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
 871 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 872 +               }
 873 +       } else {
 874 +               rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
 875 +
 876 +               if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 877 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 878 +               else
 879 +                       rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 880 +       }
 881 +
 882 +       rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 883 +       rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 884 +       rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 885 +       rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 886 +       rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
 887 +
 888 +       tx_pin = 0;
 889 +
 890 +       /* Turn on unused PA or LNA when not using 1T or 1R */
 891 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) != 1) {
 892 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 893 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 894 +       }
 895 +
 896 +       /* Turn on unused PA or LNA when not using 1T or 1R */
 897 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) != 1) {
 898 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 899 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 900 +       }
 901 +
 902 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 903 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 904 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 905 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 906 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 907 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 908 +
 909 +       rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 910 +
 911 +       rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
 912 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 913 +       rt2800usb_bbp_write(rt2x00dev, 4, bbp);
 914 +
 915 +       rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
 916 +       rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 917 +       rt2800usb_bbp_write(rt2x00dev, 3, bbp);
 918 +
 919 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 920 +               if (conf_is_ht40(conf)) {
 921 +                       rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
 922 +                       rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
 923 +                       rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
 924 +               } else {
 925 +                       rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
 926 +                       rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
 927 +                       rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
 928 +               }
 929 +       }
 930 +
 931 +       msleep(1);
 932 +}
 933 +
 934 +static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 935 +                                    const int txpower)
 936 +{
 937 +       u32 reg;
 938 +       u32 value = TXPOWER_G_TO_DEV(txpower);
 939 +       u8 r1;
 940 +
 941 +       rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 942 +       rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 943 +       rt2800usb_bbp_write(rt2x00dev, 1, r1);
 944 +
 945 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 946 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 947 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 948 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 949 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 950 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 951 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 952 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 953 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 954 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 955 +
 956 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 957 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 958 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 959 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 960 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 961 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 962 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 963 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 964 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 965 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 966 +
 967 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 968 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 969 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 970 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 971 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 972 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 973 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 974 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 975 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 976 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 977 +
 978 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 979 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 980 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 981 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 982 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 983 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 984 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 985 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 986 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 987 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 988 +
 989 +       rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 990 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 991 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 992 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 993 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 994 +       rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 995 +}
 996 +
 997 +static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 998 +                                        struct rt2x00lib_conf *libconf)
 999 +{
1000 +       u32 reg;
1001 +
1002 +       rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1003 +       rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1004 +                          libconf->conf->short_frame_max_tx_count);
1005 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1006 +                          libconf->conf->long_frame_max_tx_count);
1007 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1008 +       rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1009 +       rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1010 +       rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1011 +       rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
1012 +}
1013 +
1014 +static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
1015 +                                     struct rt2x00lib_conf *libconf)
1016 +{
1017 +       u32 reg;
1018 +
1019 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1020 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1021 +                          libconf->conf->beacon_int * 16);
1022 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1023 +}
1024 +
1025 +static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
1026 +                               struct rt2x00lib_conf *libconf)
1027 +{
1028 +       enum dev_state state =
1029 +           (libconf->conf->flags & IEEE80211_CONF_PS) ?
1030 +               STATE_SLEEP : STATE_AWAKE;
1031 +       u32 reg;
1032 +
1033 +       if (state == STATE_SLEEP) {
1034 +               rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1035 +
1036 +               rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1037 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1038 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1039 +                                  libconf->conf->listen_interval - 1);
1040 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1041 +               rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1042 +
1043 +               rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
1044 +       } else {
1045 +               rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1046 +
1047 +               rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1048 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1049 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1050 +               rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1051 +               rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1052 +       }
1053 +}
1054 +
1055 +static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1056 +                            struct rt2x00lib_conf *libconf,
1057 +                            const unsigned int flags)
1058 +{
1059 +       /* Always recalculate LNA gain before changing configuration */
1060 +       rt2800usb_config_lna_gain(rt2x00dev, libconf);
1061 +
1062 +       if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1063 +               rt2800usb_config_channel(rt2x00dev, libconf->conf,
1064 +                                        &libconf->rf, &libconf->channel);
1065 +       if (flags & IEEE80211_CONF_CHANGE_POWER)
1066 +               rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1067 +       if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1068 +               rt2800usb_config_retry_limit(rt2x00dev, libconf);
1069 +       if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1070 +               rt2800usb_config_duration(rt2x00dev, libconf);
1071 +       if (flags & IEEE80211_CONF_CHANGE_PS)
1072 +               rt2800usb_config_ps(rt2x00dev, libconf);
1073 +}
1074 +
1075 +/*
1076 + * Link tuning
1077 + */
1078 +static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1079 +                                struct link_qual *qual)
1080 +{
1081 +       u32 reg;
1082 +
1083 +       /*
1084 +        * Update FCS error count from register.
1085 +        */
1086 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1087 +       qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1088 +}
1089 +
1090 +static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1091 +{
1092 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1093 +               if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1094 +                       return 0x1c + (2 * rt2x00dev->lna_gain);
1095 +               else
1096 +                       return 0x2e + rt2x00dev->lna_gain;
1097 +       }
1098 +
1099 +       if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1100 +               return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1101 +       else
1102 +               return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1103 +}
1104 +
1105 +static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1106 +                                    struct link_qual *qual, u8 vgc_level)
1107 +{
1108 +       if (qual->vgc_level != vgc_level) {
1109 +               rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1110 +               qual->vgc_level = vgc_level;
1111 +               qual->vgc_level_reg = vgc_level;
1112 +       }
1113 +}
1114 +
1115 +static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1116 +                                 struct link_qual *qual)
1117 +{
1118 +       rt2800usb_set_vgc(rt2x00dev, qual,
1119 +                         rt2800usb_get_default_vgc(rt2x00dev));
1120 +}
1121 +
1122 +static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1123 +                                struct link_qual *qual, const u32 count)
1124 +{
1125 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1126 +               return;
1127 +
1128 +       /*
1129 +        * When RSSI is better then -80 increase VGC level with 0x10
1130 +        */
1131 +       rt2800usb_set_vgc(rt2x00dev, qual,
1132 +                         rt2800usb_get_default_vgc(rt2x00dev) +
1133 +                         ((qual->rssi > -80) * 0x10));
1134 +}
1135 +
1136 +/*
1137 + * Firmware functions
1138 + */
1139 +static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1140 +{
1141 +       return FIRMWARE_RT2870;
1142 +}
1143 +
1144 +static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1145 +{
1146 +       u16 fw_crc;
1147 +       u16 crc;
1148 +
1149 +       /*
1150 +        * The last 2 bytes in the firmware array are the crc checksum itself,
1151 +        * this means that we should never pass those 2 bytes to the crc
1152 +        * algorithm.
1153 +        */
1154 +       fw_crc = (data[len - 2] << 8 | data[len - 1]);
1155 +
1156 +       /*
1157 +        * Use the crc ccitt algorithm.
1158 +        * This will return the same value as the legacy driver which
1159 +        * used bit ordering reversion on the both the firmware bytes
1160 +        * before input input as well as on the final output.
1161 +        * Obviously using crc ccitt directly is much more efficient.
1162 +        */
1163 +       crc = crc_ccitt(~0, data, len - 2);
1164 +
1165 +       /*
1166 +        * There is a small difference between the crc-itu-t + bitrev and
1167 +        * the crc-ccitt crc calculation. In the latter method the 2 bytes
1168 +        * will be swapped, use swab16 to convert the crc to the correct
1169 +        * value.
1170 +        */
1171 +       crc = swab16(crc);
1172 +
1173 +       return fw_crc == crc;
1174 +}
1175 +
1176 +static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1177 +                                   const u8 *data, const size_t len)
1178 +{
1179 +       u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1180 +       size_t offset = 0;
1181 +
1182 +       /*
1183 +        * Firmware files:
1184 +        * There are 2 variations of the rt2870 firmware.
1185 +        * a) size: 4kb
1186 +        * b) size: 8kb
1187 +        * Note that (b) contains 2 seperate firmware blobs of 4k
1188 +        * within the file. The first blob is the same firmware as (a),
1189 +        * but the second blob is for the additional chipsets.
1190 +        */
1191 +       if (len != 4096 && len != 8192)
1192 +               return FW_BAD_LENGTH;
1193 +
1194 +       /*
1195 +        * Check if we need the upper 4kb firmware data or not.
1196 +        */
1197 +       if ((len == 4096) &&
1198 +           (chipset != 0x2860) &&
1199 +           (chipset != 0x2872) &&
1200 +           (chipset != 0x3070))
1201 +               return FW_BAD_VERSION;
1202 +
1203 +       /*
1204 +        * 8kb firmware files must be checked as if it were
1205 +        * 2 seperate firmware files.
1206 +        */
1207 +       while (offset < len) {
1208 +               if (!rt2800usb_check_crc(data + offset, 4096))
1209 +                       return FW_BAD_CRC;
1210 +
1211 +               offset += 4096;
1212 +       }
1213 +
1214 +       return FW_OK;
1215 +}
1216 +
1217 +static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1218 +                                  const u8 *data, const size_t len)
1219 +{
1220 +       unsigned int i;
1221 +       int status;
1222 +       u32 reg;
1223 +       u32 offset;
1224 +       u32 length;
1225 +       u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1226 +
1227 +       /*
1228 +        * Check which section of the firmware we need.
1229 +        */
1230 +       if ((chipset == 0x2860) || (chipset == 0x2872) || (chipset == 0x3070)) {
1231 +               offset = 0;
1232 +               length = 4096;
1233 +       } else {
1234 +               offset = 4096;
1235 +               length = 4096;
1236 +       }
1237 +
1238 +       /*
1239 +        * Wait for stable hardware.
1240 +        */
1241 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1242 +               rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1243 +               if (reg && reg != ~0)
1244 +                       break;
1245 +               msleep(1);
1246 +       }
1247 +
1248 +       if (i == REGISTER_BUSY_COUNT) {
1249 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1250 +               return -EBUSY;
1251 +       }
1252 +
1253 +       /*
1254 +        * Write firmware to device.
1255 +        */
1256 +       rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1257 +                                           USB_VENDOR_REQUEST_OUT,
1258 +                                           FIRMWARE_IMAGE_BASE,
1259 +                                           data + offset, length,
1260 +                                           REGISTER_TIMEOUT32(length));
1261 +
1262 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1263 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1264 +
1265 +       /*
1266 +        * Send firmware request to device to load firmware,
1267 +        * we need to specify a long timeout time.
1268 +        */
1269 +       status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1270 +                                            0, USB_MODE_FIRMWARE,
1271 +                                            REGISTER_TIMEOUT_FIRMWARE);
1272 +       if (status < 0) {
1273 +               ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1274 +               return status;
1275 +       }
1276 +
1277 +       /*
1278 +        * Wait for device to stabilize.
1279 +        */
1280 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1281 +               rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1282 +               if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1283 +                       break;
1284 +               msleep(1);
1285 +       }
1286 +
1287 +       if (i == REGISTER_BUSY_COUNT) {
1288 +               ERROR(rt2x00dev, "PBF system register not ready.\n");
1289 +               return -EBUSY;
1290 +       }
1291 +
1292 +       /*
1293 +        * Initialize firmware.
1294 +        */
1295 +       rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1296 +       rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1297 +       msleep(1);
1298 +
1299 +       return 0;
1300 +}
1301 +
1302 +/*
1303 + * Initialization functions.
1304 + */
1305 +static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1306 +{
1307 +       u32 reg;
1308 +       unsigned int i;
1309 +
1310 +       /*
1311 +        * Wait untill BBP and RF are ready.
1312 +        */
1313 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1314 +               rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1315 +               if (reg && reg != ~0)
1316 +                       break;
1317 +               msleep(1);
1318 +       }
1319 +
1320 +       if (i == REGISTER_BUSY_COUNT) {
1321 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1322 +               return -EBUSY;
1323 +       }
1324 +
1325 +       rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1326 +       rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1327 +
1328 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1329 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1330 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1331 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1332 +
1333 +       rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1334 +
1335 +       rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1336 +                                   USB_MODE_RESET, REGISTER_TIMEOUT);
1337 +
1338 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1339 +
1340 +       rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1341 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1342 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1343 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1344 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1345 +       rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1346 +
1347 +       rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1348 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1349 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1350 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1351 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1352 +       rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1353 +
1354 +       rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1355 +       rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1356 +
1357 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1358 +
1359 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1360 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1361 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1362 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1363 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1364 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1365 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1366 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1367 +
1368 +       if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1369 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1370 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1371 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1372 +       } else {
1373 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1374 +               rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1375 +       }
1376 +
1377 +       rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1378 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1379 +       rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1380 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1381 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1382 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1383 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1384 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1385 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1386 +       rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1387 +
1388 +       rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1389 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1390 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1391 +       rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1392 +
1393 +       rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1394 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1395 +       if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1396 +           rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1397 +               rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1398 +       else
1399 +               rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1400 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1401 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1402 +       rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1403 +
1404 +       rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1405 +
1406 +       rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1407 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1408 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1409 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1410 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1411 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1412 +       rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1413 +
1414 +       rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1415 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1416 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1417 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1418 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1419 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1420 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1421 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1422 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1423 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1424 +       rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1425 +
1426 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1427 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1428 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1429 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1430 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1431 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1432 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1433 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1434 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1435 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1436 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1437 +
1438 +       rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1439 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1440 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1441 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1442 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1443 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1444 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1445 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1446 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1447 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1448 +       rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1449 +
1450 +       rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1451 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1452 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1453 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1454 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1455 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1456 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1457 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1458 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1459 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1460 +       rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1461 +
1462 +       rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1463 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1464 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1465 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1466 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1467 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1468 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1469 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1470 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1471 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1472 +       rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1473 +
1474 +       rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1475 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1476 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1477 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1478 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1479 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1480 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1481 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1482 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1483 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1484 +       rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1485 +
1486 +       rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1487 +
1488 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1489 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1490 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1491 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1492 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1493 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1494 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1495 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1496 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1497 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1498 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1499 +
1500 +       rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1501 +       rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1502 +
1503 +       rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1504 +       rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1505 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1506 +                          IEEE80211_MAX_RTS_THRESHOLD);
1507 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1508 +       rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1509 +
1510 +       rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1511 +       rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1512 +
1513 +       /*
1514 +        * ASIC will keep garbage value after boot, clear encryption keys.
1515 +        */
1516 +       for (i = 0; i < 256; i++) {
1517 +               u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1518 +               rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1519 +                                             wcid, sizeof(wcid));
1520 +
1521 +               rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1522 +               rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1523 +       }
1524 +
1525 +       for (i = 0; i < 16; i++)
1526 +               rt2x00usb_register_write(rt2x00dev,
1527 +                                        SHARED_KEY_MODE_ENTRY(i), 0);
1528 +
1529 +       /*
1530 +        * Clear all beacons
1531 +        * For the Beacon base registers we only need to clear
1532 +        * the first byte since that byte contains the VALID and OWNER
1533 +        * bits which (when set to 0) will invalidate the entire beacon.
1534 +        */
1535 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1536 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1537 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1538 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1539 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1540 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1541 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1542 +       rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1543 +
1544 +       rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1545 +       rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1546 +       rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1547 +
1548 +       rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1549 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1550 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1551 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1552 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1553 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1554 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1555 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1556 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1557 +       rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1558 +
1559 +       rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1560 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1561 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1562 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1563 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1564 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1565 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1566 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1567 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1568 +       rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1569 +
1570 +       rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1571 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1572 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1573 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1574 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1575 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1576 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1577 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1578 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1579 +       rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1580 +
1581 +       rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1582 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1583 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1584 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1585 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1586 +       rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1587 +
1588 +       /*
1589 +        * We must clear the error counters.
1590 +        * These registers are cleared on read,
1591 +        * so we may pass a useless variable to store the value.
1592 +        */
1593 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1594 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1595 +       rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1596 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1597 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1598 +       rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1599 +
1600 +       return 0;
1601 +}
1602 +
1603 +static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1604 +{
1605 +       unsigned int i;
1606 +       u32 reg;
1607 +
1608 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1609 +               rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1610 +               if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1611 +                       return 0;
1612 +
1613 +               udelay(REGISTER_BUSY_DELAY);
1614 +       }
1615 +
1616 +       ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1617 +       return -EACCES;
1618 +}
1619 +
1620 +static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1621 +{
1622 +       unsigned int i;
1623 +       u8 value;
1624 +
1625 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1626 +               rt2800usb_bbp_read(rt2x00dev, 0, &value);
1627 +               if ((value != 0xff) && (value != 0x00))
1628 +                       return 0;
1629 +               udelay(REGISTER_BUSY_DELAY);
1630 +       }
1631 +
1632 +       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1633 +       return -EACCES;
1634 +}
1635 +
1636 +static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1637 +{
1638 +       unsigned int i;
1639 +       u16 eeprom;
1640 +       u8 reg_id;
1641 +       u8 value;
1642 +
1643 +       if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1644 +                    rt2800usb_wait_bbp_ready(rt2x00dev)))
1645 +               return -EACCES;
1646 +
1647 +       rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1648 +       rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1649 +       rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1650 +       rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1651 +       rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1652 +       rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1653 +       rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1654 +       rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1655 +       rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1656 +       rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1657 +       rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1658 +       rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1659 +       rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1660 +       rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1661 +
1662 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1663 +               rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1664 +               rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1665 +       }
1666 +
1667 +       if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1668 +               rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1669 +       }
1670 +
1671 +       if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1672 +               rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1673 +               rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1674 +               rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1675 +       }
1676 +
1677 +       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1678 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1679 +
1680 +               if (eeprom != 0xffff && eeprom != 0x0000) {
1681 +                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1682 +                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1683 +                       rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1684 +               }
1685 +       }
1686 +
1687 +       return 0;
1688 +}
1689 +
1690 +static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1691 +                                  bool bw40, u8 rfcsr24, u8 filter_target)
1692 +{
1693 +       unsigned int i;
1694 +       u8 bbp;
1695 +       u8 rfcsr;
1696 +       u8 passband;
1697 +       u8 stopband;
1698 +       u8 overtuned = 0;
1699 +
1700 +       rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1701 +
1702 +       rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1703 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1704 +       rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1705 +
1706 +       rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1707 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1708 +       rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1709 +
1710 +       /*
1711 +        * Set power & frequency of passband test tone
1712 +        */
1713 +       rt2800usb_bbp_write(rt2x00dev, 24, 0);
1714 +
1715 +       for (i = 0; i < 100; i++) {
1716 +               rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1717 +               msleep(1);
1718 +
1719 +               rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1720 +               if (passband)
1721 +                       break;
1722 +       }
1723 +
1724 +       /*
1725 +        * Set power & frequency of stopband test tone
1726 +        */
1727 +       rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1728 +
1729 +       for (i = 0; i < 100; i++) {
1730 +               rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1731 +               msleep(1);
1732 +
1733 +               rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1734 +
1735 +               if ((passband - stopband) <= filter_target) {
1736 +                       rfcsr24++;
1737 +                       overtuned += ((passband - stopband) == filter_target);
1738 +               } else
1739 +                       break;
1740 +
1741 +               rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1742 +       }
1743 +
1744 +       rfcsr24 -= !!overtuned;
1745 +
1746 +       rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1747 +       return rfcsr24;
1748 +}
1749 +
1750 +static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1751 +{
1752 +       u8 rfcsr;
1753 +       u8 bbp;
1754 +
1755 +       if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1756 +               return 0;
1757 +
1758 +       /*
1759 +        * Init RF calibration.
1760 +        */
1761 +       rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1762 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1763 +       rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1764 +       msleep(1);
1765 +       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1766 +       rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1767 +
1768 +       rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1769 +       rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1770 +       rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1771 +       rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1772 +       rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1773 +       rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1774 +       rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1775 +       rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1776 +       rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1777 +       rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1778 +       rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1779 +       rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1780 +       rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1781 +       rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1782 +       rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1783 +       rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1784 +       rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1785 +       rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1786 +       rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1787 +       rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1788 +
1789 +       /*
1790 +        * Set RX Filter calibration for 20MHz and 40MHz
1791 +        */
1792 +       rt2x00dev->calibration_bw20 =
1793 +           rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1794 +       rt2x00dev->calibration_bw40 =
1795 +           rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1796 +
1797 +       /*
1798 +        * Set back to initial state
1799 +        */
1800 +       rt2800usb_bbp_write(rt2x00dev, 24, 0);
1801 +
1802 +       rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1803 +       rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1804 +       rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1805 +
1806 +       /*
1807 +        * set BBP back to BW20
1808 +        */
1809 +       rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1810 +       rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1811 +       rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1812 +
1813 +       return 0;
1814 +}
1815 +
1816 +/*
1817 + * Device state switch handlers.
1818 + */
1819 +static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1820 +                               enum dev_state state)
1821 +{
1822 +       u32 reg;
1823 +
1824 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1825 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1826 +                          (state == STATE_RADIO_RX_ON) ||
1827 +                          (state == STATE_RADIO_RX_ON_LINK));
1828 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1829 +}
1830 +
1831 +static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1832 +{
1833 +       unsigned int i;
1834 +       u32 reg;
1835 +
1836 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1837 +               rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1838 +               if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1839 +                   !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1840 +                       return 0;
1841 +
1842 +               msleep(1);
1843 +       }
1844 +
1845 +       ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1846 +       return -EACCES;
1847 +}
1848 +
1849 +static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1850 +{
1851 +       u32 reg;
1852 +       u16 word;
1853 +
1854 +       /*
1855 +        * Initialize all registers.
1856 +        */
1857 +       if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1858 +                    rt2800usb_init_registers(rt2x00dev) ||
1859 +                    rt2800usb_init_bbp(rt2x00dev) ||
1860 +                    rt2800usb_init_rfcsr(rt2x00dev)))
1861 +               return -EIO;
1862 +
1863 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1864 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1865 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1866 +
1867 +       udelay(50);
1868 +
1869 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1870 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1871 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1872 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1873 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1874 +
1875 +
1876 +       rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1877 +       rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1878 +       /* Don't use bulk in aggregation when working with USB 1.1 */
1879 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1880 +                          (rt2x00dev->rx->usb_maxpacket == 512));
1881 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1882 +       /* FIXME: Calculate this value based on Aggregation defines */
1883 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
1884 +       rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1885 +       rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1886 +       rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1887 +
1888 +       rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1889 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1890 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1891 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1892 +
1893 +       /*
1894 +        * Send signal to firmware during boot time.
1895 +        */
1896 +       rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1897 +
1898 +       /*
1899 +        * Initialize LED control
1900 +        */
1901 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1902 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1903 +                             word & 0xff, (word >> 8) & 0xff);
1904 +
1905 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1906 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1907 +                             word & 0xff, (word >> 8) & 0xff);
1908 +
1909 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1910 +       rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1911 +                             word & 0xff, (word >> 8) & 0xff);
1912 +
1913 +       return 0;
1914 +}
1915 +
1916 +static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1917 +{
1918 +       u32 reg;
1919 +
1920 +       rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1921 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1922 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1923 +       rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1924 +
1925 +       rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1926 +       rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1927 +       rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1928 +
1929 +       /* Wait for DMA, ignore error */
1930 +       rt2800usb_wait_wpdma_ready(rt2x00dev);
1931 +
1932 +       rt2x00usb_disable_radio(rt2x00dev);
1933 +}
1934 +
1935 +static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1936 +                              enum dev_state state)
1937 +{
1938 +       rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1939 +
1940 +       if (state == STATE_AWAKE)
1941 +               rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1942 +       else
1943 +               rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1944 +
1945 +       return 0;
1946 +}
1947 +
1948 +static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1949 +                                     enum dev_state state)
1950 +{
1951 +       int retval = 0;
1952 +
1953 +       switch (state) {
1954 +       case STATE_RADIO_ON:
1955 +               /*
1956 +                * Before the radio can be enabled, the device first has
1957 +                * to be woken up. After that it needs a bit of time
1958 +                * to be fully awake and the radio can be enabled.
1959 +                */
1960 +               rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1961 +               msleep(1);
1962 +               retval = rt2800usb_enable_radio(rt2x00dev);
1963 +               break;
1964 +       case STATE_RADIO_OFF:
1965 +               /*
1966 +                * After the radio has been disablee, the device should
1967 +                * be put to sleep for powersaving.
1968 +                */
1969 +               rt2800usb_disable_radio(rt2x00dev);
1970 +               rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1971 +               break;
1972 +       case STATE_RADIO_RX_ON:
1973 +       case STATE_RADIO_RX_ON_LINK:
1974 +       case STATE_RADIO_RX_OFF:
1975 +       case STATE_RADIO_RX_OFF_LINK:
1976 +               rt2800usb_toggle_rx(rt2x00dev, state);
1977 +               break;
1978 +       case STATE_RADIO_IRQ_ON:
1979 +       case STATE_RADIO_IRQ_OFF:
1980 +               /* No support, but no error either */
1981 +               break;
1982 +       case STATE_DEEP_SLEEP:
1983 +       case STATE_SLEEP:
1984 +       case STATE_STANDBY:
1985 +       case STATE_AWAKE:
1986 +               retval = rt2800usb_set_state(rt2x00dev, state);
1987 +               break;
1988 +       default:
1989 +               retval = -ENOTSUPP;
1990 +               break;
1991 +       }
1992 +
1993 +       if (unlikely(retval))
1994 +               ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1995 +                     state, retval);
1996 +
1997 +       return retval;
1998 +}
1999 +
2000 +/*
2001 + * TX descriptor initialization
2002 + */
2003 +static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2004 +                                   struct sk_buff *skb,
2005 +                                   struct txentry_desc *txdesc)
2006 +{
2007 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
2008 +       __le32 *txi = skbdesc->desc;
2009 +       __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
2010 +       u32 word;
2011 +
2012 +       /*
2013 +        * Initialize TX Info descriptor
2014 +        */
2015 +       rt2x00_desc_read(txwi, 0, &word);
2016 +       rt2x00_set_field32(&word, TXWI_W0_FRAG,
2017 +                          test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2018 +       rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2019 +       rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2020 +       rt2x00_set_field32(&word, TXWI_W0_TS,
2021 +                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2022 +       rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2023 +                          test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2024 +       rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2025 +       rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2026 +       rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2027 +       rt2x00_set_field32(&word, TXWI_W0_BW,
2028 +                          test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2029 +       rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2030 +                          test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2031 +       rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2032 +       rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2033 +       rt2x00_desc_write(txwi, 0, word);
2034 +
2035 +       rt2x00_desc_read(txwi, 1, &word);
2036 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
2037 +                          test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2038 +       rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2039 +                          test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2040 +       rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2041 +       rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2042 +                          test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2043 +                              txdesc->key_idx : 0xff);
2044 +       rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
2045 +       rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2046 +                          skbdesc->entry->entry_idx);
2047 +       rt2x00_desc_write(txwi, 1, word);
2048 +
2049 +       /*
2050 +        * Always write 0 to IV/EIV fields, hardware will insert the IV
2051 +        * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2052 +        * When TXINFO_W0_WIV is set to 1 it will use the IV data
2053 +        * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2054 +        * crypto entry in the registers should be used to encrypt the frame.
2055 +        */
2056 +       _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2057 +       _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2058 +
2059 +       /*
2060 +        * Initialize TX descriptor
2061 +        */
2062 +       rt2x00_desc_read(txi, 0, &word);
2063 +       rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2064 +                          skb->len + TXWI_DESC_SIZE);
2065 +       rt2x00_set_field32(&word, TXINFO_W0_WIV,
2066 +                          !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2067 +       rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2068 +       rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2069 +       rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2070 +       rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2071 +                          test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2072 +       rt2x00_desc_write(txi, 0, word);
2073 +}
2074 +
2075 +/*
2076 + * TX data initialization
2077 + */
2078 +static void rt2800usb_write_beacon(struct queue_entry *entry)
2079 +{
2080 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2081 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2082 +       unsigned int beacon_base;
2083 +       u32 reg;
2084 +
2085 +       /*
2086 +        * Add the descriptor in front of the skb.
2087 +        */
2088 +       skb_push(entry->skb, entry->queue->desc_size);
2089 +       memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2090 +       skbdesc->desc = entry->skb->data;
2091 +
2092 +       /*
2093 +        * Disable beaconing while we are reloading the beacon data,
2094 +        * otherwise we might be sending out invalid data.
2095 +        */
2096 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2097 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2098 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2099 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2100 +       rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2101 +
2102 +       /*
2103 +        * Write entire beacon with descriptor to register.
2104 +        */
2105 +       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2106 +       rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2107 +                                           USB_VENDOR_REQUEST_OUT, beacon_base,
2108 +                                           entry->skb->data, entry->skb->len,
2109 +                                           REGISTER_TIMEOUT32(entry->skb->len));
2110 +
2111 +       /*
2112 +        * Clean up the beacon skb.
2113 +        */
2114 +       dev_kfree_skb(entry->skb);
2115 +       entry->skb = NULL;
2116 +}
2117 +
2118 +static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2119 +{
2120 +       int length;
2121 +
2122 +       /*
2123 +        * The length _must_ include 4 bytes padding,
2124 +        * it should always be multiple of 4,
2125 +        * but it must _not_ be a multiple of the USB packet size.
2126 +        */
2127 +       length = roundup(entry->skb->len + 4, 4);
2128 +       length += (4 * !(length % entry->queue->usb_maxpacket));
2129 +
2130 +       return length;
2131 +}
2132 +
2133 +static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2134 +                                   const enum data_queue_qid queue)
2135 +{
2136 +       u32 reg;
2137 +
2138 +       if (queue != QID_BEACON) {
2139 +               rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2140 +               return;
2141 +       }
2142 +
2143 +       rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2144 +       if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2145 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2146 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2147 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2148 +               rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2149 +       }
2150 +}
2151 +
2152 +/*
2153 + * RX control handlers
2154 + */
2155 +static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2156 +                                 struct rxdone_entry_desc *rxdesc)
2157 +{
2158 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2159 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2160 +       __le32 *rxd = (__le32 *)entry->skb->data;
2161 +       __le32 *rxwi;
2162 +       u32 rxd0;
2163 +       u32 rxwi0;
2164 +       u32 rxwi1;
2165 +       u32 rxwi2;
2166 +       u32 rxwi3;
2167 +
2168 +       /*
2169 +        * Copy descriptor to the skbdesc->desc buffer, making it safe from
2170 +        * moving of frame data in rt2x00usb.
2171 +        */
2172 +       memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2173 +       rxd = (__le32 *)skbdesc->desc;
2174 +       rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2175 +
2176 +       /*
2177 +        * It is now safe to read the descriptor on all architectures.
2178 +        */
2179 +       rt2x00_desc_read(rxd, 0, &rxd0);
2180 +       rt2x00_desc_read(rxwi, 0, &rxwi0);
2181 +       rt2x00_desc_read(rxwi, 1, &rxwi1);
2182 +       rt2x00_desc_read(rxwi, 2, &rxwi2);
2183 +       rt2x00_desc_read(rxwi, 3, &rxwi3);
2184 +
2185 +       if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2186 +               rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2187 +
2188 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2189 +               /*
2190 +                * Unfortunately we don't know the cipher type used during
2191 +                * decryption. This prevents us from correct providing
2192 +                * correct statistics through debugfs.
2193 +                */
2194 +               rxdesc->cipher = CIPHER_NONE;
2195 +               rxdesc->cipher_status =
2196 +                   rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2197 +       }
2198 +
2199 +       if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2200 +               /*
2201 +                * Hardware has stripped IV/EIV data from 802.11 frame during
2202 +                * decryption. Unfortunately the descriptor doesn't contain
2203 +                * any fields with the EIV/IV data either, so they can't
2204 +                * be restored by rt2x00lib.
2205 +                */
2206 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2207 +
2208 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2209 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
2210 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2211 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2212 +       }
2213 +
2214 +       if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2215 +               rxdesc->dev_flags |= RXDONE_MY_BSS;
2216 +
2217 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2218 +               rxdesc->flags |= RX_FLAG_SHORT_GI;
2219 +
2220 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2221 +               rxdesc->flags |= RX_FLAG_40MHZ;
2222 +
2223 +       /*
2224 +        * Detect RX rate, always use MCS as signal type.
2225 +        */
2226 +       rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2227 +       rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2228 +       rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2229 +
2230 +       /*
2231 +        * Mask of 0x8 bit to remove the short preamble flag.
2232 +        */
2233 +       if (rxdesc->dev_flags == RATE_MODE_CCK)
2234 +               rxdesc->signal &= ~0x8;
2235 +
2236 +       rxdesc->rssi =
2237 +           (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2238 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2239 +
2240 +       rxdesc->noise =
2241 +           (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2242 +            rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2243 +
2244 +       rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2245 +
2246 +       /*
2247 +        * Remove RXWI descriptor from start of buffer.
2248 +        */
2249 +       skb_pull(entry->skb, skbdesc->desc_len);
2250 +       skb_trim(entry->skb, rxdesc->size);
2251 +}
2252 +
2253 +/*
2254 + * Device probe functions.
2255 + */
2256 +static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2257 +{
2258 +       u16 word;
2259 +       u8 *mac;
2260 +       u8 default_lna_gain;
2261 +
2262 +       rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2263 +
2264 +       /*
2265 +        * Start validation of the data that has been read.
2266 +        */
2267 +       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2268 +       if (!is_valid_ether_addr(mac)) {
2269 +               DECLARE_MAC_BUF(macbuf);
2270 +
2271 +               random_ether_addr(mac);
2272 +               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2273 +       }
2274 +
2275 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2276 +       if (word == 0xffff) {
2277 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2278 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2279 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2280 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2281 +               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2282 +       } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2283 +               /*
2284 +                * There is a max of 2 RX streams for RT2860 series
2285 +                */
2286 +               if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2287 +                       rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2288 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2289 +       }
2290 +
2291 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2292 +       if (word == 0xffff) {
2293 +               rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2294 +               rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2295 +               rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2296 +               rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2297 +               rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2298 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2299 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2300 +               rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2301 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2302 +               rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2303 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2304 +               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2305 +       }
2306 +
2307 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2308 +       if ((word & 0x00ff) == 0x00ff) {
2309 +               rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2310 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2311 +                                  LED_MODE_TXRX_ACTIVITY);
2312 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2313 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2314 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2315 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2316 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2317 +               EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2318 +       }
2319 +
2320 +       /*
2321 +        * During the LNA validation we are going to use
2322 +        * lna0 as correct value. Note that EEPROM_LNA
2323 +        * is never validated.
2324 +        */
2325 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2326 +       default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2327 +
2328 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2329 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2330 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2331 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2332 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2333 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2334 +
2335 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2336 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2337 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2338 +       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2339 +           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2340 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2341 +                                  default_lna_gain);
2342 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2343 +
2344 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2345 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2346 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2347 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2348 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2349 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2350 +
2351 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2352 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2353 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2354 +       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2355 +           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2356 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2357 +                                  default_lna_gain);
2358 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2359 +
2360 +       return 0;
2361 +}
2362 +
2363 +static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2364 +{
2365 +       u32 reg;
2366 +       u16 value;
2367 +       u16 eeprom;
2368 +
2369 +       /*
2370 +        * Read EEPROM word for configuration.
2371 +        */
2372 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2373 +
2374 +       /*
2375 +        * Identify RF chipset.
2376 +        */
2377 +       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2378 +       rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2379 +       rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2380 +
2381 +       /*
2382 +        * The check for rt2860 is not a typo, some rt2870 hardware
2383 +        * identifies itself as rt2860 in the CSR register.
2384 +        */
2385 +       if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
2386 +           (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870) &&
2387 +           (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x3070)) {
2388 +               ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2389 +               return -ENODEV;
2390 +       }
2391 +
2392 +       if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2393 +           !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2394 +           !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2395 +           !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2396 +           !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2397 +           !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2398 +               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2399 +               return -ENODEV;
2400 +       }
2401 +
2402 +       /*
2403 +        * Read frequency offset and RF programming sequence.
2404 +        */
2405 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2406 +       rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2407 +
2408 +       /*
2409 +        * Read external LNA informations.
2410 +        */
2411 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2412 +
2413 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2414 +               __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2415 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2416 +               __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2417 +
2418 +       /*
2419 +        * Detect if this device has an hardware controlled radio.
2420 +        */
2421 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2422 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2423 +               __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2424 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2425 +
2426 +       /*
2427 +        * Store led settings, for correct led behaviour.
2428 +        */
2429 +#ifdef CONFIG_RT2X00_LIB_LEDS
2430 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2431 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2432 +       rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2433 +
2434 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2435 +                          &rt2x00dev->led_mcu_reg);
2436 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2437 +
2438 +       return 0;
2439 +}
2440 +
2441 +/*
2442 + * RF value list for rt2870
2443 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2444 + */
2445 +static const struct rf_channel rf_vals[] = {
2446 +       { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2447 +       { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2448 +       { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2449 +       { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2450 +       { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2451 +       { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2452 +       { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2453 +       { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2454 +       { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2455 +       { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2456 +       { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2457 +       { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2458 +       { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2459 +       { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2460 +
2461 +       /* 802.11 UNI / HyperLan 2 */
2462 +       { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2463 +       { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2464 +       { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2465 +       { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2466 +       { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2467 +       { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2468 +       { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2469 +       { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2470 +       { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2471 +       { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2472 +       { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2473 +       { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2474 +
2475 +       /* 802.11 HyperLan 2 */
2476 +       { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2477 +       { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2478 +       { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2479 +       { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2480 +       { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2481 +       { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2482 +       { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2483 +       { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2484 +       { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2485 +       { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2486 +       { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2487 +       { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2488 +       { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2489 +       { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2490 +       { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2491 +       { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2492 +
2493 +       /* 802.11 UNII */
2494 +       { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2495 +       { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2496 +       { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2497 +       { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2498 +       { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2499 +       { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2500 +       { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2501 +
2502 +       /* 802.11 Japan */
2503 +       { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2504 +       { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2505 +       { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2506 +       { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2507 +       { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2508 +       { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2509 +       { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2510 +};
2511 +
2512 +/*
2513 + * RF value list for rt3070
2514 + * Supports: 2.4 GHz
2515 + */
2516 +static const struct rf_channel rf_vals_3070[] = {
2517 +       {1,  241, 2, 2 },
2518 +       {2,  241, 2, 7 },
2519 +       {3,  242, 2, 2 },
2520 +       {4,  242, 2, 7 },
2521 +       {5,  243, 2, 2 },
2522 +       {6,  243, 2, 7 },
2523 +       {7,  244, 2, 2 },
2524 +       {8,  244, 2, 7 },
2525 +       {9,  245, 2, 2 },
2526 +       {10, 245, 2, 7 },
2527 +       {11, 246, 2, 2 },
2528 +       {12, 246, 2, 7 },
2529 +       {13, 247, 2, 2 },
2530 +       {14, 248, 2, 4 },
2531 +};
2532 +
2533 +static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2534 +{
2535 +       struct hw_mode_spec *spec = &rt2x00dev->spec;
2536 +       struct channel_info *info;
2537 +       char *tx_power1;
2538 +       char *tx_power2;
2539 +       unsigned int i;
2540 +       u16 eeprom;
2541 +
2542 +       /*
2543 +        * Initialize all hw fields.
2544 +        */
2545 +       rt2x00dev->hw->flags =
2546 +           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2547 +           IEEE80211_HW_SIGNAL_DBM |
2548 +           IEEE80211_HW_SUPPORTS_PS |
2549 +           IEEE80211_HW_PS_NULLFUNC_STACK;
2550 +       rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2551 +
2552 +       SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2553 +       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2554 +                               rt2x00_eeprom_addr(rt2x00dev,
2555 +                                                  EEPROM_MAC_ADDR_0));
2556 +
2557 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2558 +
2559 +       /*
2560 +        * Initialize HT information.
2561 +        */
2562 +       spec->ht.ht_supported = true;
2563 +       spec->ht.cap =
2564 +           IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2565 +           IEEE80211_HT_CAP_GRN_FLD |
2566 +           IEEE80211_HT_CAP_SGI_20 |
2567 +           IEEE80211_HT_CAP_SGI_40 |
2568 +           IEEE80211_HT_CAP_TX_STBC |
2569 +           IEEE80211_HT_CAP_RX_STBC |
2570 +           IEEE80211_HT_CAP_PSMP_SUPPORT;
2571 +       spec->ht.ampdu_factor = 3;
2572 +       spec->ht.ampdu_density = 4;
2573 +       spec->ht.mcs.tx_params =
2574 +           IEEE80211_HT_MCS_TX_DEFINED |
2575 +           IEEE80211_HT_MCS_TX_RX_DIFF |
2576 +           ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2577 +               IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2578 +
2579 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2580 +       case 3:
2581 +               spec->ht.mcs.rx_mask[2] = 0xff;
2582 +       case 2:
2583 +               spec->ht.mcs.rx_mask[1] = 0xff;
2584 +       case 1:
2585 +               spec->ht.mcs.rx_mask[0] = 0xff;
2586 +               spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2587 +               break;
2588 +       }
2589 +
2590 +       /*
2591 +        * Initialize hw_mode information.
2592 +        */
2593 +       spec->supported_bands = SUPPORT_BAND_2GHZ;
2594 +       spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2595 +
2596 +       if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2597 +           rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2598 +               spec->num_channels = 14;
2599 +               spec->channels = rf_vals;
2600 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2601 +                  rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2602 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
2603 +               spec->num_channels = ARRAY_SIZE(rf_vals);
2604 +               spec->channels = rf_vals;
2605 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2606 +                  rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2607 +               spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2608 +               spec->channels = rf_vals_3070;
2609 +       }
2610 +
2611 +       /*
2612 +        * Create channel information array
2613 +        */
2614 +       info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2615 +       if (!info)
2616 +               return -ENOMEM;
2617 +
2618 +       spec->channels_info = info;
2619 +
2620 +       tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2621 +       tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2622 +
2623 +       for (i = 0; i < 14; i++) {
2624 +               info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2625 +               info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2626 +       }
2627 +
2628 +       if (spec->num_channels > 14) {
2629 +               tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2630 +               tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2631 +
2632 +               for (i = 14; i < spec->num_channels; i++) {
2633 +                       info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2634 +                       info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2635 +               }
2636 +       }
2637 +
2638 +       return 0;
2639 +}
2640 +
2641 +static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2642 +{
2643 +       int retval;
2644 +
2645 +       /*
2646 +        * Allocate eeprom data.
2647 +        */
2648 +       retval = rt2800usb_validate_eeprom(rt2x00dev);
2649 +       if (retval)
2650 +               return retval;
2651 +
2652 +       retval = rt2800usb_init_eeprom(rt2x00dev);
2653 +       if (retval)
2654 +               return retval;
2655 +
2656 +       /*
2657 +        * Initialize hw specifications.
2658 +        */
2659 +       retval = rt2800usb_probe_hw_mode(rt2x00dev);
2660 +       if (retval)
2661 +               return retval;
2662 +
2663 +       /*
2664 +        * This device requires firmware.
2665 +        */
2666 +       __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2667 +       __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2668 +       if (!modparam_nohwcrypt)
2669 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2670 +
2671 +       /*
2672 +        * Set the rssi offset.
2673 +        */
2674 +       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2675 +
2676 +       return 0;
2677 +}
2678 +
2679 +/*
2680 + * IEEE80211 stack callback functions.
2681 + */
2682 +static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2683 +                                  u32 *iv32, u16 *iv16)
2684 +{
2685 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2686 +       struct mac_iveiv_entry iveiv_entry;
2687 +       u32 offset;
2688 +
2689 +       offset = MAC_IVEIV_ENTRY(hw_key_idx);
2690 +       rt2x00usb_register_multiread(rt2x00dev, offset,
2691 +                                     &iveiv_entry, sizeof(iveiv_entry));
2692 +
2693 +       memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2694 +       memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2695 +}
2696 +
2697 +static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2698 +{
2699 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2700 +       u32 reg;
2701 +       bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2702 +
2703 +       rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2704 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2705 +       rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2706 +
2707 +       rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2708 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2709 +       rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2710 +
2711 +       rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2712 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2713 +       rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2714 +
2715 +       rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2716 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2717 +       rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2718 +
2719 +       rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2720 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2721 +       rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2722 +
2723 +       rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2724 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2725 +       rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2726 +
2727 +       rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2728 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2729 +       rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2730 +
2731 +       return 0;
2732 +}
2733 +
2734 +static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2735 +                            const struct ieee80211_tx_queue_params *params)
2736 +{
2737 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2738 +       struct data_queue *queue;
2739 +       struct rt2x00_field32 field;
2740 +       int retval;
2741 +       u32 reg;
2742 +       u32 offset;
2743 +
2744 +       /*
2745 +        * First pass the configuration through rt2x00lib, that will
2746 +        * update the queue settings and validate the input. After that
2747 +        * we are free to update the registers based on the value
2748 +        * in the queue parameter.
2749 +        */
2750 +       retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2751 +       if (retval)
2752 +               return retval;
2753 +
2754 +       /*
2755 +        * We only need to perform additional register initialization
2756 +        * for WMM queues/
2757 +        */
2758 +       if (queue_idx >= 4)
2759 +               return 0;
2760 +
2761 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2762 +
2763 +       /* Update WMM TXOP register */
2764 +       offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2765 +       field.bit_offset = (queue_idx & 1) * 16;
2766 +       field.bit_mask = 0xffff << field.bit_offset;
2767 +
2768 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
2769 +       rt2x00_set_field32(&reg, field, queue->txop);
2770 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
2771 +
2772 +       /* Update WMM registers */
2773 +       field.bit_offset = queue_idx * 4;
2774 +       field.bit_mask = 0xf << field.bit_offset;
2775 +
2776 +       rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2777 +       rt2x00_set_field32(&reg, field, queue->aifs);
2778 +       rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2779 +
2780 +       rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2781 +       rt2x00_set_field32(&reg, field, queue->cw_min);
2782 +       rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2783 +
2784 +       rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2785 +       rt2x00_set_field32(&reg, field, queue->cw_max);
2786 +       rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2787 +
2788 +       /* Update EDCA registers */
2789 +       offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2790 +
2791 +       rt2x00usb_register_read(rt2x00dev, offset, &reg);
2792 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2793 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2794 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2795 +       rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2796 +       rt2x00usb_register_write(rt2x00dev, offset, reg);
2797 +
2798 +       return 0;
2799 +}
2800 +
2801 +static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2802 +{
2803 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2804 +       u64 tsf;
2805 +       u32 reg;
2806 +
2807 +       rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2808 +       tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2809 +       rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2810 +       tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2811 +
2812 +       return tsf;
2813 +}
2814 +
2815 +static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2816 +       .tx                     = rt2x00mac_tx,
2817 +       .start                  = rt2x00mac_start,
2818 +       .stop                   = rt2x00mac_stop,
2819 +       .add_interface          = rt2x00mac_add_interface,
2820 +       .remove_interface       = rt2x00mac_remove_interface,
2821 +       .config                 = rt2x00mac_config,
2822 +       .config_interface       = rt2x00mac_config_interface,
2823 +       .configure_filter       = rt2x00mac_configure_filter,
2824 +       .set_key                = rt2x00mac_set_key,
2825 +       .get_stats              = rt2x00mac_get_stats,
2826 +       .get_tkip_seq           = rt2800usb_get_tkip_seq,
2827 +       .set_rts_threshold      = rt2800usb_set_rts_threshold,
2828 +       .bss_info_changed       = rt2x00mac_bss_info_changed,
2829 +       .conf_tx                = rt2800usb_conf_tx,
2830 +       .get_tx_stats           = rt2x00mac_get_tx_stats,
2831 +       .get_tsf                = rt2800usb_get_tsf,
2832 +};
2833 +
2834 +static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2835 +       .probe_hw               = rt2800usb_probe_hw,
2836 +       .get_firmware_name      = rt2800usb_get_firmware_name,
2837 +       .check_firmware         = rt2800usb_check_firmware,
2838 +       .load_firmware          = rt2800usb_load_firmware,
2839 +       .initialize             = rt2x00usb_initialize,
2840 +       .uninitialize           = rt2x00usb_uninitialize,
2841 +       .clear_entry            = rt2x00usb_clear_entry,
2842 +       .set_device_state       = rt2800usb_set_device_state,
2843 +       .rfkill_poll            = rt2800usb_rfkill_poll,
2844 +       .link_stats             = rt2800usb_link_stats,
2845 +       .reset_tuner            = rt2800usb_reset_tuner,
2846 +       .link_tuner             = rt2800usb_link_tuner,
2847 +       .write_tx_desc          = rt2800usb_write_tx_desc,
2848 +       .write_tx_data          = rt2x00usb_write_tx_data,
2849 +       .write_beacon           = rt2800usb_write_beacon,
2850 +       .get_tx_data_len        = rt2800usb_get_tx_data_len,
2851 +       .kick_tx_queue          = rt2800usb_kick_tx_queue,
2852 +       .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2853 +       .fill_rxdone            = rt2800usb_fill_rxdone,
2854 +       .config_shared_key      = rt2800usb_config_shared_key,
2855 +       .config_pairwise_key    = rt2800usb_config_pairwise_key,
2856 +       .config_filter          = rt2800usb_config_filter,
2857 +       .config_intf            = rt2800usb_config_intf,
2858 +       .config_erp             = rt2800usb_config_erp,
2859 +       .config_ant             = rt2800usb_config_ant,
2860 +       .config                 = rt2800usb_config,
2861 +};
2862 +
2863 +static const struct data_queue_desc rt2800usb_queue_rx = {
2864 +       .entry_num              = RX_ENTRIES,
2865 +       .data_size              = AGGREGATION_SIZE,
2866 +       .desc_size              = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2867 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
2868 +};
2869 +
2870 +static const struct data_queue_desc rt2800usb_queue_tx = {
2871 +       .entry_num              = TX_ENTRIES,
2872 +       .data_size              = AGGREGATION_SIZE,
2873 +       .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2874 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
2875 +};
2876 +
2877 +static const struct data_queue_desc rt2800usb_queue_bcn = {
2878 +       .entry_num              = 8 * BEACON_ENTRIES,
2879 +       .data_size              = MGMT_FRAME_SIZE,
2880 +       .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2881 +       .priv_size              = sizeof(struct queue_entry_priv_usb),
2882 +};
2883 +
2884 +static const struct rt2x00_ops rt2800usb_ops = {
2885 +       .name           = KBUILD_MODNAME,
2886 +       .max_sta_intf   = 1,
2887 +       .max_ap_intf    = 8,
2888 +       .eeprom_size    = EEPROM_SIZE,
2889 +       .rf_size        = RF_SIZE,
2890 +       .tx_queues      = NUM_TX_QUEUES,
2891 +       .rx             = &rt2800usb_queue_rx,
2892 +       .tx             = &rt2800usb_queue_tx,
2893 +       .bcn            = &rt2800usb_queue_bcn,
2894 +       .lib            = &rt2800usb_rt2x00_ops,
2895 +       .hw             = &rt2800usb_mac80211_ops,
2896 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2897 +       .debugfs        = &rt2800usb_rt2x00debug,
2898 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2899 +};
2900 +
2901 +/*
2902 + * rt2800usb module information.
2903 + */
2904 +static struct usb_device_id rt2800usb_device_table[] = {
2905 +       /* Abocom */
2906 +       { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2907 +       { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2908 +       { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2909 +       { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2910 +       { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2911 +       { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2912 +       /* AirTies */
2913 +       { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2914 +       /* Amigo */
2915 +       { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2916 +       { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2917 +       /* Amit */
2918 +       { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2919 +       /* ASUS */
2920 +       { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2921 +       { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2922 +       { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2923 +       { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2924 +       { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2925 +       /* AzureWave */
2926 +       { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2927 +       { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2928 +       { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2929 +       /* Belkin */
2930 +       { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2931 +       { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2932 +       { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2933 +       /* Buffalo */
2934 +       { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2935 +       /* Conceptronic */
2936 +       { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2937 +       { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2938 +       { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2939 +       { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2940 +       { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2941 +       { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2942 +       { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2943 +       { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2944 +       /* Corega */
2945 +       { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2946 +       { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2947 +       { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2948 +       { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2949 +       { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2950 +       /* D-Link */
2951 +       { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2952 +       { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2953 +       { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2954 +       { USB_DEVICE(0x2001, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2955 +       { USB_DEVICE(0x2001, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2956 +       /* Edimax */
2957 +       { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2958 +       { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2959 +       { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2960 +       /* EnGenius */
2961 +       { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2962 +       { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2963 +       { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2964 +       /* Gemtek */
2965 +       { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2966 +       /* Gigabyte */
2967 +       { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2968 +       { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2969 +       { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2970 +       /* Hawking */
2971 +       { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2972 +       { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2973 +       { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2974 +       { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2975 +       /* LevelOne */
2976 +       { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2977 +       { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2978 +       /* Linksys */
2979 +       { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2980 +       /* Logitec */
2981 +       { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2982 +       { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2983 +       { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2984 +       /* Pegatron */
2985 +       { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2986 +       /* Philips */
2987 +       { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2988 +       /* Planex */
2989 +       { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2990 +       { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2991 +       { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2992 +       /* Qcom */
2993 +       { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2994 +       /* Quanta */
2995 +       { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2996 +       /* Ralink */
2997 +       { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2998 +       { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2999 +       { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
3000 +       { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
3001 +       { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
3002 +       { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3003 +       /* Samsung */
3004 +       { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3005 +       /* Siemens */
3006 +       { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
3007 +       /* Sitecom */
3008 +       { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
3009 +       { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
3010 +       { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3011 +       { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3012 +       { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3013 +       { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3014 +       { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3015 +       { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3016 +       { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3017 +       { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3018 +       /* SMC */
3019 +       { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3020 +       { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3021 +       { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3022 +       { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3023 +       { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3024 +       { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3025 +       { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3026 +       /* Sparklan */
3027 +       { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3028 +       /* U-Media*/
3029 +       { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3030 +       /* ZCOM */
3031 +       { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3032 +       { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3033 +       /* Zinwell */
3034 +       { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3035 +       { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3036 +       /* Zyxel */
3037 +       { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3038 +       { 0, }
3039 +};
3040 +
3041 +MODULE_AUTHOR(DRV_PROJECT);
3042 +MODULE_VERSION(DRV_VERSION);
3043 +MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3044 +MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3045 +MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3046 +MODULE_FIRMWARE(FIRMWARE_RT2870);
3047 +MODULE_LICENSE("GPL");
3048 +
3049 +static struct usb_driver rt2800usb_driver = {
3050 +       .name           = KBUILD_MODNAME,
3051 +       .id_table       = rt2800usb_device_table,
3052 +       .probe          = rt2x00usb_probe,
3053 +       .disconnect     = rt2x00usb_disconnect,
3054 +       .suspend        = rt2x00usb_suspend,
3055 +       .resume         = rt2x00usb_resume,
3056 +};
3057 +
3058 +static int __init rt2800usb_init(void)
3059 +{
3060 +       return usb_register(&rt2800usb_driver);
3061 +}
3062 +
3063 +static void __exit rt2800usb_exit(void)
3064 +{
3065 +       usb_deregister(&rt2800usb_driver);
3066 +}
3067 +
3068 +module_init(rt2800usb_init);
3069 +module_exit(rt2800usb_exit);
3070 --- /dev/null
3071 +++ b/drivers/net/wireless/rt2x00/rt2800usb.h
3072 @@ -0,0 +1,1932 @@
3073 +/*
3074 +       Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3075 +       <http://rt2x00.serialmonkey.com>
3076 +
3077 +       This program is free software; you can redistribute it and/or modify
3078 +       it under the terms of the GNU General Public License as published by
3079 +       the Free Software Foundation; either version 2 of the License, or
3080 +       (at your option) any later version.
3081 +
3082 +       This program is distributed in the hope that it will be useful,
3083 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
3084 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3085 +       GNU General Public License for more details.
3086 +
3087 +       You should have received a copy of the GNU General Public License
3088 +       along with this program; if not, write to the
3089 +       Free Software Foundation, Inc.,
3090 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3091 + */
3092 +
3093 +/*
3094 +       Module: rt2800usb
3095 +       Abstract: Data structures and registers for the rt2800usb module.
3096 +       Supported chipsets: RT2800U.
3097 + */
3098 +
3099 +#ifndef RT2800USB_H
3100 +#define RT2800USB_H
3101 +
3102 +/*
3103 + * RF chip defines.
3104 + *
3105 + * RF2820 2.4G 2T3R
3106 + * RF2850 2.4G/5G 2T3R
3107 + * RF2720 2.4G 1T2R
3108 + * RF2750 2.4G/5G 1T2R
3109 + * RF3020 2.4G 1T1R
3110 + * RF2020 2.4G B/G
3111 + */
3112 +#define RF2820                         0x0001
3113 +#define RF2850                         0x0002
3114 +#define RF2720                         0x0003
3115 +#define RF2750                         0x0004
3116 +#define RF3020                         0x0005
3117 +#define RF2020                         0x0006
3118 +
3119 +/*
3120 + * RT2870 version
3121 + */
3122 +#define RT2860C_VERSION                        0x28600100
3123 +#define RT2860D_VERSION                        0x28600101
3124 +#define RT2880E_VERSION                        0x28720200
3125 +#define RT2883_VERSION                 0x28830300
3126 +#define RT3070_VERSION                 0x30700200
3127 +
3128 +/*
3129 + * Signal information.
3130 + * Defaul offset is required for RSSI <-> dBm conversion.
3131 + */
3132 +#define DEFAULT_RSSI_OFFSET            120 /* FIXME */
3133 +
3134 +/*
3135 + * Register layout information.
3136 + */
3137 +#define CSR_REG_BASE                   0x1000
3138 +#define CSR_REG_SIZE                   0x0800
3139 +#define EEPROM_BASE                    0x0000
3140 +#define EEPROM_SIZE                    0x0110
3141 +#define BBP_BASE                       0x0000
3142 +#define BBP_SIZE                       0x0080
3143 +#define RF_BASE                                0x0004
3144 +#define RF_SIZE                                0x0010
3145 +
3146 +/*
3147 + * Number of TX queues.
3148 + */
3149 +#define NUM_TX_QUEUES                  4
3150 +
3151 +/*
3152 + * USB registers.
3153 + */
3154 +
3155 +/*
3156 + * HOST-MCU shared memory
3157 + */
3158 +#define HOST_CMD_CSR                   0x0404
3159 +#define HOST_CMD_CSR_HOST_COMMAND      FIELD32(0x000000ff)
3160 +
3161 +/*
3162 + * INT_SOURCE_CSR: Interrupt source register.
3163 + * Write one to clear corresponding bit.
3164 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3165 + */
3166 +#define INT_SOURCE_CSR                 0x0200
3167 +#define INT_SOURCE_CSR_RXDELAYINT      FIELD32(0x00000001)
3168 +#define INT_SOURCE_CSR_TXDELAYINT      FIELD32(0x00000002)
3169 +#define INT_SOURCE_CSR_RX_DONE         FIELD32(0x00000004)
3170 +#define INT_SOURCE_CSR_AC0_DMA_DONE    FIELD32(0x00000008)
3171 +#define INT_SOURCE_CSR_AC1_DMA_DONE    FIELD32(0x00000010)
3172 +#define INT_SOURCE_CSR_AC2_DMA_DONE    FIELD32(0x00000020)
3173 +#define INT_SOURCE_CSR_AC3_DMA_DONE    FIELD32(0x00000040)
3174 +#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00000080)
3175 +#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00000100)
3176 +#define INT_SOURCE_CSR_MCU_COMMAND     FIELD32(0x00000200)
3177 +#define INT_SOURCE_CSR_RXTX_COHERENT   FIELD32(0x00000400)
3178 +#define INT_SOURCE_CSR_TBTT            FIELD32(0x00000800)
3179 +#define INT_SOURCE_CSR_PRE_TBTT                FIELD32(0x00001000)
3180 +#define INT_SOURCE_CSR_TX_FIFO_STATUS  FIELD32(0x00002000)
3181 +#define INT_SOURCE_CSR_AUTO_WAKEUP     FIELD32(0x00004000)
3182 +#define INT_SOURCE_CSR_GPTIMER         FIELD32(0x00008000)
3183 +#define INT_SOURCE_CSR_RX_COHERENT     FIELD32(0x00010000)
3184 +#define INT_SOURCE_CSR_TX_COHERENT     FIELD32(0x00020000)
3185 +
3186 +/*
3187 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3188 + */
3189 +#define INT_MASK_CSR                   0x0204
3190 +#define INT_MASK_CSR_RXDELAYINT                FIELD32(0x00000001)
3191 +#define INT_MASK_CSR_TXDELAYINT                FIELD32(0x00000002)
3192 +#define INT_MASK_CSR_RX_DONE           FIELD32(0x00000004)
3193 +#define INT_MASK_CSR_AC0_DMA_DONE      FIELD32(0x00000008)
3194 +#define INT_MASK_CSR_AC1_DMA_DONE      FIELD32(0x00000010)
3195 +#define INT_MASK_CSR_AC2_DMA_DONE      FIELD32(0x00000020)
3196 +#define INT_MASK_CSR_AC3_DMA_DONE      FIELD32(0x00000040)
3197 +#define INT_MASK_CSR_HCCA_DMA_DONE     FIELD32(0x00000080)
3198 +#define INT_MASK_CSR_MGMT_DMA_DONE     FIELD32(0x00000100)
3199 +#define INT_MASK_CSR_MCU_COMMAND       FIELD32(0x00000200)
3200 +#define INT_MASK_CSR_RXTX_COHERENT     FIELD32(0x00000400)
3201 +#define INT_MASK_CSR_TBTT              FIELD32(0x00000800)
3202 +#define INT_MASK_CSR_PRE_TBTT          FIELD32(0x00001000)
3203 +#define INT_MASK_CSR_TX_FIFO_STATUS    FIELD32(0x00002000)
3204 +#define INT_MASK_CSR_AUTO_WAKEUP       FIELD32(0x00004000)
3205 +#define INT_MASK_CSR_GPTIMER           FIELD32(0x00008000)
3206 +#define INT_MASK_CSR_RX_COHERENT       FIELD32(0x00010000)
3207 +#define INT_MASK_CSR_TX_COHERENT       FIELD32(0x00020000)
3208 +
3209 +/*
3210 + * WPDMA_GLO_CFG
3211 + */
3212 +#define WPDMA_GLO_CFG                  0x0208
3213 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA    FIELD32(0x00000001)
3214 +#define WPDMA_GLO_CFG_TX_DMA_BUSY      FIELD32(0x00000002)
3215 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA    FIELD32(0x00000004)
3216 +#define WPDMA_GLO_CFG_RX_DMA_BUSY      FIELD32(0x00000008)
3217 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE        FIELD32(0x00000030)
3218 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE        FIELD32(0x00000040)
3219 +#define WPDMA_GLO_CFG_BIG_ENDIAN       FIELD32(0x00000080)
3220 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER   FIELD32(0x0000ff00)
3221 +#define WPDMA_GLO_CFG_HDR_SEG_LEN      FIELD32(0xffff0000)
3222 +
3223 +/*
3224 + * WPDMA_RST_IDX
3225 + */
3226 +#define WPDMA_RST_IDX                  0x020c
3227 +#define WPDMA_RST_IDX_DTX_IDX0         FIELD32(0x00000001)
3228 +#define WPDMA_RST_IDX_DTX_IDX1         FIELD32(0x00000002)
3229 +#define WPDMA_RST_IDX_DTX_IDX2         FIELD32(0x00000004)
3230 +#define WPDMA_RST_IDX_DTX_IDX3         FIELD32(0x00000008)
3231 +#define WPDMA_RST_IDX_DTX_IDX4         FIELD32(0x00000010)
3232 +#define WPDMA_RST_IDX_DTX_IDX5         FIELD32(0x00000020)
3233 +#define WPDMA_RST_IDX_DRX_IDX0         FIELD32(0x00010000)
3234 +
3235 +/*
3236 + * DELAY_INT_CFG
3237 + */
3238 +#define DELAY_INT_CFG                  0x0210
3239 +#define DELAY_INT_CFG_RXMAX_PTIME      FIELD32(0x000000ff)
3240 +#define DELAY_INT_CFG_RXMAX_PINT       FIELD32(0x00007f00)
3241 +#define DELAY_INT_CFG_RXDLY_INT_EN     FIELD32(0x00008000)
3242 +#define DELAY_INT_CFG_TXMAX_PTIME      FIELD32(0x00ff0000)
3243 +#define DELAY_INT_CFG_TXMAX_PINT       FIELD32(0x7f000000)
3244 +#define DELAY_INT_CFG_TXDLY_INT_EN     FIELD32(0x80000000)
3245 +
3246 +/*
3247 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3248 + * AIFSN0: AC_BE
3249 + * AIFSN1: AC_BK
3250 + * AIFSN1: AC_VI
3251 + * AIFSN1: AC_VO
3252 + */
3253 +#define WMM_AIFSN_CFG                  0x0214
3254 +#define WMM_AIFSN_CFG_AIFSN0           FIELD32(0x0000000f)
3255 +#define WMM_AIFSN_CFG_AIFSN1           FIELD32(0x000000f0)
3256 +#define WMM_AIFSN_CFG_AIFSN2           FIELD32(0x00000f00)
3257 +#define WMM_AIFSN_CFG_AIFSN3           FIELD32(0x0000f000)
3258 +
3259 +/*
3260 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3261 + * CWMIN0: AC_BE
3262 + * CWMIN1: AC_BK
3263 + * CWMIN1: AC_VI
3264 + * CWMIN1: AC_VO
3265 + */
3266 +#define WMM_CWMIN_CFG                  0x0218
3267 +#define WMM_CWMIN_CFG_CWMIN0           FIELD32(0x0000000f)
3268 +#define WMM_CWMIN_CFG_CWMIN1           FIELD32(0x000000f0)
3269 +#define WMM_CWMIN_CFG_CWMIN2           FIELD32(0x00000f00)
3270 +#define WMM_CWMIN_CFG_CWMIN3           FIELD32(0x0000f000)
3271 +
3272 +/*
3273 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3274 + * CWMAX0: AC_BE
3275 + * CWMAX1: AC_BK
3276 + * CWMAX1: AC_VI
3277 + * CWMAX1: AC_VO
3278 + */
3279 +#define WMM_CWMAX_CFG                  0x021c
3280 +#define WMM_CWMAX_CFG_CWMAX0           FIELD32(0x0000000f)
3281 +#define WMM_CWMAX_CFG_CWMAX1           FIELD32(0x000000f0)
3282 +#define WMM_CWMAX_CFG_CWMAX2           FIELD32(0x00000f00)
3283 +#define WMM_CWMAX_CFG_CWMAX3           FIELD32(0x0000f000)
3284 +
3285 +/*
3286 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3287 + * AC0TXOP: AC_BK in unit of 32us
3288 + * AC1TXOP: AC_BE in unit of 32us
3289 + */
3290 +#define WMM_TXOP0_CFG                  0x0220
3291 +#define WMM_TXOP0_CFG_AC0TXOP          FIELD32(0x0000ffff)
3292 +#define WMM_TXOP0_CFG_AC1TXOP          FIELD32(0xffff0000)
3293 +
3294 +/*
3295 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3296 + * AC2TXOP: AC_VI in unit of 32us
3297 + * AC3TXOP: AC_VO in unit of 32us
3298 + */
3299 +#define WMM_TXOP1_CFG                  0x0224
3300 +#define WMM_TXOP1_CFG_AC2TXOP          FIELD32(0x0000ffff)
3301 +#define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
3302 +
3303 +/*
3304 + * GPIO_CTRL_CFG:
3305 + */
3306 +#define GPIO_CTRL_CFG                  0x0228
3307 +#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
3308 +#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
3309 +#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
3310 +#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
3311 +#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
3312 +#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
3313 +#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
3314 +#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
3315 +#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00000100)
3316 +
3317 +/*
3318 + * MCU_CMD_CFG
3319 + */
3320 +#define MCU_CMD_CFG                    0x022c
3321 +
3322 +/*
3323 + * AC_BK register offsets
3324 + */
3325 +#define TX_BASE_PTR0                   0x0230
3326 +#define TX_MAX_CNT0                    0x0234
3327 +#define TX_CTX_IDX0                    0x0238
3328 +#define TX_DTX_IDX0                    0x023c
3329 +
3330 +/*
3331 + * AC_BE register offsets
3332 + */
3333 +#define TX_BASE_PTR1                   0x0240
3334 +#define TX_MAX_CNT1                    0x0244
3335 +#define TX_CTX_IDX1                    0x0248
3336 +#define TX_DTX_IDX1                    0x024c
3337 +
3338 +/*
3339 + * AC_VI register offsets
3340 + */
3341 +#define TX_BASE_PTR2                   0x0250
3342 +#define TX_MAX_CNT2                    0x0254
3343 +#define TX_CTX_IDX2                    0x0258
3344 +#define TX_DTX_IDX2                    0x025c
3345 +
3346 +/*
3347 + * AC_VO register offsets
3348 + */
3349 +#define TX_BASE_PTR3                   0x0260
3350 +#define TX_MAX_CNT3                    0x0264
3351 +#define TX_CTX_IDX3                    0x0268
3352 +#define TX_DTX_IDX3                    0x026c
3353 +
3354 +/*
3355 + * HCCA register offsets
3356 + */
3357 +#define TX_BASE_PTR4                   0x0270
3358 +#define TX_MAX_CNT4                    0x0274
3359 +#define TX_CTX_IDX4                    0x0278
3360 +#define TX_DTX_IDX4                    0x027c
3361 +
3362 +/*
3363 + * MGMT register offsets
3364 + */
3365 +#define TX_BASE_PTR5                   0x0280
3366 +#define TX_MAX_CNT5                    0x0284
3367 +#define TX_CTX_IDX5                    0x0288
3368 +#define TX_DTX_IDX5                    0x028c
3369 +
3370 +/*
3371 + * RX register offsets
3372 + */
3373 +#define RX_BASE_PTR                    0x0290
3374 +#define RX_MAX_CNT                     0x0294
3375 +#define RX_CRX_IDX                     0x0298
3376 +#define RX_DRX_IDX                     0x029c
3377 +
3378 +/*
3379 + * USB_DMA_CFG
3380 + * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
3381 + * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
3382 + * PHY_CLEAR: phy watch dog enable.
3383 + * TX_CLEAR: Clear USB DMA TX path.
3384 + * TXOP_HALT: Halt TXOP count down when TX buffer is full.
3385 + * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
3386 + * RX_BULK_EN: Enable USB DMA Rx.
3387 + * TX_BULK_EN: Enable USB DMA Tx.
3388 + * EP_OUT_VALID: OUT endpoint data valid.
3389 + * RX_BUSY: USB DMA RX FSM busy.
3390 + * TX_BUSY: USB DMA TX FSM busy.
3391 + */
3392 +#define USB_DMA_CFG                    0x02a0
3393 +#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT        FIELD32(0x000000ff)
3394 +#define USB_DMA_CFG_RX_BULK_AGG_LIMIT  FIELD32(0x0000ff00)
3395 +#define USB_DMA_CFG_PHY_CLEAR          FIELD32(0x00010000)
3396 +#define USB_DMA_CFG_TX_CLEAR           FIELD32(0x00080000)
3397 +#define USB_DMA_CFG_TXOP_HALT          FIELD32(0x00100000)
3398 +#define USB_DMA_CFG_RX_BULK_AGG_EN     FIELD32(0x00200000)
3399 +#define USB_DMA_CFG_RX_BULK_EN         FIELD32(0x00400000)
3400 +#define USB_DMA_CFG_TX_BULK_EN         FIELD32(0x00800000)
3401 +#define USB_DMA_CFG_EP_OUT_VALID       FIELD32(0x3f000000)
3402 +#define USB_DMA_CFG_RX_BUSY            FIELD32(0x40000000)
3403 +#define USB_DMA_CFG_TX_BUSY            FIELD32(0x80000000)
3404 +
3405 +/*
3406 + * USB_CYC_CFG
3407 + */
3408 +#define USB_CYC_CFG                    0x02a4
3409 +#define USB_CYC_CFG_CLOCK_CYCLE                FIELD32(0x000000ff)
3410 +
3411 +/*
3412 + * PBF_SYS_CTRL
3413 + * HOST_RAM_WRITE: enable Host program ram write selection
3414 + */
3415 +#define PBF_SYS_CTRL                   0x0400
3416 +#define PBF_SYS_CTRL_READY             FIELD32(0x00000080)
3417 +#define PBF_SYS_CTRL_HOST_RAM_WRITE    FIELD32(0x00010000)
3418 +
3419 +/*
3420 + * PBF registers
3421 + * Most are for debug. Driver doesn't touch PBF register.
3422 + */
3423 +#define PBF_CFG                                0x0408
3424 +#define PBF_MAX_PCNT                   0x040c
3425 +#define PBF_CTRL                       0x0410
3426 +#define PBF_INT_STA                    0x0414
3427 +#define PBF_INT_ENA                    0x0418
3428 +
3429 +/*
3430 + * BCN_OFFSET0:
3431 + */
3432 +#define BCN_OFFSET0                    0x042c
3433 +#define BCN_OFFSET0_BCN0               FIELD32(0x000000ff)
3434 +#define BCN_OFFSET0_BCN1               FIELD32(0x0000ff00)
3435 +#define BCN_OFFSET0_BCN2               FIELD32(0x00ff0000)
3436 +#define BCN_OFFSET0_BCN3               FIELD32(0xff000000)
3437 +
3438 +/*
3439 + * BCN_OFFSET1:
3440 + */
3441 +#define BCN_OFFSET1                    0x0430
3442 +#define BCN_OFFSET1_BCN4               FIELD32(0x000000ff)
3443 +#define BCN_OFFSET1_BCN5               FIELD32(0x0000ff00)
3444 +#define BCN_OFFSET1_BCN6               FIELD32(0x00ff0000)
3445 +#define BCN_OFFSET1_BCN7               FIELD32(0xff000000)
3446 +
3447 +/*
3448 + * PBF registers
3449 + * Most are for debug. Driver doesn't touch PBF register.
3450 + */
3451 +#define TXRXQ_PCNT                     0x0438
3452 +#define PBF_DBG                                0x043c
3453 +
3454 +/*
3455 + * RF registers
3456 + */
3457 +#define        RF_CSR_CFG                      0x0500
3458 +#define RF_CSR_CFG_DATA                        FIELD32(0x000000ff)
3459 +#define RF_CSR_CFG_REGNUM              FIELD32(0x00001f00)
3460 +#define RF_CSR_CFG_WRITE               FIELD32(0x00010000)
3461 +#define RF_CSR_CFG_BUSY                        FIELD32(0x00020000)
3462 +
3463 +/*
3464 + * MAC Control/Status Registers(CSR).
3465 + * Some values are set in TU, whereas 1 TU == 1024 us.
3466 + */
3467 +
3468 +/*
3469 + * MAC_CSR0: ASIC revision number.
3470 + * ASIC_REV: 0
3471 + * ASIC_VER: 2870
3472 + */
3473 +#define MAC_CSR0                       0x1000
3474 +#define MAC_CSR0_ASIC_REV              FIELD32(0x0000ffff)
3475 +#define MAC_CSR0_ASIC_VER              FIELD32(0xffff0000)
3476 +
3477 +/*
3478 + * MAC_SYS_CTRL:
3479 + */
3480 +#define MAC_SYS_CTRL                   0x1004
3481 +#define MAC_SYS_CTRL_RESET_CSR         FIELD32(0x00000001)
3482 +#define MAC_SYS_CTRL_RESET_BBP         FIELD32(0x00000002)
3483 +#define MAC_SYS_CTRL_ENABLE_TX         FIELD32(0x00000004)
3484 +#define MAC_SYS_CTRL_ENABLE_RX         FIELD32(0x00000008)
3485 +#define MAC_SYS_CTRL_CONTINUOUS_TX     FIELD32(0x00000010)
3486 +#define MAC_SYS_CTRL_LOOPBACK          FIELD32(0x00000020)
3487 +#define MAC_SYS_CTRL_WLAN_HALT         FIELD32(0x00000040)
3488 +#define MAC_SYS_CTRL_RX_TIMESTAMP      FIELD32(0x00000080)
3489 +
3490 +/*
3491 + * MAC_ADDR_DW0: STA MAC register 0
3492 + */
3493 +#define MAC_ADDR_DW0                   0x1008
3494 +#define MAC_ADDR_DW0_BYTE0             FIELD32(0x000000ff)
3495 +#define MAC_ADDR_DW0_BYTE1             FIELD32(0x0000ff00)
3496 +#define MAC_ADDR_DW0_BYTE2             FIELD32(0x00ff0000)
3497 +#define MAC_ADDR_DW0_BYTE3             FIELD32(0xff000000)
3498 +
3499 +/*
3500 + * MAC_ADDR_DW1: STA MAC register 1
3501 + * UNICAST_TO_ME_MASK:
3502 + * Used to mask off bits from byte 5 of the MAC address
3503 + * to determine the UNICAST_TO_ME bit for RX frames.
3504 + * The full mask is complemented by BSS_ID_MASK:
3505 + *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3506 + */
3507 +#define MAC_ADDR_DW1                   0x100c
3508 +#define MAC_ADDR_DW1_BYTE4             FIELD32(0x000000ff)
3509 +#define MAC_ADDR_DW1_BYTE5             FIELD32(0x0000ff00)
3510 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK        FIELD32(0x00ff0000)
3511 +
3512 +/*
3513 + * MAC_BSSID_DW0: BSSID register 0
3514 + */
3515 +#define MAC_BSSID_DW0                  0x1010
3516 +#define MAC_BSSID_DW0_BYTE0            FIELD32(0x000000ff)
3517 +#define MAC_BSSID_DW0_BYTE1            FIELD32(0x0000ff00)
3518 +#define MAC_BSSID_DW0_BYTE2            FIELD32(0x00ff0000)
3519 +#define MAC_BSSID_DW0_BYTE3            FIELD32(0xff000000)
3520 +
3521 +/*
3522 + * MAC_BSSID_DW1: BSSID register 1
3523 + * BSS_ID_MASK:
3524 + *     0: 1-BSSID mode (BSS index = 0)
3525 + *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
3526 + *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3527 + *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3528 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3529 + * BSSID. This will make sure that those bits will be ignored
3530 + * when determining the MY_BSS of RX frames.
3531 + */
3532 +#define MAC_BSSID_DW1                  0x1014
3533 +#define MAC_BSSID_DW1_BYTE4            FIELD32(0x000000ff)
3534 +#define MAC_BSSID_DW1_BYTE5            FIELD32(0x0000ff00)
3535 +#define MAC_BSSID_DW1_BSS_ID_MASK      FIELD32(0x00030000)
3536 +#define MAC_BSSID_DW1_BSS_BCN_NUM      FIELD32(0x001c0000)
3537 +
3538 +/*
3539 + * MAX_LEN_CFG: Maximum frame length register.
3540 + * MAX_MPDU: rt2860b max 16k bytes
3541 + * MAX_PSDU: Maximum PSDU length
3542 + *     (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3543 + */
3544 +#define MAX_LEN_CFG                    0x1018
3545 +#define MAX_LEN_CFG_MAX_MPDU           FIELD32(0x00000fff)
3546 +#define MAX_LEN_CFG_MAX_PSDU           FIELD32(0x00003000)
3547 +#define MAX_LEN_CFG_MIN_PSDU           FIELD32(0x0000c000)
3548 +#define MAX_LEN_CFG_MIN_MPDU           FIELD32(0x000f0000)
3549 +
3550 +/*
3551 + * BBP_CSR_CFG: BBP serial control register
3552 + * VALUE: Register value to program into BBP
3553 + * REG_NUM: Selected BBP register
3554 + * READ_CONTROL: 0 write BBP, 1 read BBP
3555 + * BUSY: ASIC is busy executing BBP commands
3556 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3557 + * BBP_RW_MODE: 0 serial, 1 paralell
3558 + */
3559 +#define BBP_CSR_CFG                    0x101c
3560 +#define BBP_CSR_CFG_VALUE              FIELD32(0x000000ff)
3561 +#define BBP_CSR_CFG_REGNUM             FIELD32(0x0000ff00)
3562 +#define BBP_CSR_CFG_READ_CONTROL       FIELD32(0x00010000)
3563 +#define BBP_CSR_CFG_BUSY               FIELD32(0x00020000)
3564 +#define BBP_CSR_CFG_BBP_PAR_DUR                FIELD32(0x00040000)
3565 +#define BBP_CSR_CFG_BBP_RW_MODE                FIELD32(0x00080000)
3566 +
3567 +/*
3568 + * RF_CSR_CFG0: RF control register
3569 + * REGID_AND_VALUE: Register value to program into RF
3570 + * BITWIDTH: Selected RF register
3571 + * STANDBYMODE: 0 high when standby, 1 low when standby
3572 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3573 + * BUSY: ASIC is busy executing RF commands
3574 + */
3575 +#define RF_CSR_CFG0                    0x1020
3576 +#define RF_CSR_CFG0_REGID_AND_VALUE    FIELD32(0x00ffffff)
3577 +#define RF_CSR_CFG0_BITWIDTH           FIELD32(0x1f000000)
3578 +#define RF_CSR_CFG0_REG_VALUE_BW       FIELD32(0x1fffffff)
3579 +#define RF_CSR_CFG0_STANDBYMODE                FIELD32(0x20000000)
3580 +#define RF_CSR_CFG0_SEL                        FIELD32(0x40000000)
3581 +#define RF_CSR_CFG0_BUSY               FIELD32(0x80000000)
3582 +
3583 +/*
3584 + * RF_CSR_CFG1: RF control register
3585 + * REGID_AND_VALUE: Register value to program into RF
3586 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3587 + *        0: 3 system clock cycle (37.5usec)
3588 + *        1: 5 system clock cycle (62.5usec)
3589 + */
3590 +#define RF_CSR_CFG1                    0x1024
3591 +#define RF_CSR_CFG1_REGID_AND_VALUE    FIELD32(0x00ffffff)
3592 +#define RF_CSR_CFG1_RFGAP              FIELD32(0x1f000000)
3593 +
3594 +/*
3595 + * RF_CSR_CFG2: RF control register
3596 + * VALUE: Register value to program into RF
3597 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3598 + *        0: 3 system clock cycle (37.5usec)
3599 + *        1: 5 system clock cycle (62.5usec)
3600 + */
3601 +#define RF_CSR_CFG2                    0x1028
3602 +#define RF_CSR_CFG2_VALUE              FIELD32(0x00ffffff)
3603 +
3604 +/*
3605 + * LED_CFG: LED control
3606 + * color LED's:
3607 + *   0: off
3608 + *   1: blinking upon TX2
3609 + *   2: periodic slow blinking
3610 + *   3: always on
3611 + * LED polarity:
3612 + *   0: active low
3613 + *   1: active high
3614 + */
3615 +#define LED_CFG                                0x102c
3616 +#define LED_CFG_ON_PERIOD              FIELD32(0x000000ff)
3617 +#define LED_CFG_OFF_PERIOD             FIELD32(0x0000ff00)
3618 +#define LED_CFG_SLOW_BLINK_PERIOD      FIELD32(0x003f0000)
3619 +#define LED_CFG_R_LED_MODE             FIELD32(0x03000000)
3620 +#define LED_CFG_G_LED_MODE             FIELD32(0x0c000000)
3621 +#define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
3622 +#define LED_CFG_LED_POLAR              FIELD32(0x40000000)
3623 +
3624 +/*
3625 + * XIFS_TIME_CFG: MAC timing
3626 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3627 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3628 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3629 + *     when MAC doesn't reference BBP signal BBRXEND
3630 + * EIFS: unit 1us
3631 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3632 + *
3633 + */
3634 +#define XIFS_TIME_CFG                  0x1100
3635 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME   FIELD32(0x000000ff)
3636 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME   FIELD32(0x0000ff00)
3637 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME   FIELD32(0x000f0000)
3638 +#define XIFS_TIME_CFG_EIFS             FIELD32(0x1ff00000)
3639 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE  FIELD32(0x20000000)
3640 +
3641 +/*
3642 + * BKOFF_SLOT_CFG:
3643 + */
3644 +#define BKOFF_SLOT_CFG                 0x1104
3645 +#define BKOFF_SLOT_CFG_SLOT_TIME       FIELD32(0x000000ff)
3646 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME   FIELD32(0x0000ff00)
3647 +
3648 +/*
3649 + * NAV_TIME_CFG:
3650 + */
3651 +#define NAV_TIME_CFG                   0x1108
3652 +#define NAV_TIME_CFG_SIFS              FIELD32(0x000000ff)
3653 +#define NAV_TIME_CFG_SLOT_TIME         FIELD32(0x0000ff00)
3654 +#define NAV_TIME_CFG_EIFS              FIELD32(0x01ff0000)
3655 +#define NAV_TIME_ZERO_SIFS             FIELD32(0x02000000)
3656 +
3657 +/*
3658 + * CH_TIME_CFG: count as channel busy
3659 + */
3660 +#define CH_TIME_CFG                    0x110c
3661 +
3662 +/*
3663 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3664 + */
3665 +#define PBF_LIFE_TIMER                 0x1110
3666 +
3667 +/*
3668 + * BCN_TIME_CFG:
3669 + * BEACON_INTERVAL: in unit of 1/16 TU
3670 + * TSF_TICKING: Enable TSF auto counting
3671 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3672 + * BEACON_GEN: Enable beacon generator
3673 + */
3674 +#define BCN_TIME_CFG                   0x1114
3675 +#define BCN_TIME_CFG_BEACON_INTERVAL   FIELD32(0x0000ffff)
3676 +#define BCN_TIME_CFG_TSF_TICKING       FIELD32(0x00010000)
3677 +#define BCN_TIME_CFG_TSF_SYNC          FIELD32(0x00060000)
3678 +#define BCN_TIME_CFG_TBTT_ENABLE       FIELD32(0x00080000)
3679 +#define BCN_TIME_CFG_BEACON_GEN                FIELD32(0x00100000)
3680 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE        FIELD32(0xf0000000)
3681 +
3682 +/*
3683 + * TBTT_SYNC_CFG:
3684 + */
3685 +#define TBTT_SYNC_CFG                  0x1118
3686 +
3687 +/*
3688 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3689 + */
3690 +#define TSF_TIMER_DW0                  0x111c
3691 +#define TSF_TIMER_DW0_LOW_WORD         FIELD32(0xffffffff)
3692 +
3693 +/*
3694 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3695 + */
3696 +#define TSF_TIMER_DW1                  0x1120
3697 +#define TSF_TIMER_DW1_HIGH_WORD                FIELD32(0xffffffff)
3698 +
3699 +/*
3700 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3701 + */
3702 +#define TBTT_TIMER                     0x1124
3703 +
3704 +/*
3705 + * INT_TIMER_CFG:
3706 + */
3707 +#define INT_TIMER_CFG                  0x1128
3708 +
3709 +/*
3710 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3711 + */
3712 +#define INT_TIMER_EN                   0x112c
3713 +
3714 +/*
3715 + * CH_IDLE_STA: channel idle time
3716 + */
3717 +#define CH_IDLE_STA                    0x1130
3718 +
3719 +/*
3720 + * CH_BUSY_STA: channel busy time
3721 + */
3722 +#define CH_BUSY_STA                    0x1134
3723 +
3724 +/*
3725 + * MAC_STATUS_CFG:
3726 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3727 + *     if 1 or higher one of the 2 registers is busy.
3728 + */
3729 +#define MAC_STATUS_CFG                 0x1200
3730 +#define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
3731 +
3732 +/*
3733 + * PWR_PIN_CFG:
3734 + */
3735 +#define PWR_PIN_CFG                    0x1204
3736 +
3737 +/*
3738 + * AUTOWAKEUP_CFG: Manual power control / status register
3739 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3740 + * AUTOWAKE: 0:sleep, 1:awake
3741 + */
3742 +#define AUTOWAKEUP_CFG                 0x1208
3743 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME  FIELD32(0x000000ff)
3744 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE        FIELD32(0x00007f00)
3745 +#define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
3746 +
3747 +/*
3748 + * EDCA_AC0_CFG:
3749 + */
3750 +#define EDCA_AC0_CFG                   0x1300
3751 +#define EDCA_AC0_CFG_TX_OP             FIELD32(0x000000ff)
3752 +#define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
3753 +#define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
3754 +#define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
3755 +
3756 +/*
3757 + * EDCA_AC1_CFG:
3758 + */
3759 +#define EDCA_AC1_CFG                   0x1304
3760 +#define EDCA_AC1_CFG_TX_OP             FIELD32(0x000000ff)
3761 +#define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
3762 +#define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
3763 +#define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
3764 +
3765 +/*
3766 + * EDCA_AC2_CFG:
3767 + */
3768 +#define EDCA_AC2_CFG                   0x1308
3769 +#define EDCA_AC2_CFG_TX_OP             FIELD32(0x000000ff)
3770 +#define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
3771 +#define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
3772 +#define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
3773 +
3774 +/*
3775 + * EDCA_AC3_CFG:
3776 + */
3777 +#define EDCA_AC3_CFG                   0x130c
3778 +#define EDCA_AC3_CFG_TX_OP             FIELD32(0x000000ff)
3779 +#define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
3780 +#define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
3781 +#define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)
3782 +
3783 +/*
3784 + * EDCA_TID_AC_MAP:
3785 + */
3786 +#define EDCA_TID_AC_MAP                        0x1310
3787 +
3788 +/*
3789 + * TX_PWR_CFG_0:
3790 + */
3791 +#define TX_PWR_CFG_0                   0x1314
3792 +#define TX_PWR_CFG_0_1MBS              FIELD32(0x0000000f)
3793 +#define TX_PWR_CFG_0_2MBS              FIELD32(0x000000f0)
3794 +#define TX_PWR_CFG_0_55MBS             FIELD32(0x00000f00)
3795 +#define TX_PWR_CFG_0_11MBS             FIELD32(0x0000f000)
3796 +#define TX_PWR_CFG_0_6MBS              FIELD32(0x000f0000)
3797 +#define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
3798 +#define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
3799 +#define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
3800 +
3801 +/*
3802 + * TX_PWR_CFG_1:
3803 + */
3804 +#define TX_PWR_CFG_1                   0x1318
3805 +#define TX_PWR_CFG_1_24MBS             FIELD32(0x0000000f)
3806 +#define TX_PWR_CFG_1_36MBS             FIELD32(0x000000f0)
3807 +#define TX_PWR_CFG_1_48MBS             FIELD32(0x00000f00)
3808 +#define TX_PWR_CFG_1_54MBS             FIELD32(0x0000f000)
3809 +#define TX_PWR_CFG_1_MCS0              FIELD32(0x000f0000)
3810 +#define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
3811 +#define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
3812 +#define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
3813 +
3814 +/*
3815 + * TX_PWR_CFG_2:
3816 + */
3817 +#define TX_PWR_CFG_2                   0x131c
3818 +#define TX_PWR_CFG_2_MCS4              FIELD32(0x0000000f)
3819 +#define TX_PWR_CFG_2_MCS5              FIELD32(0x000000f0)
3820 +#define TX_PWR_CFG_2_MCS6              FIELD32(0x00000f00)
3821 +#define TX_PWR_CFG_2_MCS7              FIELD32(0x0000f000)
3822 +#define TX_PWR_CFG_2_MCS8              FIELD32(0x000f0000)
3823 +#define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
3824 +#define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
3825 +#define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
3826 +
3827 +/*
3828 + * TX_PWR_CFG_3:
3829 + */
3830 +#define TX_PWR_CFG_3                   0x1320
3831 +#define TX_PWR_CFG_3_MCS12             FIELD32(0x0000000f)
3832 +#define TX_PWR_CFG_3_MCS13             FIELD32(0x000000f0)
3833 +#define TX_PWR_CFG_3_MCS14             FIELD32(0x00000f00)
3834 +#define TX_PWR_CFG_3_MCS15             FIELD32(0x0000f000)
3835 +#define TX_PWR_CFG_3_UKNOWN1           FIELD32(0x000f0000)
3836 +#define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
3837 +#define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
3838 +#define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
3839 +
3840 +/*
3841 + * TX_PWR_CFG_4:
3842 + */
3843 +#define TX_PWR_CFG_4                   0x1324
3844 +#define TX_PWR_CFG_4_UKNOWN5           FIELD32(0x0000000f)
3845 +#define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
3846 +#define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
3847 +#define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
3848 +
3849 +/*
3850 + * TX_PIN_CFG:
3851 + */
3852 +#define TX_PIN_CFG                     0x1328
3853 +#define TX_PIN_CFG_PA_PE_A0_EN         FIELD32(0x00000001)
3854 +#define TX_PIN_CFG_PA_PE_G0_EN         FIELD32(0x00000002)
3855 +#define TX_PIN_CFG_PA_PE_A1_EN         FIELD32(0x00000004)
3856 +#define TX_PIN_CFG_PA_PE_G1_EN         FIELD32(0x00000008)
3857 +#define TX_PIN_CFG_PA_PE_A0_POL                FIELD32(0x00000010)
3858 +#define TX_PIN_CFG_PA_PE_G0_POL                FIELD32(0x00000020)
3859 +#define TX_PIN_CFG_PA_PE_A1_POL                FIELD32(0x00000040)
3860 +#define TX_PIN_CFG_PA_PE_G1_POL                FIELD32(0x00000080)
3861 +#define TX_PIN_CFG_LNA_PE_A0_EN                FIELD32(0x00000100)
3862 +#define TX_PIN_CFG_LNA_PE_G0_EN                FIELD32(0x00000200)
3863 +#define TX_PIN_CFG_LNA_PE_A1_EN                FIELD32(0x00000400)
3864 +#define TX_PIN_CFG_LNA_PE_G1_EN                FIELD32(0x00000800)
3865 +#define TX_PIN_CFG_LNA_PE_A0_POL       FIELD32(0x00001000)
3866 +#define TX_PIN_CFG_LNA_PE_G0_POL       FIELD32(0x00002000)
3867 +#define TX_PIN_CFG_LNA_PE_A1_POL       FIELD32(0x00004000)
3868 +#define TX_PIN_CFG_LNA_PE_G1_POL       FIELD32(0x00008000)
3869 +#define TX_PIN_CFG_RFTR_EN             FIELD32(0x00010000)
3870 +#define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
3871 +#define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
3872 +#define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
3873 +
3874 +/*
3875 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3876 + */
3877 +#define TX_BAND_CFG                    0x132c
3878 +#define TX_BAND_CFG_HT40_PLUS          FIELD32(0x00000001)
3879 +#define TX_BAND_CFG_A                  FIELD32(0x00000002)
3880 +#define TX_BAND_CFG_BG                 FIELD32(0x00000004)
3881 +
3882 +/*
3883 + * TX_SW_CFG0:
3884 + */
3885 +#define TX_SW_CFG0                     0x1330
3886 +
3887 +/*
3888 + * TX_SW_CFG1:
3889 + */
3890 +#define TX_SW_CFG1                     0x1334
3891 +
3892 +/*
3893 + * TX_SW_CFG2:
3894 + */
3895 +#define TX_SW_CFG2                     0x1338
3896 +
3897 +/*
3898 + * TXOP_THRES_CFG:
3899 + */
3900 +#define TXOP_THRES_CFG                 0x133c
3901 +
3902 +/*
3903 + * TXOP_CTRL_CFG:
3904 + */
3905 +#define TXOP_CTRL_CFG                  0x1340
3906 +
3907 +/*
3908 + * TX_RTS_CFG:
3909 + * RTS_THRES: unit:byte
3910 + * RTS_FBK_EN: enable rts rate fallback
3911 + */
3912 +#define TX_RTS_CFG                     0x1344
3913 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT        FIELD32(0x000000ff)
3914 +#define TX_RTS_CFG_RTS_THRES           FIELD32(0x00ffff00)
3915 +#define TX_RTS_CFG_RTS_FBK_EN          FIELD32(0x01000000)
3916 +
3917 +/*
3918 + * TX_TIMEOUT_CFG:
3919 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3920 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3921 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3922 + *                it is recommended that:
3923 + *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3924 + */
3925 +#define TX_TIMEOUT_CFG                 0x1348
3926 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME   FIELD32(0x000000f0)
3927 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT  FIELD32(0x0000ff00)
3928 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT   FIELD32(0x00ff0000)
3929 +
3930 +/*
3931 + * TX_RTY_CFG:
3932 + * SHORT_RTY_LIMIT: short retry limit
3933 + * LONG_RTY_LIMIT: long retry limit
3934 + * LONG_RTY_THRE: Long retry threshoold
3935 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3936 + *                   0:expired by retry limit, 1: expired by mpdu life timer
3937 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3938 + *               0:expired by retry limit, 1: expired by mpdu life timer
3939 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3940 + */
3941 +#define TX_RTY_CFG                     0x134c
3942 +#define TX_RTY_CFG_SHORT_RTY_LIMIT     FIELD32(0x000000ff)
3943 +#define TX_RTY_CFG_LONG_RTY_LIMIT      FIELD32(0x0000ff00)
3944 +#define TX_RTY_CFG_LONG_RTY_THRE       FIELD32(0x0fff0000)
3945 +#define TX_RTY_CFG_NON_AGG_RTY_MODE    FIELD32(0x10000000)
3946 +#define TX_RTY_CFG_AGG_RTY_MODE                FIELD32(0x20000000)
3947 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE   FIELD32(0x40000000)
3948 +
3949 +/*
3950 + * TX_LINK_CFG:
3951 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3952 + * MFB_ENABLE: TX apply remote MFB 1:enable
3953 + * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
3954 + *                     0: not apply remote remote unsolicit (MFS=7)
3955 + * TX_MRQ_EN: MCS request TX enable
3956 + * TX_RDG_EN: RDG TX enable
3957 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3958 + * REMOTE_MFB: remote MCS feedback
3959 + * REMOTE_MFS: remote MCS feedback sequence number
3960 + */
3961 +#define TX_LINK_CFG                    0x1350
3962 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME        FIELD32(0x000000ff)
3963 +#define TX_LINK_CFG_MFB_ENABLE         FIELD32(0x00000100)
3964 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3965 +#define TX_LINK_CFG_TX_MRQ_EN          FIELD32(0x00000400)
3966 +#define TX_LINK_CFG_TX_RDG_EN          FIELD32(0x00000800)
3967 +#define TX_LINK_CFG_TX_CF_ACK_EN       FIELD32(0x00001000)
3968 +#define TX_LINK_CFG_REMOTE_MFB         FIELD32(0x00ff0000)
3969 +#define TX_LINK_CFG_REMOTE_MFS         FIELD32(0xff000000)
3970 +
3971 +/*
3972 + * HT_FBK_CFG0:
3973 + */
3974 +#define HT_FBK_CFG0                    0x1354
3975 +#define HT_FBK_CFG0_HTMCS0FBK          FIELD32(0x0000000f)
3976 +#define HT_FBK_CFG0_HTMCS1FBK          FIELD32(0x000000f0)
3977 +#define HT_FBK_CFG0_HTMCS2FBK          FIELD32(0x00000f00)
3978 +#define HT_FBK_CFG0_HTMCS3FBK          FIELD32(0x0000f000)
3979 +#define HT_FBK_CFG0_HTMCS4FBK          FIELD32(0x000f0000)
3980 +#define HT_FBK_CFG0_HTMCS5FBK          FIELD32(0x00f00000)
3981 +#define HT_FBK_CFG0_HTMCS6FBK          FIELD32(0x0f000000)
3982 +#define HT_FBK_CFG0_HTMCS7FBK          FIELD32(0xf0000000)
3983 +
3984 +/*
3985 + * HT_FBK_CFG1:
3986 + */
3987 +#define HT_FBK_CFG1                    0x1358
3988 +#define HT_FBK_CFG1_HTMCS8FBK          FIELD32(0x0000000f)
3989 +#define HT_FBK_CFG1_HTMCS9FBK          FIELD32(0x000000f0)
3990 +#define HT_FBK_CFG1_HTMCS10FBK         FIELD32(0x00000f00)
3991 +#define HT_FBK_CFG1_HTMCS11FBK         FIELD32(0x0000f000)
3992 +#define HT_FBK_CFG1_HTMCS12FBK         FIELD32(0x000f0000)
3993 +#define HT_FBK_CFG1_HTMCS13FBK         FIELD32(0x00f00000)
3994 +#define HT_FBK_CFG1_HTMCS14FBK         FIELD32(0x0f000000)
3995 +#define HT_FBK_CFG1_HTMCS15FBK         FIELD32(0xf0000000)
3996 +
3997 +/*
3998 + * LG_FBK_CFG0:
3999 + */
4000 +#define LG_FBK_CFG0                    0x135c
4001 +#define LG_FBK_CFG0_OFDMMCS0FBK                FIELD32(0x0000000f)
4002 +#define LG_FBK_CFG0_OFDMMCS1FBK                FIELD32(0x000000f0)
4003 +#define LG_FBK_CFG0_OFDMMCS2FBK                FIELD32(0x00000f00)
4004 +#define LG_FBK_CFG0_OFDMMCS3FBK                FIELD32(0x0000f000)
4005 +#define LG_FBK_CFG0_OFDMMCS4FBK                FIELD32(0x000f0000)
4006 +#define LG_FBK_CFG0_OFDMMCS5FBK                FIELD32(0x00f00000)
4007 +#define LG_FBK_CFG0_OFDMMCS6FBK                FIELD32(0x0f000000)
4008 +#define LG_FBK_CFG0_OFDMMCS7FBK                FIELD32(0xf0000000)
4009 +
4010 +/*
4011 + * LG_FBK_CFG1:
4012 + */
4013 +#define LG_FBK_CFG1                    0x1360
4014 +#define LG_FBK_CFG0_CCKMCS0FBK         FIELD32(0x0000000f)
4015 +#define LG_FBK_CFG0_CCKMCS1FBK         FIELD32(0x000000f0)
4016 +#define LG_FBK_CFG0_CCKMCS2FBK         FIELD32(0x00000f00)
4017 +#define LG_FBK_CFG0_CCKMCS3FBK         FIELD32(0x0000f000)
4018 +
4019 +/*
4020 + * CCK_PROT_CFG: CCK Protection
4021 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
4022 + * PROTECT_CTRL: Protection control frame type for CCK TX
4023 + *               0:none, 1:RTS/CTS, 2:CTS-to-self
4024 + * PROTECT_NAV: TXOP protection type for CCK TX
4025 + *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
4026 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
4027 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
4028 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
4029 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
4030 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
4031 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
4032 + * RTS_TH_EN: RTS threshold enable on CCK TX
4033 + */
4034 +#define CCK_PROT_CFG                   0x1364
4035 +#define CCK_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
4036 +#define CCK_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
4037 +#define CCK_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
4038 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
4039 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
4040 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
4041 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
4042 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
4043 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
4044 +#define CCK_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
4045 +
4046 +/*
4047 + * OFDM_PROT_CFG: OFDM Protection
4048 + */
4049 +#define OFDM_PROT_CFG                  0x1368
4050 +#define OFDM_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4051 +#define OFDM_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4052 +#define OFDM_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4053 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4054 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4055 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4056 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4057 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4058 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4059 +#define OFDM_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4060 +
4061 +/*
4062 + * MM20_PROT_CFG: MM20 Protection
4063 + */
4064 +#define MM20_PROT_CFG                  0x136c
4065 +#define MM20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4066 +#define MM20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4067 +#define MM20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4068 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4069 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4070 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4071 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4072 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4073 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4074 +#define MM20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4075 +
4076 +/*
4077 + * MM40_PROT_CFG: MM40 Protection
4078 + */
4079 +#define MM40_PROT_CFG                  0x1370
4080 +#define MM40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4081 +#define MM40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4082 +#define MM40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4083 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4084 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4085 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4086 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4087 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4088 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4089 +#define MM40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4090 +
4091 +/*
4092 + * GF20_PROT_CFG: GF20 Protection
4093 + */
4094 +#define GF20_PROT_CFG                  0x1374
4095 +#define GF20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4096 +#define GF20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4097 +#define GF20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4098 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4099 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4100 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4101 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4102 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4103 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4104 +#define GF20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4105 +
4106 +/*
4107 + * GF40_PROT_CFG: GF40 Protection
4108 + */
4109 +#define GF40_PROT_CFG                  0x1378
4110 +#define GF40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
4111 +#define GF40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
4112 +#define GF40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
4113 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
4114 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4115 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4116 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4117 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4118 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4119 +#define GF40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
4120 +
4121 +/*
4122 + * EXP_CTS_TIME:
4123 + */
4124 +#define EXP_CTS_TIME                   0x137c
4125 +
4126 +/*
4127 + * EXP_ACK_TIME:
4128 + */
4129 +#define EXP_ACK_TIME                   0x1380
4130 +
4131 +/*
4132 + * RX_FILTER_CFG: RX configuration register.
4133 + */
4134 +#define RX_FILTER_CFG                  0x1400
4135 +#define RX_FILTER_CFG_DROP_CRC_ERROR   FIELD32(0x00000001)
4136 +#define RX_FILTER_CFG_DROP_PHY_ERROR   FIELD32(0x00000002)
4137 +#define RX_FILTER_CFG_DROP_NOT_TO_ME   FIELD32(0x00000004)
4138 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4139 +#define RX_FILTER_CFG_DROP_VER_ERROR   FIELD32(0x00000010)
4140 +#define RX_FILTER_CFG_DROP_MULTICAST   FIELD32(0x00000020)
4141 +#define RX_FILTER_CFG_DROP_BROADCAST   FIELD32(0x00000040)
4142 +#define RX_FILTER_CFG_DROP_DUPLICATE   FIELD32(0x00000080)
4143 +#define RX_FILTER_CFG_DROP_CF_END_ACK  FIELD32(0x00000100)
4144 +#define RX_FILTER_CFG_DROP_CF_END      FIELD32(0x00000200)
4145 +#define RX_FILTER_CFG_DROP_ACK         FIELD32(0x00000400)
4146 +#define RX_FILTER_CFG_DROP_CTS         FIELD32(0x00000800)
4147 +#define RX_FILTER_CFG_DROP_RTS         FIELD32(0x00001000)
4148 +#define RX_FILTER_CFG_DROP_PSPOLL      FIELD32(0x00002000)
4149 +#define RX_FILTER_CFG_DROP_BA          FIELD32(0x00004000)
4150 +#define RX_FILTER_CFG_DROP_BAR         FIELD32(0x00008000)
4151 +#define RX_FILTER_CFG_DROP_CNTL                FIELD32(0x00010000)
4152 +
4153 +/*
4154 + * AUTO_RSP_CFG:
4155 + * AUTORESPONDER: 0: disable, 1: enable
4156 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4157 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4158 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4159 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4160 + * DUAL_CTS_EN: Power bit value in control frame
4161 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4162 + */
4163 +#define AUTO_RSP_CFG                   0x1404
4164 +#define AUTO_RSP_CFG_AUTORESPONDER     FIELD32(0x00000001)
4165 +#define AUTO_RSP_CFG_BAC_ACK_POLICY    FIELD32(0x00000002)
4166 +#define AUTO_RSP_CFG_CTS_40_MMODE      FIELD32(0x00000004)
4167 +#define AUTO_RSP_CFG_CTS_40_MREF       FIELD32(0x00000008)
4168 +#define AUTO_RSP_CFG_AR_PREAMBLE       FIELD32(0x00000010)
4169 +#define AUTO_RSP_CFG_DUAL_CTS_EN       FIELD32(0x00000040)
4170 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT   FIELD32(0x00000080)
4171 +
4172 +/*
4173 + * LEGACY_BASIC_RATE:
4174 + */
4175 +#define LEGACY_BASIC_RATE              0x1408
4176 +
4177 +/*
4178 + * HT_BASIC_RATE:
4179 + */
4180 +#define HT_BASIC_RATE                  0x140c
4181 +
4182 +/*
4183 + * HT_CTRL_CFG:
4184 + */
4185 +#define HT_CTRL_CFG                    0x1410
4186 +
4187 +/*
4188 + * SIFS_COST_CFG:
4189 + */
4190 +#define SIFS_COST_CFG                  0x1414
4191 +
4192 +/*
4193 + * RX_PARSER_CFG:
4194 + * Set NAV for all received frames
4195 + */
4196 +#define RX_PARSER_CFG                  0x1418
4197 +
4198 +/*
4199 + * TX_SEC_CNT0:
4200 + */
4201 +#define TX_SEC_CNT0                    0x1500
4202 +
4203 +/*
4204 + * RX_SEC_CNT0:
4205 + */
4206 +#define RX_SEC_CNT0                    0x1504
4207 +
4208 +/*
4209 + * CCMP_FC_MUTE:
4210 + */
4211 +#define CCMP_FC_MUTE                   0x1508
4212 +
4213 +/*
4214 + * TXOP_HLDR_ADDR0:
4215 + */
4216 +#define TXOP_HLDR_ADDR0                        0x1600
4217 +
4218 +/*
4219 + * TXOP_HLDR_ADDR1:
4220 + */
4221 +#define TXOP_HLDR_ADDR1                        0x1604
4222 +
4223 +/*
4224 + * TXOP_HLDR_ET:
4225 + */
4226 +#define TXOP_HLDR_ET                   0x1608
4227 +
4228 +/*
4229 + * QOS_CFPOLL_RA_DW0:
4230 + */
4231 +#define QOS_CFPOLL_RA_DW0              0x160c
4232 +
4233 +/*
4234 + * QOS_CFPOLL_RA_DW1:
4235 + */
4236 +#define QOS_CFPOLL_RA_DW1              0x1610
4237 +
4238 +/*
4239 + * QOS_CFPOLL_QC:
4240 + */
4241 +#define QOS_CFPOLL_QC                  0x1614
4242 +
4243 +/*
4244 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4245 + */
4246 +#define RX_STA_CNT0                    0x1700
4247 +#define RX_STA_CNT0_CRC_ERR            FIELD32(0x0000ffff)
4248 +#define RX_STA_CNT0_PHY_ERR            FIELD32(0xffff0000)
4249 +
4250 +/*
4251 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4252 + */
4253 +#define RX_STA_CNT1                    0x1704
4254 +#define RX_STA_CNT1_FALSE_CCA          FIELD32(0x0000ffff)
4255 +#define RX_STA_CNT1_PLCP_ERR           FIELD32(0xffff0000)
4256 +
4257 +/*
4258 + * RX_STA_CNT2:
4259 + */
4260 +#define RX_STA_CNT2                    0x1708
4261 +#define RX_STA_CNT2_RX_DUPLI_COUNT     FIELD32(0x0000ffff)
4262 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW   FIELD32(0xffff0000)
4263 +
4264 +/*
4265 + * TX_STA_CNT0: TX Beacon count
4266 + */
4267 +#define TX_STA_CNT0                    0x170c
4268 +#define TX_STA_CNT0_TX_FAIL_COUNT      FIELD32(0x0000ffff)
4269 +#define TX_STA_CNT0_TX_BEACON_COUNT    FIELD32(0xffff0000)
4270 +
4271 +/*
4272 + * TX_STA_CNT1: TX tx count
4273 + */
4274 +#define TX_STA_CNT1                    0x1710
4275 +#define TX_STA_CNT1_TX_SUCCESS         FIELD32(0x0000ffff)
4276 +#define TX_STA_CNT1_TX_RETRANSMIT      FIELD32(0xffff0000)
4277 +
4278 +/*
4279 + * TX_STA_CNT2: TX tx count
4280 + */
4281 +#define TX_STA_CNT2                    0x1714
4282 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT  FIELD32(0x0000ffff)
4283 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT        FIELD32(0xffff0000)
4284 +
4285 +/*
4286 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4287 + */
4288 +#define TX_STA_FIFO                    0x1718
4289 +#define TX_STA_FIFO_VALID              FIELD32(0x00000001)
4290 +#define TX_STA_FIFO_PID_TYPE           FIELD32(0x0000001e)
4291 +#define TX_STA_FIFO_TX_SUCCESS         FIELD32(0x00000020)
4292 +#define TX_STA_FIFO_TX_AGGRE           FIELD32(0x00000040)
4293 +#define TX_STA_FIFO_TX_ACK_REQUIRED    FIELD32(0x00000080)
4294 +#define TX_STA_FIFO_WCID               FIELD32(0x0000ff00)
4295 +#define TX_STA_FIFO_SUCCESS_RATE       FIELD32(0xffff0000)
4296 +
4297 +/*
4298 + * TX_AGG_CNT: Debug counter
4299 + */
4300 +#define TX_AGG_CNT                     0x171c
4301 +#define TX_AGG_CNT_NON_AGG_TX_COUNT    FIELD32(0x0000ffff)
4302 +#define TX_AGG_CNT_AGG_TX_COUNT                FIELD32(0xffff0000)
4303 +
4304 +/*
4305 + * TX_AGG_CNT0:
4306 + */
4307 +#define TX_AGG_CNT0                    0x1720
4308 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT   FIELD32(0x0000ffff)
4309 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT   FIELD32(0xffff0000)
4310 +
4311 +/*
4312 + * TX_AGG_CNT1:
4313 + */
4314 +#define TX_AGG_CNT1                    0x1724
4315 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT   FIELD32(0x0000ffff)
4316 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT   FIELD32(0xffff0000)
4317 +
4318 +/*
4319 + * TX_AGG_CNT2:
4320 + */
4321 +#define TX_AGG_CNT2                    0x1728
4322 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT   FIELD32(0x0000ffff)
4323 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT   FIELD32(0xffff0000)
4324 +
4325 +/*
4326 + * TX_AGG_CNT3:
4327 + */
4328 +#define TX_AGG_CNT3                    0x172c
4329 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT   FIELD32(0x0000ffff)
4330 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT   FIELD32(0xffff0000)
4331 +
4332 +/*
4333 + * TX_AGG_CNT4:
4334 + */
4335 +#define TX_AGG_CNT4                    0x1730
4336 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT   FIELD32(0x0000ffff)
4337 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT  FIELD32(0xffff0000)
4338 +
4339 +/*
4340 + * TX_AGG_CNT5:
4341 + */
4342 +#define TX_AGG_CNT5                    0x1734
4343 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT  FIELD32(0x0000ffff)
4344 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT  FIELD32(0xffff0000)
4345 +
4346 +/*
4347 + * TX_AGG_CNT6:
4348 + */
4349 +#define TX_AGG_CNT6                    0x1738
4350 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT  FIELD32(0x0000ffff)
4351 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT  FIELD32(0xffff0000)
4352 +
4353 +/*
4354 + * TX_AGG_CNT7:
4355 + */
4356 +#define TX_AGG_CNT7                    0x173c
4357 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT  FIELD32(0x0000ffff)
4358 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT  FIELD32(0xffff0000)
4359 +
4360 +/*
4361 + * MPDU_DENSITY_CNT:
4362 + * TX_ZERO_DEL: TX zero length delimiter count
4363 + * RX_ZERO_DEL: RX zero length delimiter count
4364 + */
4365 +#define MPDU_DENSITY_CNT               0x1740
4366 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL   FIELD32(0x0000ffff)
4367 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL   FIELD32(0xffff0000)
4368 +
4369 +/*
4370 + * Security key table memory.
4371 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4372 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4373 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4374 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4375 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4376 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4377 + */
4378 +#define MAC_WCID_BASE                  0x1800
4379 +#define PAIRWISE_KEY_TABLE_BASE                0x4000
4380 +#define MAC_IVEIV_TABLE_BASE           0x6000
4381 +#define MAC_WCID_ATTRIBUTE_BASE                0x6800
4382 +#define SHARED_KEY_TABLE_BASE          0x6c00
4383 +#define SHARED_KEY_MODE_BASE           0x7000
4384 +
4385 +#define MAC_WCID_ENTRY(__idx) \
4386 +       ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4387 +#define PAIRWISE_KEY_ENTRY(__idx) \
4388 +       ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4389 +#define MAC_IVEIV_ENTRY(__idx) \
4390 +       ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4391 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4392 +       ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4393 +#define SHARED_KEY_ENTRY(__idx) \
4394 +       ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4395 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4396 +       ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4397 +
4398 +struct mac_wcid_entry {
4399 +       u8 mac[6];
4400 +       u8 reserved[2];
4401 +} __attribute__ ((packed));
4402 +
4403 +struct hw_key_entry {
4404 +       u8 key[16];
4405 +       u8 tx_mic[8];
4406 +       u8 rx_mic[8];
4407 +} __attribute__ ((packed));
4408 +
4409 +struct mac_iveiv_entry {
4410 +       u8 iv[8];
4411 +} __attribute__ ((packed));
4412 +
4413 +/*
4414 + * MAC_WCID_ATTRIBUTE:
4415 + */
4416 +#define MAC_WCID_ATTRIBUTE_KEYTAB      FIELD32(0x00000001)
4417 +#define MAC_WCID_ATTRIBUTE_CIPHER      FIELD32(0x0000000e)
4418 +#define MAC_WCID_ATTRIBUTE_BSS_IDX     FIELD32(0x00000070)
4419 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF    FIELD32(0x00000380)
4420 +
4421 +/*
4422 + * SHARED_KEY_MODE:
4423 + */
4424 +#define SHARED_KEY_MODE_BSS0_KEY0      FIELD32(0x00000007)
4425 +#define SHARED_KEY_MODE_BSS0_KEY1      FIELD32(0x00000070)
4426 +#define SHARED_KEY_MODE_BSS0_KEY2      FIELD32(0x00000700)
4427 +#define SHARED_KEY_MODE_BSS0_KEY3      FIELD32(0x00007000)
4428 +#define SHARED_KEY_MODE_BSS1_KEY0      FIELD32(0x00070000)
4429 +#define SHARED_KEY_MODE_BSS1_KEY1      FIELD32(0x00700000)
4430 +#define SHARED_KEY_MODE_BSS1_KEY2      FIELD32(0x07000000)
4431 +#define SHARED_KEY_MODE_BSS1_KEY3      FIELD32(0x70000000)
4432 +
4433 +/*
4434 + * HOST-MCU communication
4435 + */
4436 +
4437 +/*
4438 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4439 + */
4440 +#define H2M_MAILBOX_CSR                        0x7010
4441 +#define H2M_MAILBOX_CSR_ARG0           FIELD32(0x000000ff)
4442 +#define H2M_MAILBOX_CSR_ARG1           FIELD32(0x0000ff00)
4443 +#define H2M_MAILBOX_CSR_CMD_TOKEN      FIELD32(0x00ff0000)
4444 +#define H2M_MAILBOX_CSR_OWNER          FIELD32(0xff000000)
4445 +
4446 +/*
4447 + * H2M_MAILBOX_CID:
4448 + */
4449 +#define H2M_MAILBOX_CID                        0x7014
4450 +
4451 +/*
4452 + * H2M_MAILBOX_STATUS:
4453 + */
4454 +#define H2M_MAILBOX_STATUS             0x701c
4455 +
4456 +/*
4457 + * H2M_INT_SRC:
4458 + */
4459 +#define H2M_INT_SRC                    0x7024
4460 +
4461 +/*
4462 + * H2M_BBP_AGENT:
4463 + */
4464 +#define H2M_BBP_AGENT                  0x7028
4465 +
4466 +/*
4467 + * MCU_LEDCS: LED control for MCU Mailbox.
4468 + */
4469 +#define MCU_LEDCS_LED_MODE             FIELD8(0x1f)
4470 +#define MCU_LEDCS_POLARITY             FIELD8(0x01)
4471 +
4472 +/*
4473 + * HW_CS_CTS_BASE:
4474 + * Carrier-sense CTS frame base address.
4475 + * It's where mac stores carrier-sense frame for carrier-sense function.
4476 + */
4477 +#define HW_CS_CTS_BASE                 0x7700
4478 +
4479 +/*
4480 + * HW_DFS_CTS_BASE:
4481 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4482 + */
4483 +#define HW_DFS_CTS_BASE                        0x7780
4484 +
4485 +/*
4486 + * TXRX control registers - base address 0x3000
4487 + */
4488 +
4489 +/*
4490 + * TXRX_CSR1:
4491 + * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4492 + */
4493 +#define TXRX_CSR1                      0x77d0
4494 +
4495 +/*
4496 + * HW_DEBUG_SETTING_BASE:
4497 + * since NULL frame won't be that long (256 byte)
4498 + * We steal 16 tail bytes to save debugging settings
4499 + */
4500 +#define HW_DEBUG_SETTING_BASE          0x77f0
4501 +#define HW_DEBUG_SETTING_BASE2         0x7770
4502 +
4503 +/*
4504 + * HW_BEACON_BASE
4505 + * In order to support maximum 8 MBSS and its maximum length
4506 + * is 512 bytes for each beacon
4507 + * Three section discontinue memory segments will be used.
4508 + * 1. The original region for BCN 0~3
4509 + * 2. Extract memory from FCE table for BCN 4~5
4510 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4511 + *    It occupied those memory of wcid 238~253 for BCN 6
4512 + *    and wcid 222~237 for BCN 7
4513 + *
4514 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4515 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4516 + */
4517 +#define HW_BEACON_BASE0                        0x7800
4518 +#define HW_BEACON_BASE1                        0x7a00
4519 +#define HW_BEACON_BASE2                        0x7c00
4520 +#define HW_BEACON_BASE3                        0x7e00
4521 +#define HW_BEACON_BASE4                        0x7200
4522 +#define HW_BEACON_BASE5                        0x7400
4523 +#define HW_BEACON_BASE6                        0x5dc0
4524 +#define HW_BEACON_BASE7                        0x5bc0
4525 +
4526 +#define HW_BEACON_OFFSET(__index) \
4527 +       ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4528 +         (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4529 +         (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4530 +
4531 +/*
4532 + * 8051 firmware image.
4533 + */
4534 +#define FIRMWARE_RT2870                        "rt2870.bin"
4535 +#define FIRMWARE_IMAGE_BASE            0x3000
4536 +
4537 +/*
4538 + * BBP registers.
4539 + * The wordsize of the BBP is 8 bits.
4540 + */
4541 +
4542 +/*
4543 + * BBP 1: TX Antenna
4544 + */
4545 +#define BBP1_TX_POWER                  FIELD8(0x07)
4546 +#define BBP1_TX_ANTENNA                        FIELD8(0x18)
4547 +
4548 +/*
4549 + * BBP 3: RX Antenna
4550 + */
4551 +#define BBP3_RX_ANTENNA                        FIELD8(0x18)
4552 +#define BBP3_HT40_PLUS                 FIELD8(0x20)
4553 +
4554 +/*
4555 + * BBP 4: Bandwidth
4556 + */
4557 +#define BBP4_TX_BF                     FIELD8(0x01)
4558 +#define BBP4_BANDWIDTH                 FIELD8(0x18)
4559 +
4560 +/*
4561 + * RFCSR registers
4562 + * The wordsize of the RFCSR is 8 bits.
4563 + */
4564 +
4565 +/*
4566 + * RFCSR 6:
4567 + */
4568 +#define RFCSR6_R                       FIELD8(0x03)
4569 +
4570 +/*
4571 + * RFCSR 7:
4572 + */
4573 +#define RFCSR7_RF_TUNING               FIELD8(0x01)
4574 +
4575 +/*
4576 + * RFCSR 12:
4577 + */
4578 +#define RFCSR12_TX_POWER               FIELD8(0x1f)
4579 +
4580 +/*
4581 + * RFCSR 22:
4582 + */
4583 +#define RFCSR22_BASEBAND_LOOPBACK      FIELD8(0x01)
4584 +
4585 +/*
4586 + * RFCSR 23:
4587 + */
4588 +#define RFCSR23_FREQ_OFFSET            FIELD8(0x7f)
4589 +
4590 +/*
4591 + * RFCSR 30:
4592 + */
4593 +#define RFCSR30_RF_CALIBRATION         FIELD8(0x80)
4594 +
4595 +/*
4596 + * RF registers
4597 + */
4598 +
4599 +/*
4600 + * RF 2
4601 + */
4602 +#define RF2_ANTENNA_RX2                        FIELD32(0x00000040)
4603 +#define RF2_ANTENNA_TX1                        FIELD32(0x00004000)
4604 +#define RF2_ANTENNA_RX1                        FIELD32(0x00020000)
4605 +
4606 +/*
4607 + * RF 3
4608 + */
4609 +#define RF3_TXPOWER_G                  FIELD32(0x00003e00)
4610 +#define RF3_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000200)
4611 +#define RF3_TXPOWER_A                  FIELD32(0x00003c00)
4612 +
4613 +/*
4614 + * RF 4
4615 + */
4616 +#define RF4_TXPOWER_G                  FIELD32(0x000007c0)
4617 +#define RF4_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000040)
4618 +#define RF4_TXPOWER_A                  FIELD32(0x00000780)
4619 +#define RF4_FREQ_OFFSET                        FIELD32(0x001f8000)
4620 +#define RF4_HT40                       FIELD32(0x00200000)
4621 +
4622 +/*
4623 + * EEPROM content.
4624 + * The wordsize of the EEPROM is 16 bits.
4625 + */
4626 +
4627 +/*
4628 + * EEPROM Version
4629 + */
4630 +#define EEPROM_VERSION                 0x0001
4631 +#define EEPROM_VERSION_FAE             FIELD16(0x00ff)
4632 +#define EEPROM_VERSION_VERSION         FIELD16(0xff00)
4633 +
4634 +/*
4635 + * HW MAC address.
4636 + */
4637 +#define EEPROM_MAC_ADDR_0              0x0002
4638 +#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
4639 +#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
4640 +#define EEPROM_MAC_ADDR_1              0x0003
4641 +#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
4642 +#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
4643 +#define EEPROM_MAC_ADDR_2              0x0004
4644 +#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
4645 +#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
4646 +
4647 +/*
4648 + * EEPROM ANTENNA config
4649 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4650 + * TXPATH: 1: 1T, 2: 2T
4651 + */
4652 +#define        EEPROM_ANTENNA                  0x001a
4653 +#define EEPROM_ANTENNA_RXPATH          FIELD16(0x000f)
4654 +#define EEPROM_ANTENNA_TXPATH          FIELD16(0x00f0)
4655 +#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0f00)
4656 +
4657 +/*
4658 + * EEPROM NIC config
4659 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4660 + */
4661 +#define        EEPROM_NIC                      0x001b
4662 +#define EEPROM_NIC_HW_RADIO            FIELD16(0x0001)
4663 +#define EEPROM_NIC_DYNAMIC_TX_AGC      FIELD16(0x0002)
4664 +#define EEPROM_NIC_EXTERNAL_LNA_BG     FIELD16(0x0004)
4665 +#define EEPROM_NIC_EXTERNAL_LNA_A      FIELD16(0x0008)
4666 +#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0010)
4667 +#define EEPROM_NIC_BW40M_SB_BG         FIELD16(0x0020)
4668 +#define EEPROM_NIC_BW40M_SB_A          FIELD16(0x0040)
4669 +#define EEPROM_NIC_WPS_PBC             FIELD16(0x0080)
4670 +#define EEPROM_NIC_BW40M_BG            FIELD16(0x0100)
4671 +#define EEPROM_NIC_BW40M_A             FIELD16(0x0200)
4672 +
4673 +/*
4674 + * EEPROM frequency
4675 + */
4676 +#define        EEPROM_FREQ                     0x001d
4677 +#define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
4678 +#define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
4679 +#define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
4680 +
4681 +/*
4682 + * EEPROM LED
4683 + * POLARITY_RDY_G: Polarity RDY_G setting.
4684 + * POLARITY_RDY_A: Polarity RDY_A setting.
4685 + * POLARITY_ACT: Polarity ACT setting.
4686 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4687 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4688 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4689 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4690 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4691 + * LED_MODE: Led mode.
4692 + */
4693 +#define EEPROM_LED1                    0x001e
4694 +#define EEPROM_LED2                    0x001f
4695 +#define EEPROM_LED3                    0x0020
4696 +#define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
4697 +#define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
4698 +#define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
4699 +#define EEPROM_LED_POLARITY_GPIO_0     FIELD16(0x0008)
4700 +#define EEPROM_LED_POLARITY_GPIO_1     FIELD16(0x0010)
4701 +#define EEPROM_LED_POLARITY_GPIO_2     FIELD16(0x0020)
4702 +#define EEPROM_LED_POLARITY_GPIO_3     FIELD16(0x0040)
4703 +#define EEPROM_LED_POLARITY_GPIO_4     FIELD16(0x0080)
4704 +#define EEPROM_LED_LED_MODE            FIELD16(0x1f00)
4705 +
4706 +/*
4707 + * EEPROM LNA
4708 + */
4709 +#define EEPROM_LNA                     0x0022
4710 +#define EEPROM_LNA_BG                  FIELD16(0x00ff)
4711 +#define EEPROM_LNA_A0                  FIELD16(0xff00)
4712 +
4713 +/*
4714 + * EEPROM RSSI BG offset
4715 + */
4716 +#define EEPROM_RSSI_BG                 0x0023
4717 +#define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
4718 +#define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
4719 +
4720 +/*
4721 + * EEPROM RSSI BG2 offset
4722 + */
4723 +#define EEPROM_RSSI_BG2                        0x0024
4724 +#define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
4725 +#define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
4726 +
4727 +/*
4728 + * EEPROM RSSI A offset
4729 + */
4730 +#define EEPROM_RSSI_A                  0x0025
4731 +#define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
4732 +#define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
4733 +
4734 +/*
4735 + * EEPROM RSSI A2 offset
4736 + */
4737 +#define EEPROM_RSSI_A2                 0x0026
4738 +#define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
4739 +#define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
4740 +
4741 +/*
4742 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4743 + *     This is delta in 40MHZ.
4744 + * VALUE: Tx Power dalta value (MAX=4)
4745 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4746 + * TXPOWER: Enable:
4747 + */
4748 +#define EEPROM_TXPOWER_DELTA           0x0028
4749 +#define EEPROM_TXPOWER_DELTA_VALUE     FIELD16(0x003f)
4750 +#define EEPROM_TXPOWER_DELTA_TYPE      FIELD16(0x0040)
4751 +#define EEPROM_TXPOWER_DELTA_TXPOWER   FIELD16(0x0080)
4752 +
4753 +/*
4754 + * EEPROM TXPOWER 802.11BG
4755 + */
4756 +#define        EEPROM_TXPOWER_BG1              0x0029
4757 +#define        EEPROM_TXPOWER_BG2              0x0030
4758 +#define EEPROM_TXPOWER_BG_SIZE         7
4759 +#define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
4760 +#define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
4761 +
4762 +/*
4763 + * EEPROM TXPOWER 802.11A
4764 + */
4765 +#define EEPROM_TXPOWER_A1              0x003c
4766 +#define EEPROM_TXPOWER_A2              0x0053
4767 +#define EEPROM_TXPOWER_A_SIZE          6
4768 +#define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
4769 +#define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
4770 +
4771 +/*
4772 + * EEPROM TXpower byrate: 20MHZ power
4773 + */
4774 +#define EEPROM_TXPOWER_BYRATE          0x006f
4775 +
4776 +/*
4777 + * EEPROM BBP.
4778 + */
4779 +#define        EEPROM_BBP_START                0x0078
4780 +#define EEPROM_BBP_SIZE                        16
4781 +#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
4782 +#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
4783 +
4784 +/*
4785 + * MCU mailbox commands.
4786 + */
4787 +#define MCU_SLEEP                      0x30
4788 +#define MCU_WAKEUP                     0x31
4789 +#define MCU_LED                                0x50
4790 +#define MCU_LED_STRENGTH               0x51
4791 +#define MCU_LED_1                      0x52
4792 +#define MCU_LED_2                      0x53
4793 +#define MCU_LED_3                      0x54
4794 +#define MCU_RADAR                      0x60
4795 +#define MCU_BOOT_SIGNAL                        0x72
4796 +
4797 +/*
4798 + * DMA descriptor defines.
4799 + */
4800 +#define TXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
4801 +#define TXINFO_DESC_SIZE               ( 1 * sizeof(__le32) )
4802 +#define TXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4803 +#define RXD_DESC_SIZE                  ( 1 * sizeof(__le32) )
4804 +#define RXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4805 +
4806 +/*
4807 + * TX descriptor format for TX, PRIO and Beacon Ring.
4808 + */
4809 +
4810 +/*
4811 + * Word0
4812 + */
4813 +#define TXD_W0_SD_PTR0                 FIELD32(0xffffffff)
4814 +
4815 +/*
4816 + * Word1
4817 + */
4818 +#define TXD_W1_SD_LEN1                 FIELD32(0x00003fff)
4819 +#define TXD_W1_LAST_SEC1               FIELD32(0x00004000)
4820 +#define TXD_W1_BURST                   FIELD32(0x00008000)
4821 +#define TXD_W1_SD_LEN0                 FIELD32(0x3fff0000)
4822 +#define TXD_W1_LAST_SEC0               FIELD32(0x40000000)
4823 +#define TXD_W1_DMA_DONE                        FIELD32(0x80000000)
4824 +
4825 +/*
4826 + * Word2
4827 + */
4828 +#define TXD_W2_SD_PTR1                 FIELD32(0xffffffff)
4829 +
4830 +/*
4831 + * Word3
4832 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
4833 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4834 + *       0:MGMT, 1:HCCA 2:EDCA
4835 + */
4836 +#define TXD_W3_WIV                     FIELD32(0x01000000)
4837 +#define TXD_W3_QSEL                    FIELD32(0x06000000)
4838 +#define TXD_W3_TCO                     FIELD32(0x20000000)
4839 +#define TXD_W3_UCO                     FIELD32(0x40000000)
4840 +#define TXD_W3_ICO                     FIELD32(0x80000000)
4841 +
4842 +/*
4843 + * TX Info structure
4844 + */
4845 +
4846 +/*
4847 + * Word0
4848 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
4849 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4850 + *       0:MGMT, 1:HCCA 2:EDCA
4851 + * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
4852 + * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
4853 + *               Force USB DMA transmit frame from current selected endpoint
4854 + */
4855 +#define TXINFO_W0_USB_DMA_TX_PKT_LEN   FIELD32(0x0000ffff)
4856 +#define TXINFO_W0_WIV                  FIELD32(0x01000000)
4857 +#define TXINFO_W0_QSEL                 FIELD32(0x06000000)
4858 +#define TXINFO_W0_SW_USE_LAST_ROUND    FIELD32(0x08000000)
4859 +#define TXINFO_W0_USB_DMA_NEXT_VALID   FIELD32(0x40000000)
4860 +#define TXINFO_W0_USB_DMA_TX_BURST     FIELD32(0x80000000)
4861 +
4862 +/*
4863 + * TX WI structure
4864 + */
4865 +
4866 +/*
4867 + * Word0
4868 + * FRAG: 1 To inform TKIP engine this is a fragment.
4869 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4870 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4871 + * BW: Channel bandwidth 20MHz or 40 MHz
4872 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4873 + */
4874 +#define TXWI_W0_FRAG                   FIELD32(0x00000001)
4875 +#define TXWI_W0_MIMO_PS                        FIELD32(0x00000002)
4876 +#define TXWI_W0_CF_ACK                 FIELD32(0x00000004)
4877 +#define TXWI_W0_TS                     FIELD32(0x00000008)
4878 +#define TXWI_W0_AMPDU                  FIELD32(0x00000010)
4879 +#define TXWI_W0_MPDU_DENSITY           FIELD32(0x000000e0)
4880 +#define TXWI_W0_TX_OP                  FIELD32(0x00000300)
4881 +#define TXWI_W0_MCS                    FIELD32(0x007f0000)
4882 +#define TXWI_W0_BW                     FIELD32(0x00800000)
4883 +#define TXWI_W0_SHORT_GI               FIELD32(0x01000000)
4884 +#define TXWI_W0_STBC                   FIELD32(0x06000000)
4885 +#define TXWI_W0_IFS                    FIELD32(0x08000000)
4886 +#define TXWI_W0_PHYMODE                        FIELD32(0xc0000000)
4887 +
4888 +/*
4889 + * Word1
4890 + */
4891 +#define TXWI_W1_ACK                    FIELD32(0x00000001)
4892 +#define TXWI_W1_NSEQ                   FIELD32(0x00000002)
4893 +#define TXWI_W1_BW_WIN_SIZE            FIELD32(0x000000fc)
4894 +#define TXWI_W1_WIRELESS_CLI_ID                FIELD32(0x0000ff00)
4895 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4896 +#define TXWI_W1_PACKETID               FIELD32(0xf0000000)
4897 +
4898 +/*
4899 + * Word2
4900 + */
4901 +#define TXWI_W2_IV                     FIELD32(0xffffffff)
4902 +
4903 +/*
4904 + * Word3
4905 + */
4906 +#define TXWI_W3_EIV                    FIELD32(0xffffffff)
4907 +
4908 +/*
4909 + * RX descriptor format for RX Ring.
4910 + */
4911 +
4912 +/*
4913 + * Word0
4914 + * UNICAST_TO_ME: This RX frame is unicast to me.
4915 + * MULTICAST: This is a multicast frame.
4916 + * BROADCAST: This is a broadcast frame.
4917 + * MY_BSS: this frame belongs to the same BSSID.
4918 + * CRC_ERROR: CRC error.
4919 + * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
4920 + * AMSDU: rx with 802.3 header, not 802.11 header.
4921 + */
4922 +
4923 +#define RXD_W0_BA                      FIELD32(0x00000001)
4924 +#define RXD_W0_DATA                    FIELD32(0x00000002)
4925 +#define RXD_W0_NULLDATA                        FIELD32(0x00000004)
4926 +#define RXD_W0_FRAG                    FIELD32(0x00000008)
4927 +#define RXD_W0_UNICAST_TO_ME           FIELD32(0x00000010)
4928 +#define RXD_W0_MULTICAST               FIELD32(0x00000020)
4929 +#define RXD_W0_BROADCAST               FIELD32(0x00000040)
4930 +#define RXD_W0_MY_BSS                  FIELD32(0x00000080)
4931 +#define RXD_W0_CRC_ERROR               FIELD32(0x00000100)
4932 +#define RXD_W0_CIPHER_ERROR            FIELD32(0x00000600)
4933 +#define RXD_W0_AMSDU                   FIELD32(0x00000800)
4934 +#define RXD_W0_HTC                     FIELD32(0x00001000)
4935 +#define RXD_W0_RSSI                    FIELD32(0x00002000)
4936 +#define RXD_W0_L2PAD                   FIELD32(0x00004000)
4937 +#define RXD_W0_AMPDU                   FIELD32(0x00008000)
4938 +#define RXD_W0_DECRYPTED               FIELD32(0x00010000)
4939 +#define RXD_W0_PLCP_RSSI               FIELD32(0x00020000)
4940 +#define RXD_W0_CIPHER_ALG              FIELD32(0x00040000)
4941 +#define RXD_W0_LAST_AMSDU              FIELD32(0x00080000)
4942 +#define RXD_W0_PLCP_SIGNAL             FIELD32(0xfff00000)
4943 +
4944 +/*
4945 + * RX WI structure
4946 + */
4947 +
4948 +/*
4949 + * Word0
4950 + */
4951 +#define RXWI_W0_WIRELESS_CLI_ID                FIELD32(0x000000ff)
4952 +#define RXWI_W0_KEY_INDEX              FIELD32(0x00000300)
4953 +#define RXWI_W0_BSSID                  FIELD32(0x00001c00)
4954 +#define RXWI_W0_UDF                    FIELD32(0x0000e000)
4955 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4956 +#define RXWI_W0_TID                    FIELD32(0xf0000000)
4957 +
4958 +/*
4959 + * Word1
4960 + */
4961 +#define RXWI_W1_FRAG                   FIELD32(0x0000000f)
4962 +#define RXWI_W1_SEQUENCE               FIELD32(0x0000fff0)
4963 +#define RXWI_W1_MCS                    FIELD32(0x007f0000)
4964 +#define RXWI_W1_BW                     FIELD32(0x00800000)
4965 +#define RXWI_W1_SHORT_GI               FIELD32(0x01000000)
4966 +#define RXWI_W1_STBC                   FIELD32(0x06000000)
4967 +#define RXWI_W1_PHYMODE                        FIELD32(0xc0000000)
4968 +
4969 +/*
4970 + * Word2
4971 + */
4972 +#define RXWI_W2_RSSI0                  FIELD32(0x000000ff)
4973 +#define RXWI_W2_RSSI1                  FIELD32(0x0000ff00)
4974 +#define RXWI_W2_RSSI2                  FIELD32(0x00ff0000)
4975 +
4976 +/*
4977 + * Word3
4978 + */
4979 +#define RXWI_W3_SNR0                   FIELD32(0x000000ff)
4980 +#define RXWI_W3_SNR1                   FIELD32(0x0000ff00)
4981 +
4982 +/*
4983 + * Macro's for converting txpower from EEPROM to mac80211 value
4984 + * and from mac80211 value to register value.
4985 + */
4986 +#define MIN_G_TXPOWER  0
4987 +#define MIN_A_TXPOWER  -7
4988 +#define MAX_G_TXPOWER  31
4989 +#define MAX_A_TXPOWER  15
4990 +#define DEFAULT_TXPOWER        5
4991 +
4992 +#define TXPOWER_G_FROM_DEV(__txpower) \
4993 +       ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4994 +
4995 +#define TXPOWER_G_TO_DEV(__txpower) \
4996 +       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4997 +
4998 +#define TXPOWER_A_FROM_DEV(__txpower) \
4999 +       ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5000 +
5001 +#define TXPOWER_A_TO_DEV(__txpower) \
5002 +       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
5003 +
5004 +#endif /* RT2800USB_H */
5005 --- a/drivers/net/wireless/rt2x00/rt2x00.h
5006 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
5007 @@ -142,6 +142,7 @@ struct rt2x00_chip {
5008  #define RT2860D                0x0681  /* 2.4GHz, 5GHz PCI/CB */
5009  #define RT2890         0x0701  /* 2.4GHz PCIe */
5010  #define RT2890D                0x0781  /* 2.4GHz, 5GHz PCIe */
5011 +#define RT2870         0x1600
5012
5013         u16 rf;
5014         u32 rev;
5015 @@ -780,6 +781,12 @@ struct rt2x00_dev {
5016         u8 freq_offset;
5017
5018         /*
5019 +        * Calibration information (for rt2800usb).
5020 +        */
5021 +       u8 calibration_bw20;
5022 +       u8 calibration_bw40;
5023 +
5024 +       /*
5025          * Low level statistics which will have
5026          * to be kept up to date while device is running.
5027          */