package/mac80211/patches/302-rt2x00-Implement-support-for-rt2800pci.patch

   1 From dda25991ee4dc0a2ebe2e3b50857971fe1d878c4 Mon Sep 17 00:00:00 2001
   2 From: Ivo van Doorn <IvDoorn@gmail.com>
   3 Date: Sat, 10 Jan 2009 11:03:23 +0100
   4 Subject: [PATCH] rt2x00: Implement support for rt2800pci
   5
   6 Add support for the rt2800pci chipset.
   7
   8 Includes various patches from Mattias, Mark and Felix.
   9
  10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
  11 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
  12 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  13 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
  14 ---
  15  drivers/net/wireless/rt2x00/Kconfig     |   15 +
  16  drivers/net/wireless/rt2x00/Makefile    |    1 +
  17  drivers/net/wireless/rt2x00/rt2800pci.c | 2707 +++++++++++++++++++++++++++++++
  18  drivers/net/wireless/rt2x00/rt2800pci.h | 1879 +++++++++++++++++++++
  19  drivers/net/wireless/rt2x00/rt2x00.h    |    4 +
  20  5 files changed, 4606 insertions(+), 0 deletions(-)
  21  create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
  22  create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
  23
  24 --- a/drivers/net/wireless/rt2x00/Makefile
  25 +++ b/drivers/net/wireless/rt2x00/Makefile
  26 @@ -16,5 +16,6 @@ obj-$(CONFIG_RT2X00_LIB_USB)          += rt2x00u
  27  obj-$(CONFIG_RT2400PCI)                        += rt2400pci.o
  28  obj-$(CONFIG_RT2500PCI)                        += rt2500pci.o
  29  obj-$(CONFIG_RT61PCI)                  += rt61pci.o
  30 +obj-$(CONFIG_RT2800PCI)                        += rt2800pci.o
  31  obj-$(CONFIG_RT2500USB)                        += rt2500usb.o
  32  obj-$(CONFIG_RT73USB)                  += rt73usb.o
  33 --- /dev/null
  34 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
  35 @@ -0,0 +1,2707 @@
  36 +/*
  37 +       Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
  38 +       <http://rt2x00.serialmonkey.com>
  39 +
  40 +       This program is free software; you can redistribute it and/or modify
  41 +       it under the terms of the GNU General Public License as published by
  42 +       the Free Software Foundation; either version 2 of the License, or
  43 +       (at your option) any later version.
  44 +
  45 +       This program is distributed in the hope that it will be useful,
  46 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
  47 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  48 +       GNU General Public License for more details.
  49 +
  50 +       You should have received a copy of the GNU General Public License
  51 +       along with this program; if not, write to the
  52 +       Free Software Foundation, Inc.,
  53 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  54 + */
  55 +
  56 +/*
  57 +       Module: rt2800pci
  58 +       Abstract: rt2800pci device specific routines.
  59 +       Supported chipsets: RT2800E & RT2800ED.
  60 + */
  61 +
  62 +#include <linux/crc-ccitt.h>
  63 +#include <linux/delay.h>
  64 +#include <linux/etherdevice.h>
  65 +#include <linux/init.h>
  66 +#include <linux/kernel.h>
  67 +#include <linux/module.h>
  68 +#include <linux/pci.h>
  69 +#include <linux/eeprom_93cx6.h>
  70 +
  71 +#include "rt2x00.h"
  72 +#include "rt2x00pci.h"
  73 +#include "rt2800pci.h"
  74 +
  75 +/*
  76 + * Allow hardware encryption to be disabled.
  77 + */
  78 +static int modparam_nohwcrypt = 0;
  79 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  80 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  81 +
  82 +/*
  83 + * Register access.
  84 + * BBP and RF register require indirect register access,
  85 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  86 + * These indirect registers work with busy bits,
  87 + * and we will try maximal REGISTER_BUSY_COUNT times to access
  88 + * the register while taking a REGISTER_BUSY_DELAY us delay
  89 + * between each attampt. When the busy bit is still set at that time,
  90 + * the access attempt is considered to have failed,
  91 + * and we will print an error.
  92 + */
  93 +#define WAIT_FOR_BBP(__dev, __reg) \
  94 +       rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  95 +#define WAIT_FOR_RF(__dev, __reg) \
  96 +       rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  97 +#define WAIT_FOR_MCU(__dev, __reg) \
  98 +       rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  99 +                              H2M_MAILBOX_CSR_OWNER, (__reg))
 100 +
 101 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
 102 +                               const unsigned int word, const u8 value)
 103 +{
 104 +       u32 reg;
 105 +
 106 +       mutex_lock(&rt2x00dev->csr_mutex);
 107 +
 108 +       /*
 109 +        * Wait until the BBP becomes available, afterwards we
 110 +        * can safely write the new data into the register.
 111 +        */
 112 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 113 +               reg = 0;
 114 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 115 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 116 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 117 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 118 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 119 +
 120 +               rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
 121 +       }
 122 +
 123 +       mutex_unlock(&rt2x00dev->csr_mutex);
 124 +}
 125 +
 126 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
 127 +                              const unsigned int word, u8 *value)
 128 +{
 129 +       u32 reg;
 130 +
 131 +       mutex_lock(&rt2x00dev->csr_mutex);
 132 +
 133 +       /*
 134 +        * Wait until the BBP becomes available, afterwards we
 135 +        * can safely write the read request into the register.
 136 +        * After the data has been written, we wait until hardware
 137 +        * returns the correct value, if at any time the register
 138 +        * doesn't become available in time, reg will be 0xffffffff
 139 +        * which means we return 0xff to the caller.
 140 +        */
 141 +       if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 142 +               reg = 0;
 143 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 144 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 145 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 146 +               rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 147 +
 148 +               rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
 149 +
 150 +               WAIT_FOR_BBP(rt2x00dev, &reg);
 151 +       }
 152 +
 153 +       *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 154 +
 155 +       mutex_unlock(&rt2x00dev->csr_mutex);
 156 +}
 157 +
 158 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
 159 +                              const unsigned int word, const u32 value)
 160 +{
 161 +       u32 reg;
 162 +
 163 +       if (!word)
 164 +               return;
 165 +
 166 +       mutex_lock(&rt2x00dev->csr_mutex);
 167 +
 168 +       /*
 169 +        * Wait until the RF becomes available, afterwards we
 170 +        * can safely write the new data into the register.
 171 +        */
 172 +       if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 173 +               reg = 0;
 174 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 175 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 176 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 177 +               rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 178 +
 179 +               rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
 180 +               rt2x00_rf_write(rt2x00dev, word, value);
 181 +       }
 182 +
 183 +       mutex_unlock(&rt2x00dev->csr_mutex);
 184 +}
 185 +
 186 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 187 +                                 const u8 command, const u8 token,
 188 +                                 const u8 arg0, const u8 arg1)
 189 +{
 190 +       u32 reg;
 191 +
 192 +       mutex_lock(&rt2x00dev->csr_mutex);
 193 +
 194 +       /*
 195 +        * Wait until the MCU becomes available, afterwards we
 196 +        * can safely write the new data into the register.
 197 +        */
 198 +       if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 199 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 200 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 201 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 202 +               rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 203 +               rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 204 +
 205 +               reg = 0;
 206 +               rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 207 +               rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 208 +       }
 209 +
 210 +       mutex_unlock(&rt2x00dev->csr_mutex);
 211 +}
 212 +
 213 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 214 +{
 215 +       struct rt2x00_dev *rt2x00dev = eeprom->data;
 216 +       u32 reg;
 217 +
 218 +       rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 219 +
 220 +       eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 221 +       eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 222 +       eeprom->reg_data_clock =
 223 +           !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 224 +       eeprom->reg_chip_select =
 225 +           !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 226 +}
 227 +
 228 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 229 +{
 230 +       struct rt2x00_dev *rt2x00dev = eeprom->data;
 231 +       u32 reg = 0;
 232 +
 233 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 234 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 235 +       rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 236 +                          !!eeprom->reg_data_clock);
 237 +       rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 238 +                          !!eeprom->reg_chip_select);
 239 +
 240 +       rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 241 +}
 242 +
 243 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
 244 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
 245 +       .owner  = THIS_MODULE,
 246 +       .csr    = {
 247 +               .read           = rt2x00pci_register_read,
 248 +               .write          = rt2x00pci_register_write,
 249 +               .flags          = RT2X00DEBUGFS_OFFSET,
 250 +               .word_base      = CSR_REG_BASE,
 251 +               .word_size      = sizeof(u32),
 252 +               .word_count     = CSR_REG_SIZE / sizeof(u32),
 253 +       },
 254 +       .eeprom = {
 255 +               .read           = rt2x00_eeprom_read,
 256 +               .write          = rt2x00_eeprom_write,
 257 +               .word_base      = EEPROM_BASE,
 258 +               .word_size      = sizeof(u16),
 259 +               .word_count     = EEPROM_SIZE / sizeof(u16),
 260 +       },
 261 +       .bbp    = {
 262 +               .read           = rt2800pci_bbp_read,
 263 +               .write          = rt2800pci_bbp_write,
 264 +               .word_base      = BBP_BASE,
 265 +               .word_size      = sizeof(u8),
 266 +               .word_count     = BBP_SIZE / sizeof(u8),
 267 +       },
 268 +       .rf     = {
 269 +               .read           = rt2x00_rf_read,
 270 +               .write          = rt2800pci_rf_write,
 271 +               .word_base      = RF_BASE,
 272 +               .word_size      = sizeof(u32),
 273 +               .word_count     = RF_SIZE / sizeof(u32),
 274 +       },
 275 +};
 276 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 277 +
 278 +#ifdef CONFIG_RT2X00_LIB_RFKILL
 279 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 280 +{
 281 +       u32 reg;
 282 +
 283 +       rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 284 +       return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 285 +}
 286 +#else
 287 +#define rt2800pci_rfkill_poll  NULL
 288 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
 289 +
 290 +#ifdef CONFIG_RT2X00_LIB_LEDS
 291 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
 292 +                                    enum led_brightness brightness)
 293 +{
 294 +       struct rt2x00_led *led =
 295 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 296 +       unsigned int enabled = brightness != LED_OFF;
 297 +       unsigned int bg_mode =
 298 +           (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 299 +       unsigned int polarity =
 300 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 301 +                                  EEPROM_FREQ_LED_POLARITY);
 302 +       unsigned int ledmode =
 303 +               rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 304 +                                  EEPROM_FREQ_LED_MODE);
 305 +
 306 +       if (led->type == LED_TYPE_RADIO) {
 307 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 308 +                                     enabled ? 0x20 : 0);
 309 +       } else if (led->type == LED_TYPE_ASSOC) {
 310 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 311 +                                     enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 312 +       } else if (led->type == LED_TYPE_QUALITY) {
 313 +               /*
 314 +                * The brightness is divided into 6 levels (0 - 5),
 315 +                * The specs tell us the following levels:
 316 +                *      0, 1 ,3, 7, 15, 31
 317 +                * to determine the level in a simple way we can simply
 318 +                * work with bitshifting:
 319 +                *      (1 << level) - 1
 320 +                */
 321 +               rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 322 +                                     (1 << brightness / (LED_FULL / 6)) - 1,
 323 +                                     polarity);
 324 +       }
 325 +}
 326 +
 327 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
 328 +                              unsigned long *delay_on,
 329 +                              unsigned long *delay_off)
 330 +{
 331 +       struct rt2x00_led *led =
 332 +           container_of(led_cdev, struct rt2x00_led, led_dev);
 333 +       u32 reg;
 334 +
 335 +       rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
 336 +       rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 337 +       rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 338 +       rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 339 +       rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 340 +       rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 341 +       rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 342 +       rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 343 +       rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
 344 +
 345 +       return 0;
 346 +}
 347 +
 348 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
 349 +                              struct rt2x00_led *led,
 350 +                              enum led_type type)
 351 +{
 352 +       led->rt2x00dev = rt2x00dev;
 353 +       led->type = type;
 354 +       led->led_dev.brightness_set = rt2800pci_brightness_set;
 355 +       led->led_dev.blink_set = rt2800pci_blink_set;
 356 +       led->flags = LED_INITIALIZED;
 357 +}
 358 +#endif /* CONFIG_RT2X00_LIB_LEDS */
 359 +
 360 +/*
 361 + * Configuration handlers.
 362 + */
 363 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 364 +                                      struct rt2x00lib_crypto *crypto,
 365 +                                      struct ieee80211_key_conf *key)
 366 +{
 367 +       u32 offset;
 368 +       u32 reg;
 369 +
 370 +       offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
 371 +
 372 +       reg = 0;
 373 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 374 +                          !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 375 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
 376 +                          crypto->cipher);
 377 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 378 +                          (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
 379 +       rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
 380 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 381 +}
 382 +
 383 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 384 +                                      struct rt2x00lib_crypto *crypto,
 385 +                                      struct ieee80211_key_conf *key)
 386 +{
 387 +       struct hw_key_entry key_entry;
 388 +       struct rt2x00_field32 field;
 389 +       u32 offset;
 390 +       u32 mask;
 391 +       u32 reg;
 392 +
 393 +       if (crypto->cmd == SET_KEY) {
 394 +               memcpy(key_entry.key, crypto->key,
 395 +                      sizeof(key_entry.key));
 396 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 397 +                      sizeof(key_entry.tx_mic));
 398 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 399 +                      sizeof(key_entry.rx_mic));
 400 +
 401 +               offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 402 +               rt2x00pci_register_multiwrite(rt2x00dev, offset,
 403 +                                             &key_entry, sizeof(key_entry));
 404 +
 405 +               /*
 406 +                * The driver does not support the IV/EIV generation
 407 +                * in hardware. However it doesn't support the IV/EIV
 408 +                * inside the ieee80211 frame either, but requires it
 409 +                * to be provided seperately for the descriptor.
 410 +                * rt2x00lib will cut the IV/EIV data out of all frames
 411 +                * given to us by mac80211, but we must tell mac80211
 412 +                * to generate the IV/EIV data.
 413 +                */
 414 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 415 +       }
 416 +
 417 +       /*
 418 +        * The cipher types are stored over multiple registers
 419 +        * starting with SHARED_KEY_MODE_BASE each word will have
 420 +        * 32 bits and contains the cipher types for 2 modes each.
 421 +        * Using the correct defines correctly will cause overhead,
 422 +        * so just calculate the correct offset.
 423 +        */
 424 +       mask = key->hw_key_idx % 8;
 425 +       field.bit_offset = (3 * mask);
 426 +       field.bit_mask = 0x7 << field.bit_offset;
 427 +
 428 +       offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 429 +       rt2x00pci_register_read(rt2x00dev, offset, &reg);
 430 +       rt2x00_set_field32(&reg, field,
 431 +                          (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
 432 +       rt2x00pci_register_write(rt2x00dev, offset, reg);
 433 +
 434 +       /*
 435 +        * Update WCID information
 436 +        */
 437 +       rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 438 +
 439 +       return 0;
 440 +}
 441 +
 442 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 443 +                                        struct rt2x00lib_crypto *crypto,
 444 +                                        struct ieee80211_key_conf *key)
 445 +{
 446 +       struct hw_key_entry key_entry;
 447 +       u32 offset;
 448 +
 449 +       /*
 450 +        * 1 pairwise key is possible per AID, this means that the AID
 451 +        * equals our hw_key_idx.
 452 +        */
 453 +       key->hw_key_idx = crypto->aid;
 454 +
 455 +       if (crypto->cmd == SET_KEY) {
 456 +               memcpy(key_entry.key, crypto->key,
 457 +                      sizeof(key_entry.key));
 458 +               memcpy(key_entry.tx_mic, crypto->tx_mic,
 459 +                      sizeof(key_entry.tx_mic));
 460 +               memcpy(key_entry.rx_mic, crypto->rx_mic,
 461 +                      sizeof(key_entry.rx_mic));
 462 +
 463 +               offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 464 +               rt2x00pci_register_multiwrite(rt2x00dev, offset,
 465 +                                             &key_entry, sizeof(key_entry));
 466 +
 467 +               /*
 468 +                * The driver does not support the IV/EIV generation
 469 +                * in hardware. However it doesn't support the IV/EIV
 470 +                * inside the ieee80211 frame either, but requires it
 471 +                * to be provided seperately for the descriptor.
 472 +                * rt2x00lib will cut the IV/EIV data out of all frames
 473 +                * given to us by mac80211, but we must tell mac80211
 474 +                * to generate the IV/EIV data.
 475 +                */
 476 +               key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 477 +       }
 478 +
 479 +       /*
 480 +        * Update WCID information
 481 +        */
 482 +       rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 483 +
 484 +       return 0;
 485 +}
 486 +
 487 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
 488 +                                   const unsigned int filter_flags)
 489 +{
 490 +       u32 reg;
 491 +
 492 +       /*
 493 +        * Start configuration steps.
 494 +        * Note that the version error will always be dropped
 495 +        * and broadcast frames will always be accepted since
 496 +        * there is no filter for it at this time.
 497 +        */
 498 +       rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 499 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 500 +                          !(filter_flags & FIF_FCSFAIL));
 501 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 502 +                          !(filter_flags & FIF_PLCPFAIL));
 503 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 504 +                          !(filter_flags & FIF_PROMISC_IN_BSS));
 505 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD,
 506 +                          !(filter_flags & FIF_OTHER_BSS));
 507 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 508 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 509 +                          !(filter_flags & FIF_ALLMULTI));
 510 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 511 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 512 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 513 +                          !(filter_flags & FIF_CONTROL));
 514 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 515 +                          !(filter_flags & FIF_CONTROL));
 516 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 517 +                          !(filter_flags & FIF_CONTROL));
 518 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 519 +                          !(filter_flags & FIF_CONTROL));
 520 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 521 +                          !(filter_flags & FIF_CONTROL));
 522 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 523 +                          !(filter_flags & FIF_CONTROL));
 524 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 525 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
 526 +       rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 527 +                          !(filter_flags & FIF_CONTROL));
 528 +       rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 529 +}
 530 +
 531 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
 532 +                                 struct rt2x00_intf *intf,
 533 +                                 struct rt2x00intf_conf *conf,
 534 +                                 const unsigned int flags)
 535 +{
 536 +       unsigned int beacon_base;
 537 +       u32 reg;
 538 +
 539 +       if (flags & CONFIG_UPDATE_TYPE) {
 540 +               /*
 541 +                * Clear current synchronisation setup.
 542 +                * For the Beacon base registers we only need to clear
 543 +                * the first byte since that byte contains the VALID and OWNER
 544 +                * bits which (when set to 0) will invalidate the entire beacon.
 545 +                */
 546 +               beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 547 +               rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 548 +
 549 +               /*
 550 +                * Enable synchronisation.
 551 +                */
 552 +               rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 553 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 554 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 555 +               rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 556 +               rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 557 +       }
 558 +
 559 +       if (flags & CONFIG_UPDATE_MAC) {
 560 +               reg = le32_to_cpu(conf->mac[1]);
 561 +               rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 562 +               conf->mac[1] = cpu_to_le32(reg);
 563 +
 564 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 565 +                                             conf->mac, sizeof(conf->mac));
 566 +       }
 567 +
 568 +       if (flags & CONFIG_UPDATE_BSSID) {
 569 +               reg = le32_to_cpu(conf->bssid[1]);
 570 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 571 +               rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 572 +               conf->bssid[1] = cpu_to_le32(reg);
 573 +
 574 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 575 +                                             conf->bssid, sizeof(conf->bssid));
 576 +       }
 577 +}
 578 +
 579 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
 580 +                                struct rt2x00lib_erp *erp)
 581 +{
 582 +       u32 reg;
 583 +
 584 +       rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 585 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
 586 +                          erp->ack_timeout);
 587 +       rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 588 +
 589 +       rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 590 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 591 +                          !!erp->short_preamble);
 592 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 593 +                          !!erp->short_preamble);
 594 +       rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 595 +
 596 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 597 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 598 +                          erp->cts_protection ? 2 : 0);
 599 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 600 +
 601 +       rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 602 +                                erp->basic_rates);
 603 +       rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE,
 604 +                                erp->basic_rates >> 32);
 605 +
 606 +       rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 607 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 608 +       rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 609 +       rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 610 +
 611 +       rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 612 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 613 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 614 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 615 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 616 +       rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 617 +       rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 618 +}
 619 +
 620 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
 621 +                                struct antenna_setup *ant)
 622 +{
 623 +       u16 eeprom;
 624 +       u8 r1;
 625 +       u8 r3;
 626 +
 627 +       /*
 628 +        * FIXME: Use requested antenna configuration.
 629 +        */
 630 +
 631 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 632 +
 633 +       rt2800pci_bbp_read(rt2x00dev, 1, &r1);
 634 +       rt2800pci_bbp_read(rt2x00dev, 3, &r3);
 635 +
 636 +       /*
 637 +        * Configure the TX antenna.
 638 +        */
 639 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
 640 +       case 1:
 641 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 642 +               break;
 643 +       case 2:
 644 +       case 3:
 645 +               /* Do nothing */
 646 +               break;
 647 +       }
 648 +
 649 +       /*
 650 +        * Configure the RX antenna.
 651 +        */
 652 +       switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
 653 +       case 1:
 654 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 655 +               break;
 656 +       case 2:
 657 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 658 +               break;
 659 +       case 3:
 660 +               rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 661 +               break;
 662 +       }
 663 +
 664 +       rt2800pci_bbp_write(rt2x00dev, 3, r3);
 665 +       rt2800pci_bbp_write(rt2x00dev, 1, r1);
 666 +}
 667 +
 668 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 669 +                                     struct rt2x00lib_conf *libconf)
 670 +{
 671 +       u16 eeprom;
 672 +       short lna_gain;
 673 +
 674 +       if (libconf->rf.channel <= 14) {
 675 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 676 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 677 +       } else if (libconf->rf.channel <= 64) {
 678 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 679 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 680 +       } else if (libconf->rf.channel <= 128) {
 681 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 682 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 683 +       } else {
 684 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 685 +               lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 686 +       }
 687 +
 688 +       rt2x00dev->lna_gain = lna_gain;
 689 +}
 690 +
 691 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
 692 +                                    struct rf_channel *rf,
 693 +                                    struct channel_info *info)
 694 +{
 695 +       u32 reg;
 696 +       unsigned int tx_pin;
 697 +       u16 eeprom;
 698 +
 699 +       tx_pin = 0;
 700 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 701 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 702 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 703 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 704 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 705 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 706 +       rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 707 +
 708 +       rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 709 +
 710 +       /*
 711 +        * Determine antenna settings from EEPROM
 712 +        */
 713 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
 714 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
 715 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 716 +               /* Turn off unused PA or LNA when only 1T or 1R */
 717 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
 718 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
 719 +       }
 720 +
 721 +       if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
 722 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 723 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 724 +               /* Turn off unused PA or LNA when only 1T or 1R */
 725 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
 726 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
 727 +       } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
 728 +               rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 729 +
 730 +       if (rf->channel > 14) {
 731 +               /*
 732 +                * When TX power is below 0, we should increase it by 7 to
 733 +                * make it a positive value (Minumum value is -7).
 734 +                * However this means that values between 0 and 7 have
 735 +                * double meaning, and we should set a 7DBm boost flag.
 736 +                */
 737 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 738 +                                  (info->tx_power1 >= 0));
 739 +
 740 +               if (info->tx_power1 < 0)
 741 +                       info->tx_power1 += 7;
 742 +
 743 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 744 +                                  TXPOWER_A_TO_DEV(info->tx_power1));
 745 +
 746 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 747 +                                  (info->tx_power2 >= 0));
 748 +
 749 +               if (info->tx_power2 < 0)
 750 +                       info->tx_power2 += 7;
 751 +
 752 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 753 +                                  TXPOWER_A_TO_DEV(info->tx_power2));
 754 +
 755 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
 756 +       } else {
 757 +               rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 758 +                                  TXPOWER_G_TO_DEV(info->tx_power1));
 759 +               rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 760 +                                  TXPOWER_G_TO_DEV(info->tx_power2));
 761 +
 762 +               rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
 763 +       }
 764 +
 765 +       rt2x00_set_field32(&rf->rf4, RF4_BW40,
 766 +                          test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
 767 +
 768 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 769 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 770 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 771 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 772 +
 773 +       udelay(200);
 774 +
 775 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 776 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 777 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 778 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 779 +
 780 +       udelay(200);
 781 +
 782 +       rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
 783 +       rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
 784 +       rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 785 +       rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
 786 +
 787 +       /*
 788 +        * Change BBP settings
 789 +        */
 790 +       rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 791 +       rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 792 +       rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 793 +       rt2800pci_bbp_write(rt2x00dev, 86, 0);
 794 +
 795 +       if (rf->channel <= 14) {
 796 +               if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 797 +                       rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
 798 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
 799 +               } else {
 800 +                       rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
 801 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
 802 +               }
 803 +
 804 +               rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 805 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
 806 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
 807 +               rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
 808 +       } else {
 809 +               rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
 810 +
 811 +               if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 812 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
 813 +               else
 814 +                       rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
 815 +
 816 +               rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 817 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
 818 +               rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
 819 +               rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
 820 +       }
 821 +
 822 +       rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 823 +
 824 +       msleep(1);
 825 +}
 826 +
 827 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 828 +                                    const int txpower)
 829 +{
 830 +       u32 reg;
 831 +       u32 value = TXPOWER_G_TO_DEV(txpower);
 832 +       u8 r1;
 833 +
 834 +       rt2800pci_bbp_read(rt2x00dev, 1, &r1);
 835 +       rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 836 +       rt2800pci_bbp_write(rt2x00dev, 1, r1);
 837 +
 838 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 839 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 840 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 841 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 842 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 843 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 844 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 845 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 846 +       rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 847 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 848 +
 849 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 850 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 851 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 852 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 853 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 854 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 855 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 856 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 857 +       rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 858 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 859 +
 860 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 861 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 862 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 863 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 864 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 865 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 866 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 867 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 868 +       rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 869 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 870 +
 871 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 872 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 873 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 874 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 875 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 876 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 877 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 878 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 879 +       rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 880 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 881 +
 882 +       rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 883 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 884 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 885 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 886 +       rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 887 +       rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 888 +}
 889 +
 890 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 891 +                                        struct rt2x00lib_conf *libconf)
 892 +{
 893 +       u32 reg;
 894 +
 895 +       rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 896 +       rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 897 +                          libconf->conf->short_frame_max_tx_count);
 898 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 899 +                          libconf->conf->long_frame_max_tx_count);
 900 +       rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 901 +       rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 902 +       rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 903 +       rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 904 +       rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
 905 +}
 906 +
 907 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
 908 +                                     struct rt2x00lib_conf *libconf)
 909 +{
 910 +       u32 reg;
 911 +
 912 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 913 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 914 +                          libconf->conf->beacon_int * 16);
 915 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 916 +}
 917 +
 918 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
 919 +                            struct rt2x00lib_conf *libconf,
 920 +                            const unsigned int flags)
 921 +{
 922 +       /* Always recalculate LNA gain before changing configuration */
 923 +       rt2800pci_config_lna_gain(rt2x00dev, libconf);
 924 +
 925 +       if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 926 +               rt2800pci_config_channel(rt2x00dev, &libconf->rf,
 927 +                                        &libconf->channel);
 928 +       if (flags & IEEE80211_CONF_CHANGE_POWER)
 929 +               rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 930 +       if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 931 +               rt2800pci_config_retry_limit(rt2x00dev, libconf);
 932 +       if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
 933 +               rt2800pci_config_duration(rt2x00dev, libconf);
 934 +}
 935 +
 936 +/*
 937 + * Link tuning
 938 + */
 939 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
 940 +                                struct link_qual *qual)
 941 +{
 942 +       u32 reg;
 943 +
 944 +       /*
 945 +        * Update FCS error count from register.
 946 +        */
 947 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
 948 +       qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
 949 +
 950 +       /*
 951 +        * Update False CCA count from register.
 952 +        */
 953 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
 954 +       qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
 955 +}
 956 +
 957 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
 958 +{
 959 +       if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
 960 +               return 0x2e + rt2x00dev->lna_gain;
 961 +
 962 +       if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
 963 +               return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
 964 +       else
 965 +               return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
 966 +}
 967 +
 968 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 969 +                                    struct link_qual *qual, u8 vgc_level)
 970 +{
 971 +       if (qual->vgc_level != vgc_level) {
 972 +               rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
 973 +               qual->vgc_level = vgc_level;
 974 +               qual->vgc_level_reg = vgc_level;
 975 +       }
 976 +}
 977 +
 978 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 979 +                                 struct link_qual *qual)
 980 +{
 981 +       rt2800pci_set_vgc(rt2x00dev, qual,
 982 +                         rt2800pci_get_default_vgc(rt2x00dev));
 983 +}
 984 +
 985 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 986 +                                struct link_qual *qual, const u32 count)
 987 +{
 988 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C)
 989 +               return;
 990 +
 991 +       /*
 992 +        * When RSSI is better then -80 increase VGC level with 0x10
 993 +        */
 994 +       rt2800pci_set_vgc(rt2x00dev, qual,
 995 +                         rt2800pci_get_default_vgc(rt2x00dev) +
 996 +                         ((qual->rssi > -80) * 0x10));
 997 +}
 998 +
 999 +/*
1000 + * Firmware functions
1001 + */
1002 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1003 +{
1004 +       return FIRMWARE_RT2860;
1005 +}
1006 +
1007 +static u16 rt2800pci_get_firmware_crc(const void *data, const size_t len)
1008 +{
1009 +       u16 crc;
1010 +
1011 +       /*
1012 +        * Use the crc ccitt algorithm.
1013 +        * This will return the same value as the legacy driver which
1014 +        * used bit ordering reversion on the both the firmware bytes
1015 +        * before input input as well as on the final output.
1016 +        * Obviously using crc ccitt directly is much more efficient.
1017 +        * The last 2 bytes in the firmware array are the crc checksum itself,
1018 +        * this means that we should never pass those 2 bytes to the crc
1019 +        * algorithm.
1020 +        */
1021 +       crc = crc_ccitt(~0, data, len - 2);
1022 +
1023 +       /*
1024 +        * There is a small difference between the crc-itu-t + bitrev and
1025 +        * the crc-ccitt crc calculation. In the latter method the 2 bytes
1026 +        * will be swapped, use swab16 to convert the crc to the correct
1027 +        * value.
1028 +        */
1029 +       return swab16(crc);
1030 +}
1031 +
1032 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1033 +                                  const void *data, const size_t len)
1034 +{
1035 +       unsigned int i;
1036 +       u32 reg;
1037 +
1038 +       /*
1039 +        * Wait for stable hardware.
1040 +        */
1041 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1042 +               rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1043 +               if (reg && reg != ~0)
1044 +                       break;
1045 +               msleep(1);
1046 +       }
1047 +
1048 +       if (i == REGISTER_BUSY_COUNT) {
1049 +               ERROR(rt2x00dev, "Unstable hardware.\n");
1050 +               return -EBUSY;
1051 +       }
1052 +
1053 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1054 +       rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1055 +
1056 +       /*
1057 +        * Disable DMA, will be reenabled later when enabling
1058 +        * the radio.
1059 +        */
1060 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1061 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1062 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1063 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1064 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1065 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1066 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1067 +
1068 +       /*
1069 +        * enable Host program ram write selection
1070 +        */
1071 +       reg = 0;
1072 +       rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1073 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1074 +
1075 +       /*
1076 +        * Write firmware to device.
1077 +        */
1078 +       rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1079 +                                     data, len);
1080 +
1081 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1082 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1083 +
1084 +       /*
1085 +        * Wait for device to stabilize.
1086 +        */
1087 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1088 +               rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1089 +               if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1090 +                       break;
1091 +               msleep(1);
1092 +       }
1093 +
1094 +       if (i == REGISTER_BUSY_COUNT) {
1095 +               ERROR(rt2x00dev, "PBF system register not ready.\n");
1096 +               return -EBUSY;
1097 +       }
1098 +
1099 +       /*
1100 +        * Disable interrupts
1101 +        */
1102 +       rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1103 +
1104 +       /*
1105 +        * Initialize BBP R/W access agent
1106 +        */
1107 +       rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1108 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1109 +
1110 +       return 0;
1111 +}
1112 +
1113 +/*
1114 + * Initialization functions.
1115 + */
1116 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1117 +{
1118 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1119 +       u32 word;
1120 +
1121 +       if (entry->queue->qid == QID_RX) {
1122 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1123 +
1124 +               return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1125 +       } else {
1126 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1127 +
1128 +               return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1129 +       }
1130 +}
1131 +
1132 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1133 +{
1134 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1135 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1136 +       u32 word;
1137 +
1138 +       if (entry->queue->qid == QID_RX) {
1139 +               rt2x00_desc_read(entry_priv->desc, 0, &word);
1140 +               rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1141 +               rt2x00_desc_write(entry_priv->desc, 0, word);
1142 +
1143 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1144 +               rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1145 +               rt2x00_desc_write(entry_priv->desc, 1, word);
1146 +       } else {
1147 +               rt2x00_desc_read(entry_priv->desc, 1, &word);
1148 +               rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1149 +               rt2x00_desc_write(entry_priv->desc, 1, word);
1150 +       }
1151 +}
1152 +
1153 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1154 +{
1155 +       struct queue_entry_priv_pci *entry_priv;
1156 +       u32 reg;
1157 +
1158 +       /*
1159 +        * Initialize registers.
1160 +        */
1161 +       entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1162 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1163 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1164 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1165 +
1166 +       entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1167 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1168 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1169 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1170 +
1171 +       entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1172 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1173 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1174 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1175 +
1176 +       entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1177 +       rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1178 +       rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1179 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1180 +
1181 +       entry_priv = rt2x00dev->rx->entries[0].priv_data;
1182 +       rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1183 +       rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1184 +       rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1185 +
1186 +       /*
1187 +        * Enable global DMA configuration
1188 +        */
1189 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1190 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1191 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1192 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1193 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1194 +
1195 +       rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1196 +
1197 +       return 0;
1198 +}
1199 +
1200 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1201 +{
1202 +       u32 reg;
1203 +       unsigned int i;
1204 +
1205 +       rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1206 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1207 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1208 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1209 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1210 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1211 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1212 +       rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1213 +       rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1214 +
1215 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1216 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1217 +
1218 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1219 +
1220 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1221 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1222 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1223 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1224 +
1225 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1226 +
1227 +       rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1228 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1229 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1230 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1231 +       rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1232 +       rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1233 +
1234 +       rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1235 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1236 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1237 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1238 +       rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1239 +       rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1240 +
1241 +       rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1242 +       rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1243 +
1244 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1245 +
1246 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1247 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1248 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1249 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1250 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1251 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1252 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1253 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1254 +
1255 +       rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1256 +       rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1257 +
1258 +       rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1259 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1260 +       rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1261 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1262 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1263 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1264 +       rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1265 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1266 +       rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1267 +       rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1268 +
1269 +       rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1270 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1271 +       rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1272 +       rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1273 +
1274 +       rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1275 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1276 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1277 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1278 +       rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1279 +       rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1280 +
1281 +       rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1282 +
1283 +       rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1284 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1285 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1286 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1287 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1288 +       rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1289 +       rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1290 +
1291 +       rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1292 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1293 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1294 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1295 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1296 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1297 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1298 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1299 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1300 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1301 +       rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1302 +
1303 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1304 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1305 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1306 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1307 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1308 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1309 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1310 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1311 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1312 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1313 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1314 +
1315 +       rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1316 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1317 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1318 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1319 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1320 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1321 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1322 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1323 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1324 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1325 +       rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1326 +
1327 +       rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1328 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1329 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1330 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1331 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1332 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1333 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1334 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1335 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1336 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1337 +       rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1338 +
1339 +       rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1340 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1341 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1342 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1343 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1344 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1345 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1346 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1347 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1348 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1349 +       rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1350 +
1351 +       rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1352 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1353 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1354 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1355 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1356 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1357 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1358 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1359 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1360 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1361 +       rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1362 +
1363 +       rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1364 +       rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1365 +
1366 +       rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1367 +       rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1368 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1369 +       rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1370 +
1371 +       rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1372 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1373 +
1374 +       /*
1375 +        * ASIC will keep garbage value after boot, clear encryption keys.
1376 +        */
1377 +       for (i = 0; i < 254; i++) {
1378 +               u32 wcid[2] = { 0xffffffff, 0x0000ffff };
1379 +               rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1380 +                                             wcid, sizeof(wcid));
1381 +       }
1382 +
1383 +       for (i = 0; i < 4; i++)
1384 +               rt2x00pci_register_write(rt2x00dev,
1385 +                                        SHARED_KEY_MODE_ENTRY(i), 0);
1386 +
1387 +       for (i = 0; i < 256; i++)
1388 +               rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1389 +
1390 +       /*
1391 +        * Clear all beacons
1392 +        * For the Beacon base registers we only need to clear
1393 +        * the first byte since that byte contains the VALID and OWNER
1394 +        * bits which (when set to 0) will invalidate the entire beacon.
1395 +        */
1396 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1397 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1398 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1399 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1400 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1401 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1402 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1403 +       rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1404 +
1405 +       rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1406 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1407 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1408 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1409 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1410 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1411 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1412 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1413 +       rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1414 +       rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1415 +
1416 +       rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1417 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1418 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1419 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1420 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1421 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1422 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1423 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1424 +       rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1425 +       rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1426 +
1427 +       rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1428 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1429 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1430 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1431 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1432 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1433 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1434 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1435 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1436 +       rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1437 +
1438 +       rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1439 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1440 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1441 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1442 +       rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1443 +       rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1444 +
1445 +       /*
1446 +        * We must clear the error counters.
1447 +        * These registers are cleared on read,
1448 +        * so we may pass a useless variable to store the value.
1449 +        */
1450 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1451 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1452 +       rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1453 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1454 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1455 +       rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1456 +
1457 +       return 0;
1458 +}
1459 +
1460 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1461 +{
1462 +       unsigned int i;
1463 +       u32 reg;
1464 +
1465 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1466 +               rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1467 +               if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1468 +                       return 0;
1469 +
1470 +               udelay(REGISTER_BUSY_DELAY);
1471 +       }
1472 +
1473 +       ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1474 +       return -EACCES;
1475 +}
1476 +
1477 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1478 +{
1479 +       unsigned int i;
1480 +       u8 value;
1481 +
1482 +       /*
1483 +        * BBP was enabled after firmware was loaded,
1484 +        * but we need to reactivate it now.
1485 +        */
1486 +       rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0x00000000);
1487 +       rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0x00000000);
1488 +       msleep(1);
1489 +
1490 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1491 +               rt2800pci_bbp_read(rt2x00dev, 0, &value);
1492 +               if ((value != 0xff) && (value != 0x00))
1493 +                       return 0;
1494 +               udelay(REGISTER_BUSY_DELAY);
1495 +       }
1496 +
1497 +       ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1498 +       return -EACCES;
1499 +}
1500 +
1501 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1502 +{
1503 +       unsigned int i;
1504 +       u16 eeprom;
1505 +       u8 reg_id;
1506 +       u8 value;
1507 +
1508 +       if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1509 +                    rt2800pci_wait_bbp_ready(rt2x00dev)))
1510 +               return -EACCES;
1511 +
1512 +       rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1513 +       rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1514 +       rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1515 +       rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1516 +       rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1517 +       rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1518 +       rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1519 +       rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1520 +       rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1521 +       rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1522 +       rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1523 +       rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1524 +       rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1525 +       rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1526 +
1527 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_C) {
1528 +               rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1529 +               rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1530 +       }
1531 +
1532 +       if (rt2x00_rev(&rt2x00dev->chip) == RT2860_VERSION_D)
1533 +               rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1534 +
1535 +       for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1536 +               rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1537 +
1538 +               if (eeprom != 0xffff && eeprom != 0x0000) {
1539 +                       reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1540 +                       value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1541 +                       rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1542 +               }
1543 +       }
1544 +
1545 +       return 0;
1546 +}
1547 +
1548 +/*
1549 + * Device state switch handlers.
1550 + */
1551 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1552 +                               enum dev_state state)
1553 +{
1554 +       u32 reg;
1555 +
1556 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1557 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1558 +                          (state == STATE_RADIO_RX_ON) ||
1559 +                          (state == STATE_RADIO_RX_ON_LINK));
1560 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1561 +}
1562 +
1563 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1564 +                                enum dev_state state)
1565 +{
1566 +       int mask = (state == STATE_RADIO_IRQ_ON);
1567 +       u32 reg;
1568 +
1569 +       /*
1570 +        * When interrupts are being enabled, the interrupt registers
1571 +        * should clear the register to assure a clean state.
1572 +        */
1573 +       if (state == STATE_RADIO_IRQ_ON) {
1574 +               rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1575 +               rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1576 +       }
1577 +
1578 +       rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1579 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1580 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1581 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1582 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1583 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1584 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1585 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1586 +       rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1587 +       rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1588 +       rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1589 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1590 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1591 +       rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1592 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1593 +       rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1594 +       rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1595 +       rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1596 +       rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1597 +       rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1598 +}
1599 +
1600 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1601 +{
1602 +       unsigned int i;
1603 +       u32 reg;
1604 +
1605 +       for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1606 +               rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1607 +               if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1608 +                   !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1609 +                       return 0;
1610 +
1611 +               msleep(1);
1612 +       }
1613 +
1614 +       ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1615 +       return -EACCES;
1616 +}
1617 +
1618 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1619 +{
1620 +       u32 reg;
1621 +       u16 word;
1622 +
1623 +       /*
1624 +        * Initialize all registers.
1625 +        */
1626 +       if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1627 +                    rt2800pci_init_queues(rt2x00dev) ||
1628 +                    rt2800pci_init_registers(rt2x00dev) ||
1629 +                    rt2800pci_init_bbp(rt2x00dev)))
1630 +               return -EIO;
1631 +
1632 +       /*
1633 +        * Send signal to firmware during boot time.
1634 +        */
1635 +       rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1636 +
1637 +       /* Wait for DMA, ignore error */
1638 +       rt2800pci_wait_wpdma_ready(rt2x00dev);
1639 +
1640 +       /*
1641 +        * Enable RX.
1642 +        */
1643 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1644 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1645 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1646 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
1647 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1648 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1649 +
1650 +       rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1651 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1652 +       rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1653 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1654 +
1655 +       /*
1656 +        * Initialize LED control
1657 +        */
1658 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1659 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1660 +                             word & 0xff, (word >> 8) & 0xff);
1661 +
1662 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1663 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1664 +                             word & 0xff, (word >> 8) & 0xff);
1665 +
1666 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1667 +       rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1668 +                             word & 0xff, (word >> 8) & 0xff);
1669 +
1670 +       return 0;
1671 +}
1672 +
1673 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1674 +{
1675 +       u32 reg;
1676 +
1677 +       rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1678 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1679 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1680 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1681 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1682 +       rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1683 +       rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1684 +
1685 +       rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1686 +       rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1687 +       rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1688 +
1689 +       rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1690 +
1691 +       /* Wait for DMA, ignore error */
1692 +       rt2800pci_wait_wpdma_ready(rt2x00dev);
1693 +}
1694 +
1695 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1696 +                              enum dev_state state)
1697 +{
1698 +       rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1699 +
1700 +       if (state == STATE_AWAKE)
1701 +               rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1702 +       else
1703 +               rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1704 +
1705 +       return 0;
1706 +}
1707 +
1708 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1709 +                                     enum dev_state state)
1710 +{
1711 +       int retval = 0;
1712 +
1713 +       switch (state) {
1714 +       case STATE_RADIO_ON:
1715 +               /*
1716 +                * Before the radio can be enabled, the device first has
1717 +                * to be woken up. After that it needs a bit of time
1718 +                * to be fully awake and the radio can be enabled.
1719 +                */
1720 +               rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1721 +               msleep(1);
1722 +               retval = rt2800pci_enable_radio(rt2x00dev);
1723 +               break;
1724 +       case STATE_RADIO_OFF:
1725 +               /*
1726 +                * After the radio has been disablee, the device should
1727 +                * be put to sleep for powersaving.
1728 +                */
1729 +               rt2800pci_disable_radio(rt2x00dev);
1730 +               rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1731 +               break;
1732 +       case STATE_RADIO_RX_ON:
1733 +       case STATE_RADIO_RX_ON_LINK:
1734 +       case STATE_RADIO_RX_OFF:
1735 +       case STATE_RADIO_RX_OFF_LINK:
1736 +               rt2800pci_toggle_rx(rt2x00dev, state);
1737 +               break;
1738 +       case STATE_RADIO_IRQ_ON:
1739 +       case STATE_RADIO_IRQ_OFF:
1740 +               rt2800pci_toggle_irq(rt2x00dev, state);
1741 +               break;
1742 +       case STATE_DEEP_SLEEP:
1743 +       case STATE_SLEEP:
1744 +       case STATE_STANDBY:
1745 +       case STATE_AWAKE:
1746 +               retval = rt2800pci_set_state(rt2x00dev, state);
1747 +               break;
1748 +       default:
1749 +               retval = -ENOTSUPP;
1750 +               break;
1751 +       }
1752 +
1753 +       if (unlikely(retval))
1754 +               ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1755 +                     state, retval);
1756 +
1757 +       return retval;
1758 +}
1759 +
1760 +/*
1761 + * TX descriptor initialization
1762 + */
1763 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1764 +                                   struct sk_buff *skb,
1765 +                                   struct txentry_desc *txdesc)
1766 +{
1767 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1768 +       __le32 *txd = skbdesc->desc;
1769 +       __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1770 +       u32 word;
1771 +
1772 +       /*
1773 +        * Initialize TX Info descriptor
1774 +        */
1775 +       rt2x00_desc_read(txwi, 0, &word);
1776 +       rt2x00_set_field32(&word, TXWI_W0_FRAG,
1777 +                          test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1778 +                          test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1779 +       rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1780 +       rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1781 +       rt2x00_set_field32(&word, TXWI_W0_TS,
1782 +                          test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1783 +       rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1784 +                          test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1785 +       rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1786 +       rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1787 +       rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1788 +       rt2x00_set_field32(&word, TXWI_W0_BW,
1789 +                          test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1790 +       rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1791 +                          test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1792 +       rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1793 +       rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1794 +       rt2x00_desc_write(txwi, 0, word);
1795 +
1796 +       rt2x00_desc_read(txwi, 1, &word);
1797 +       rt2x00_set_field32(&word, TXWI_W1_ACK,
1798 +                          test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1799 +       rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1800 +                          test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1801 +       rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1802 +       rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1803 +                          skbdesc->entry->entry_idx);
1804 +       rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1805 +       rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1806 +                          skbdesc->entry->queue->qid);
1807 +       rt2x00_desc_write(txwi, 1, word);
1808 +
1809 +       if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1810 +               _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
1811 +               _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
1812 +       }
1813 +
1814 +       /*
1815 +        * Initialize TX descriptor
1816 +        */
1817 +       rt2x00_desc_read(txd, 0, &word);
1818 +       rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1819 +       rt2x00_desc_write(txd, 0, word);
1820 +
1821 +       rt2x00_desc_read(txd, 1, &word);
1822 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1823 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1824 +       rt2x00_set_field32(&word, TXD_W1_BURST,
1825 +                          test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1826 +       rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1827 +                          rt2x00dev->hw->extra_tx_headroom);
1828 +       rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1829 +                          !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1830 +       rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1831 +       rt2x00_desc_write(txd, 1, word);
1832 +
1833 +       rt2x00_desc_read(txd, 2, &word);
1834 +       rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1835 +                          skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1836 +       rt2x00_desc_write(txd, 2, word);
1837 +
1838 +       rt2x00_desc_read(txd, 3, &word);
1839 +       rt2x00_set_field32(&word, TXD_W3_WIV, 1);
1840 +       rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1841 +       rt2x00_desc_write(txd, 3, word);
1842 +}
1843 +
1844 +/*
1845 + * TX data initialization
1846 + */
1847 +static void rt2800pci_write_beacon(struct queue_entry *entry)
1848 +{
1849 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1850 +       struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1851 +       unsigned int beacon_base;
1852 +       u32 reg;
1853 +
1854 +       /*
1855 +        * Disable beaconing while we are reloading the beacon data,
1856 +        * otherwise we might be sending out invalid data.
1857 +        */
1858 +       rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1859 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1860 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1861 +       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1862 +       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1863 +
1864 +       /*
1865 +        * Write entire beacon with descriptor to register.
1866 +        */
1867 +       beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1868 +       rt2x00pci_register_multiwrite(rt2x00dev,
1869 +                                     beacon_base,
1870 +                                     skbdesc->desc, skbdesc->desc_len);
1871 +       rt2x00pci_register_multiwrite(rt2x00dev,
1872 +                                     beacon_base + skbdesc->desc_len,
1873 +                                     entry->skb->data, entry->skb->len);
1874 +
1875 +       /*
1876 +        * Clean up beacon skb.
1877 +        */
1878 +       dev_kfree_skb_any(entry->skb);
1879 +       entry->skb = NULL;
1880 +}
1881 +
1882 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1883 +                                   const enum data_queue_qid queue_idx)
1884 +{
1885 +       struct data_queue *queue;
1886 +       unsigned int idx, qidx = 0;
1887 +       u32 reg;
1888 +
1889 +       if (queue_idx == QID_BEACON) {
1890 +               rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1891 +               if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1892 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1893 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1894 +                       rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1895 +                       rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1896 +               }
1897 +               return;
1898 +       }
1899 +
1900 +       if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
1901 +               return;
1902 +
1903 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1904 +       idx = queue->index[Q_INDEX];
1905 +
1906 +       if (queue_idx == QID_MGMT)
1907 +               qidx = 5;
1908 +       else
1909 +               qidx = queue_idx;
1910 +
1911 +       rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
1912 +}
1913 +
1914 +/*
1915 + * RX control handlers
1916 + */
1917 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
1918 +                                 struct rxdone_entry_desc *rxdesc)
1919 +{
1920 +       struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1921 +       struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1922 +       __le32 *rxd = entry_priv->desc;
1923 +       __le32 *rxwi = (__le32 *)entry->skb->data;
1924 +       u32 rxd3;
1925 +       u32 rxwi0;
1926 +       u32 rxwi1;
1927 +       u32 rxwi2;
1928 +       u32 rxwi3;
1929 +
1930 +       rt2x00_desc_read(rxd, 3, &rxd3);
1931 +       rt2x00_desc_read(rxwi, 0, &rxwi0);
1932 +       rt2x00_desc_read(rxwi, 1, &rxwi1);
1933 +       rt2x00_desc_read(rxwi, 2, &rxwi2);
1934 +       rt2x00_desc_read(rxwi, 3, &rxwi3);
1935 +
1936 +       if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
1937 +               rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1938 +
1939 +       if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1940 +               /*
1941 +                * Unfortunately we don't know the cipher type used during
1942 +                * decryption. This prevents us from correct providing
1943 +                * correct statistics through debugfs.
1944 +                */
1945 +               rxdesc->cipher = CIPHER_NONE;
1946 +               rxdesc->cipher_status =
1947 +                   rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
1948 +       }
1949 +
1950 +       if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
1951 +               /*
1952 +                * Hardware has stripped IV/EIV data from 802.11 frame during
1953 +                * decryption. Unfortunately the descriptor doesn't contain
1954 +                * any fields with the EIV/IV data either, so they can't
1955 +                * be restored by rt2x00lib.
1956 +                */
1957 +               rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1958 +
1959 +               if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1960 +                       rxdesc->flags |= RX_FLAG_DECRYPTED;
1961 +               else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1962 +                       rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1963 +       }
1964 +
1965 +       if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
1966 +               rxdesc->dev_flags |= RXDONE_MY_BSS;
1967 +
1968 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
1969 +               rxdesc->flags |= RX_FLAG_SHORT_GI;
1970 +
1971 +       if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
1972 +               rxdesc->flags |= RX_FLAG_40MHZ;
1973 +
1974 +       /*
1975 +        * Detect RX rate, always use MCS as signal type.
1976 +        */
1977 +       rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
1978 +       rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
1979 +       rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
1980 +
1981 +       /*
1982 +        * Mask of 0x8 bit to remove the short preamble flag.
1983 +        */
1984 +       if (rxdesc->dev_flags == RATE_MODE_CCK)
1985 +               rxdesc->signal &= ~0x8;
1986 +
1987 +       rxdesc->rssi =
1988 +           (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
1989 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
1990 +            rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
1991 +
1992 +       rxdesc->noise =
1993 +           (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
1994 +            rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
1995 +
1996 +       rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
1997 +
1998 +       /*
1999 +        * Remove TXWI descriptor from start of buffer.
2000 +        */
2001 +       skb_pull(entry->skb, TXWI_DESC_SIZE);
2002 +       skb_trim(entry->skb, rxdesc->size);
2003 +}
2004 +
2005 +/*
2006 + * Interrupt functions.
2007 + */
2008 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2009 +{
2010 +       struct data_queue *queue;
2011 +       struct queue_entry *entry;
2012 +       struct queue_entry *entry_done;
2013 +       struct queue_entry_priv_pci *entry_priv;
2014 +       struct txdone_entry_desc txdesc;
2015 +       u32 word;
2016 +       u32 reg;
2017 +       u32 old_reg;
2018 +       int type;
2019 +       int index;
2020 +
2021 +       /*
2022 +        * During each loop we will compare the freshly read
2023 +        * TX_STA_FIFO register value with the value read from
2024 +        * the previous loop. If the 2 values are equal then
2025 +        * we should stop processing because the chance it
2026 +        * quite big that the device has been unplugged and
2027 +        * we risk going into an endless loop.
2028 +        */
2029 +       old_reg = 0;
2030 +
2031 +       while (1) {
2032 +               rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2033 +               if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2034 +                       break;
2035 +
2036 +               if (old_reg == reg)
2037 +                       break;
2038 +               old_reg = reg;
2039 +
2040 +               /*
2041 +                * Skip this entry when it contains an invalid
2042 +                * queue identication number.
2043 +                */
2044 +               type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2045 +               queue = rt2x00queue_get_queue(rt2x00dev, type);
2046 +               if (unlikely(!queue))
2047 +                       continue;
2048 +
2049 +               /*
2050 +                * Skip this entry when it contains an invalid
2051 +                * index number.
2052 +                */
2053 +               index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2054 +               if (unlikely(index >= queue->limit))
2055 +                       continue;
2056 +
2057 +               entry = &queue->entries[index];
2058 +               entry_priv = entry->priv_data;
2059 +               rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2060 +
2061 +               entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2062 +               while (entry != entry_done) {
2063 +                       /*
2064 +                        * Catch up.
2065 +                        * Just report any entries we missed as failed.
2066 +                        */
2067 +                       WARNING(rt2x00dev,
2068 +                               "TX status report missed for entry %d\n",
2069 +                               entry_done->entry_idx);
2070 +
2071 +                       txdesc.flags = 0;
2072 +                       __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2073 +                       txdesc.retry = 0;
2074 +
2075 +                       rt2x00lib_txdone(entry_done, &txdesc);
2076 +                       entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2077 +               }
2078 +
2079 +               /*
2080 +                * Obtain the status about this packet.
2081 +                */
2082 +               txdesc.flags = 0;
2083 +               if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2084 +                       __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2085 +               else
2086 +                       __set_bit(TXDONE_FAILURE, &txdesc.flags);
2087 +               txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2088 +
2089 +               rt2x00lib_txdone(entry, &txdesc);
2090 +       }
2091 +}
2092 +
2093 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2094 +{
2095 +       struct rt2x00_dev *rt2x00dev = dev_instance;
2096 +       u32 reg;
2097 +
2098 +       /* Read status and ACK all interrupts */
2099 +       rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2100 +       rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2101 +
2102 +       if (!reg)
2103 +               return IRQ_NONE;
2104 +
2105 +       if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2106 +               return IRQ_HANDLED;
2107 +
2108 +       /*
2109 +        * 1 - Rx ring done interrupt.
2110 +        */
2111 +       if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2112 +               rt2x00pci_rxdone(rt2x00dev);
2113 +
2114 +       if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2115 +               rt2800pci_txdone(rt2x00dev);
2116 +
2117 +       return IRQ_HANDLED;
2118 +}
2119 +
2120 +/*
2121 + * Device probe functions.
2122 + */
2123 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2124 +{
2125 +       struct eeprom_93cx6 eeprom;
2126 +       u32 reg;
2127 +       u16 word;
2128 +       u8 *mac;
2129 +       u8 default_lna_gain;
2130 +
2131 +       rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2132 +
2133 +       eeprom.data = rt2x00dev;
2134 +       eeprom.register_read = rt2800pci_eepromregister_read;
2135 +       eeprom.register_write = rt2800pci_eepromregister_write;
2136 +       eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2137 +           PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2138 +       eeprom.reg_data_in = 0;
2139 +       eeprom.reg_data_out = 0;
2140 +       eeprom.reg_data_clock = 0;
2141 +       eeprom.reg_chip_select = 0;
2142 +
2143 +       eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2144 +                              EEPROM_SIZE / sizeof(u16));
2145 +
2146 +       /*
2147 +        * Start validation of the data that has been read.
2148 +        */
2149 +       mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2150 +       if (!is_valid_ether_addr(mac)) {
2151 +               DECLARE_MAC_BUF(macbuf);
2152 +
2153 +               random_ether_addr(mac);
2154 +               EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2155 +       }
2156 +
2157 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2158 +       if (word == 0xffff) {
2159 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2160 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2161 +               rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2162 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2163 +               EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2164 +       }
2165 +
2166 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2167 +       if (word != 0) {
2168 +               /* NIC configuration must always be 0. */
2169 +               word = 0;
2170 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2171 +               EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2172 +       }
2173 +
2174 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2175 +       if ((word & 0x00ff) == 0x00ff) {
2176 +               rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2177 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2178 +                                  LED_MODE_TXRX_ACTIVITY);
2179 +               rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2180 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2181 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2182 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2183 +               rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2184 +               EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2185 +       }
2186 +
2187 +       /*
2188 +        * During the LNA validation we are going to use
2189 +        * lna0 as correct value. Note that EEPROM_LNA
2190 +        * is never validated.
2191 +        */
2192 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2193 +       default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2194 +
2195 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2196 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2197 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2198 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2199 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2200 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2201 +
2202 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2203 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2204 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2205 +       if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2206 +           rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2207 +               rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2208 +                                  default_lna_gain);
2209 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2210 +
2211 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2212 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2213 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2214 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2215 +               rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2216 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2217 +
2218 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2219 +       if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2220 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2221 +       if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2222 +           rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2223 +               rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2224 +                                  default_lna_gain);
2225 +       rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2226 +
2227 +       return 0;
2228 +}
2229 +
2230 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2231 +{
2232 +       u32 reg;
2233 +       u16 value;
2234 +       u16 eeprom;
2235 +       u16 device;
2236 +
2237 +       /*
2238 +        * Read EEPROM word for configuration.
2239 +        */
2240 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2241 +
2242 +       /*
2243 +        * Identify RF chipset.
2244 +        * To determine the RT chip we have to read the
2245 +        * PCI header of the device.
2246 +        */
2247 +       pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2248 +                            PCI_CONFIG_HEADER_DEVICE, &device);
2249 +       value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2250 +       rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2251 +       reg = rt2x00_get_field32(reg, MAC_CSR0_ASIC_REV);
2252 +       rt2x00_set_chip(rt2x00dev, device, value, reg);
2253 +
2254 +       if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2255 +           !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2256 +           !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2257 +           !rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2258 +               ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2259 +               return -ENODEV;
2260 +       }
2261 +
2262 +       /*
2263 +        * Read frequency offset and RF programming sequence.
2264 +        */
2265 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2266 +       rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2267 +
2268 +       /*
2269 +        * Read external LNA informations.
2270 +        */
2271 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2272 +
2273 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2274 +               __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2275 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2276 +               __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2277 +
2278 +       /*
2279 +        * Detect if this device has an hardware controlled radio.
2280 +        */
2281 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2282 +       if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2283 +               __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2284 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2285 +
2286 +       /*
2287 +        * Store led settings, for correct led behaviour.
2288 +        */
2289 +#ifdef CONFIG_RT2X00_LIB_LEDS
2290 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2291 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2292 +       rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2293 +
2294 +       rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2295 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2296 +
2297 +       return 0;
2298 +}
2299 +
2300 +/*
2301 + * RF value list for rt2860
2302 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2303 + */
2304 +static const struct rf_channel rf_vals[] = {
2305 +       { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2306 +       { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2307 +       { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2308 +       { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2309 +       { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2310 +       { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2311 +       { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2312 +       { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2313 +       { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2314 +       { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2315 +       { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2316 +       { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2317 +       { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2318 +       { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2319 +
2320 +       /* 802.11 UNI / HyperLan 2 */
2321 +       { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2322 +       { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2323 +       { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2324 +       { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2325 +       { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2326 +       { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2327 +       { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2328 +       { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2329 +       { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2330 +       { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2331 +       { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2332 +       { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2333 +
2334 +       /* 802.11 HyperLan 2 */
2335 +       { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2336 +       { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2337 +       { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2338 +       { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2339 +       { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2340 +       { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2341 +       { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2342 +       { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2343 +       { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2344 +       { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2345 +       { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2346 +       { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2347 +       { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2348 +       { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2349 +       { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2350 +       { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2351 +
2352 +       /* 802.11 UNII */
2353 +       { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2354 +       { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2355 +       { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2356 +       { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2357 +       { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2358 +       { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2359 +       { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2360 +
2361 +       /* 802.11 Japan */
2362 +       { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2363 +       { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2364 +       { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2365 +       { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2366 +       { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2367 +       { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2368 +       { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2369 +};
2370 +
2371 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2372 +{
2373 +       struct hw_mode_spec *spec = &rt2x00dev->spec;
2374 +       struct channel_info *info;
2375 +       char *tx_power1;
2376 +       char *tx_power2;
2377 +       unsigned int i;
2378 +
2379 +       /*
2380 +        * Initialize all hw fields.
2381 +        */
2382 +       rt2x00dev->hw->flags =
2383 +           IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2384 +           IEEE80211_HW_SIGNAL_DBM;
2385 +       rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2386 +
2387 +       SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2388 +       SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2389 +                               rt2x00_eeprom_addr(rt2x00dev,
2390 +                                                  EEPROM_MAC_ADDR_0));
2391 +
2392 +       /*
2393 +        * Initialize hw_mode information.
2394 +        */
2395 +       spec->supported_bands = SUPPORT_BAND_2GHZ;
2396 +       spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2397 +
2398 +       if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2399 +           rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2400 +               spec->num_channels = 14;
2401 +               spec->channels = rf_vals;
2402 +       } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2403 +                  rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2404 +               spec->supported_bands |= SUPPORT_BAND_5GHZ;
2405 +               spec->num_channels = ARRAY_SIZE(rf_vals);
2406 +               spec->channels = rf_vals;
2407 +       }
2408 +
2409 +       /*
2410 +        * Initialize HT information.
2411 +        */
2412 +       spec->ht.ht_supported = true;
2413 +       spec->ht.cap =
2414 +           IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2415 +           IEEE80211_HT_CAP_GRN_FLD |
2416 +           IEEE80211_HT_CAP_SGI_20 |
2417 +           IEEE80211_HT_CAP_SGI_40 |
2418 +           IEEE80211_HT_CAP_TX_STBC |
2419 +           IEEE80211_HT_CAP_RX_STBC |
2420 +           IEEE80211_HT_CAP_PSMP_SUPPORT;
2421 +       spec->ht.ampdu_factor = 3;
2422 +       spec->ht.ampdu_density = 4;
2423 +       spec->ht.mcs.rx_mask[0] = 0xff;
2424 +       spec->ht.mcs.rx_mask[1] = 0xff;
2425 +       spec->ht.mcs.tx_params =
2426 +           IEEE80211_HT_MCS_TX_DEFINED;
2427 +
2428 +       /*
2429 +        * Create channel information array
2430 +        */
2431 +       info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2432 +       if (!info)
2433 +               return -ENOMEM;
2434 +
2435 +       spec->channels_info = info;
2436 +
2437 +       tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2438 +       tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2439 +
2440 +       for (i = 0; i < 14; i++) {
2441 +               info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2442 +               info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2443 +       }
2444 +
2445 +       if (spec->num_channels > 14) {
2446 +               tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2447 +               tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2448 +
2449 +               for (i = 14; i < spec->num_channels; i++) {
2450 +                       info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2451 +                       info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2452 +               }
2453 +       }
2454 +
2455 +       return 0;
2456 +}
2457 +
2458 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2459 +{
2460 +       int retval;
2461 +
2462 +       /*
2463 +        * Allocate eeprom data.
2464 +        */
2465 +       retval = rt2800pci_validate_eeprom(rt2x00dev);
2466 +       if (retval)
2467 +               return retval;
2468 +
2469 +       retval = rt2800pci_init_eeprom(rt2x00dev);
2470 +       if (retval)
2471 +               return retval;
2472 +
2473 +       /*
2474 +        * Initialize hw specifications.
2475 +        */
2476 +       retval = rt2800pci_probe_hw_mode(rt2x00dev);
2477 +       if (retval)
2478 +               return retval;
2479 +
2480 +       /*
2481 +        * This device requires firmware.
2482 +        */
2483 +       __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2484 +       if (!modparam_nohwcrypt)
2485 +               __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2486 +
2487 +       /*
2488 +        * Set the rssi offset.
2489 +        */
2490 +       rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2491 +
2492 +       return 0;
2493 +}
2494 +
2495 +/*
2496 + * IEEE80211 stack callback functions.
2497 + */
2498 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2499 +{
2500 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2501 +       u32 reg;
2502 +
2503 +       rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2504 +       rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2505 +       rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2506 +
2507 +       rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2508 +       rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2509 +       rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2510 +
2511 +       rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2512 +       rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2513 +       rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2514 +
2515 +       rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2516 +       rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 1);
2517 +       rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2518 +
2519 +       rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2520 +       rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 1);
2521 +       rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2522 +
2523 +       rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2524 +       rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 1);
2525 +       rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2526 +
2527 +       rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2528 +       rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 1);
2529 +       rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2530 +
2531 +       return 0;
2532 +}
2533 +
2534 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2535 +                            const struct ieee80211_tx_queue_params *params)
2536 +{
2537 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2538 +       struct data_queue *queue;
2539 +       struct rt2x00_field32 field;
2540 +       int retval;
2541 +       u32 reg;
2542 +       u32 offset;
2543 +
2544 +       /*
2545 +        * First pass the configuration through rt2x00lib, that will
2546 +        * update the queue settings and validate the input. After that
2547 +        * we are free to update the registers based on the value
2548 +        * in the queue parameter.
2549 +        */
2550 +       retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2551 +       if (retval)
2552 +               return retval;
2553 +
2554 +       queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2555 +
2556 +       /* Update WMM TXOP register */
2557 +       if (queue_idx < 2) {
2558 +               field.bit_offset = queue_idx * 16;
2559 +               field.bit_mask = 0xffff << field.bit_offset;
2560 +
2561 +               rt2x00pci_register_read(rt2x00dev, WMM_TXOP0_CFG, &reg);
2562 +               rt2x00_set_field32(&reg, field, queue->txop);
2563 +               rt2x00pci_register_write(rt2x00dev, WMM_TXOP0_CFG, reg);
2564 +       } else if (queue_idx < 4) {
2565 +               field.bit_offset = (queue_idx - 2) * 16;
2566 +               field.bit_mask = 0xffff << field.bit_offset;
2567 +
2568 +               rt2x00pci_register_read(rt2x00dev, WMM_TXOP1_CFG, &reg);
2569 +               rt2x00_set_field32(&reg, field, queue->txop);
2570 +               rt2x00pci_register_write(rt2x00dev, WMM_TXOP1_CFG, reg);
2571 +       }
2572 +
2573 +       /* Update WMM registers */
2574 +       field.bit_offset = queue_idx * 4;
2575 +       field.bit_mask = 0xf << field.bit_offset;
2576 +
2577 +       rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2578 +       rt2x00_set_field32(&reg, field, queue->aifs);
2579 +       rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2580 +
2581 +       rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2582 +       rt2x00_set_field32(&reg, field, queue->cw_min);
2583 +       rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2584 +
2585 +       rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2586 +       rt2x00_set_field32(&reg, field, queue->cw_max);
2587 +       rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2588 +
2589 +       /* Update EDCA registers */
2590 +       if (queue_idx < 4) {
2591 +               offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2592 +
2593 +               rt2x00pci_register_read(rt2x00dev, offset, &reg);
2594 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2595 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2596 +               rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2597 +               rt2x00pci_register_write(rt2x00dev, offset, reg);
2598 +       }
2599 +
2600 +       return 0;
2601 +}
2602 +
2603 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2604 +{
2605 +       struct rt2x00_dev *rt2x00dev = hw->priv;
2606 +       u64 tsf;
2607 +       u32 reg;
2608 +
2609 +       rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2610 +       tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2611 +       rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2612 +       tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2613 +
2614 +       return tsf;
2615 +}
2616 +
2617 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2618 +       .tx                     = rt2x00mac_tx,
2619 +       .start                  = rt2x00mac_start,
2620 +       .stop                   = rt2x00mac_stop,
2621 +       .add_interface          = rt2x00mac_add_interface,
2622 +       .remove_interface       = rt2x00mac_remove_interface,
2623 +       .config                 = rt2x00mac_config,
2624 +       .config_interface       = rt2x00mac_config_interface,
2625 +       .configure_filter       = rt2x00mac_configure_filter,
2626 +       .set_key                = rt2x00mac_set_key,
2627 +       .get_stats              = rt2x00mac_get_stats,
2628 +       .set_rts_threshold      = rt2800pci_set_rts_threshold,
2629 +       .bss_info_changed       = rt2x00mac_bss_info_changed,
2630 +       .conf_tx                = rt2800pci_conf_tx,
2631 +       .get_tx_stats           = rt2x00mac_get_tx_stats,
2632 +       .get_tsf                = rt2800pci_get_tsf,
2633 +};
2634 +
2635 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2636 +       .irq_handler            = rt2800pci_interrupt,
2637 +       .probe_hw               = rt2800pci_probe_hw,
2638 +       .get_firmware_name      = rt2800pci_get_firmware_name,
2639 +       .get_firmware_crc       = rt2800pci_get_firmware_crc,
2640 +       .load_firmware          = rt2800pci_load_firmware,
2641 +       .initialize             = rt2x00pci_initialize,
2642 +       .uninitialize           = rt2x00pci_uninitialize,
2643 +       .get_entry_state        = rt2800pci_get_entry_state,
2644 +       .clear_entry            = rt2800pci_clear_entry,
2645 +       .set_device_state       = rt2800pci_set_device_state,
2646 +       .rfkill_poll            = rt2800pci_rfkill_poll,
2647 +       .link_stats             = rt2800pci_link_stats,
2648 +       .reset_tuner            = rt2800pci_reset_tuner,
2649 +       .link_tuner             = rt2800pci_link_tuner,
2650 +       .write_tx_desc          = rt2800pci_write_tx_desc,
2651 +       .write_tx_data          = rt2x00pci_write_tx_data,
2652 +       .write_beacon           = rt2800pci_write_beacon,
2653 +       .kick_tx_queue          = rt2800pci_kick_tx_queue,
2654 +       .fill_rxdone            = rt2800pci_fill_rxdone,
2655 +       .config_shared_key      = rt2800pci_config_shared_key,
2656 +       .config_pairwise_key    = rt2800pci_config_pairwise_key,
2657 +       .config_filter          = rt2800pci_config_filter,
2658 +       .config_intf            = rt2800pci_config_intf,
2659 +       .config_erp             = rt2800pci_config_erp,
2660 +       .config_ant             = rt2800pci_config_ant,
2661 +       .config                 = rt2800pci_config,
2662 +};
2663 +
2664 +static const struct data_queue_desc rt2800pci_queue_rx = {
2665 +       .entry_num              = RX_ENTRIES,
2666 +       .data_size              = DATA_FRAME_SIZE,
2667 +       .desc_size              = RXD_DESC_SIZE,
2668 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
2669 +};
2670 +
2671 +static const struct data_queue_desc rt2800pci_queue_tx = {
2672 +       .entry_num              = TX_ENTRIES,
2673 +       .data_size              = DATA_FRAME_SIZE,
2674 +       .desc_size              = TXD_DESC_SIZE,
2675 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
2676 +};
2677 +
2678 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2679 +       .entry_num              = 8 * BEACON_ENTRIES,
2680 +       .data_size              = 0, /* No DMA required for beacons */
2681 +       .desc_size              = TXWI_DESC_SIZE,
2682 +       .priv_size              = sizeof(struct queue_entry_priv_pci),
2683 +};
2684 +
2685 +static const struct rt2x00_ops rt2800pci_ops = {
2686 +       .name           = KBUILD_MODNAME,
2687 +       .max_sta_intf   = 1,
2688 +       .max_ap_intf    = 8,
2689 +       .eeprom_size    = EEPROM_SIZE,
2690 +       .rf_size        = RF_SIZE,
2691 +       .tx_queues      = NUM_TX_QUEUES,
2692 +       .rx             = &rt2800pci_queue_rx,
2693 +       .tx             = &rt2800pci_queue_tx,
2694 +       .bcn            = &rt2800pci_queue_bcn,
2695 +       .lib            = &rt2800pci_rt2x00_ops,
2696 +       .hw             = &rt2800pci_mac80211_ops,
2697 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2698 +       .debugfs        = &rt2800pci_rt2x00debug,
2699 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2700 +};
2701 +
2702 +/*
2703 + * RT2800pci module information.
2704 + */
2705 +static struct pci_device_id rt2800pci_device_table[] = {
2706 +       { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2707 +       { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2708 +       { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2709 +       { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2710 +       { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2711 +       { 0, }
2712 +};
2713 +
2714 +MODULE_AUTHOR(DRV_PROJECT);
2715 +MODULE_VERSION(DRV_VERSION);
2716 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2717 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2718 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2719 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2720 +MODULE_LICENSE("GPL");
2721 +
2722 +static struct pci_driver rt2800pci_driver = {
2723 +       .name           = KBUILD_MODNAME,
2724 +       .id_table       = rt2800pci_device_table,
2725 +       .probe          = rt2x00pci_probe,
2726 +       .remove         = __devexit_p(rt2x00pci_remove),
2727 +       .suspend        = rt2x00pci_suspend,
2728 +       .resume         = rt2x00pci_resume,
2729 +};
2730 +
2731 +static int __init rt2800pci_init(void)
2732 +{
2733 +       return pci_register_driver(&rt2800pci_driver);
2734 +}
2735 +
2736 +static void __exit rt2800pci_exit(void)
2737 +{
2738 +       pci_unregister_driver(&rt2800pci_driver);
2739 +}
2740 +
2741 +module_init(rt2800pci_init);
2742 +module_exit(rt2800pci_exit);
2743 --- /dev/null
2744 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
2745 @@ -0,0 +1,1879 @@
2746 +/*
2747 +       Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
2748 +       <http://rt2x00.serialmonkey.com>
2749 +
2750 +       This program is free software; you can redistribute it and/or modify
2751 +       it under the terms of the GNU General Public License as published by
2752 +       the Free Software Foundation; either version 2 of the License, or
2753 +       (at your option) any later version.
2754 +
2755 +       This program is distributed in the hope that it will be useful,
2756 +       but WITHOUT ANY WARRANTY; without even the implied warranty of
2757 +       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2758 +       GNU General Public License for more details.
2759 +
2760 +       You should have received a copy of the GNU General Public License
2761 +       along with this program; if not, write to the
2762 +       Free Software Foundation, Inc.,
2763 +       59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2764 + */
2765 +
2766 +/*
2767 +       Module: rt2800pci
2768 +       Abstract: Data structures and registers for the rt2800pci module.
2769 +       Supported chipsets: RT2800E & RT2800ED.
2770 + */
2771 +
2772 +#ifndef RT2800PCI_H
2773 +#define RT2800PCI_H
2774 +
2775 +/*
2776 + * RF chip defines.
2777 + *
2778 + * RF2820 2.4G 2T3R
2779 + * RF2850 2.4G/5G 2T3R
2780 + * RF2720 2.4G 1T2R
2781 + * RF2750 2.4G/5G 1T2R
2782 + * RF3020 2.4G 1T1R
2783 + * RF2020 2.4G B/G
2784 + */
2785 +#define RF2820                         0x0001
2786 +#define RF2850                         0x0002
2787 +#define RF2720                         0x0003
2788 +#define RF2750                         0x0004
2789 +#define RF3020                         0x0005
2790 +#define RF2020                         0x0006
2791 +
2792 +/*
2793 + * RT2860 version
2794 + */
2795 +#define RT2860_VERSION_C               0x0100
2796 +#define RT2860_VERSION_D               0x0101
2797 +#define RT2860_VERSION_E               0x0200
2798 +
2799 +/*
2800 + * Signal information.
2801 + * Defaul offset is required for RSSI <-> dBm conversion.
2802 + */
2803 +#define DEFAULT_RSSI_OFFSET            120 /* FIXME */
2804 +
2805 +/*
2806 + * Register layout information.
2807 + */
2808 +#define CSR_REG_BASE                   0x1000
2809 +#define CSR_REG_SIZE                   0x0800
2810 +#define EEPROM_BASE                    0x0000
2811 +#define EEPROM_SIZE                    0x0110
2812 +#define BBP_BASE                       0x0000
2813 +#define BBP_SIZE                       0x0080
2814 +#define RF_BASE                                0x0000
2815 +#define RF_SIZE                                0x0014
2816 +
2817 +/*
2818 + * Number of TX queues.
2819 + */
2820 +#define NUM_TX_QUEUES                  4
2821 +
2822 +/*
2823 + * PCI registers.
2824 + */
2825 +
2826 +/*
2827 + * PCI Configuration Header
2828 + */
2829 +#define PCI_CONFIG_HEADER_VENDOR       0x0000
2830 +#define PCI_CONFIG_HEADER_DEVICE       0x0002
2831 +
2832 +/*
2833 + * E2PROM_CSR: EEPROM control register.
2834 + * RELOAD: Write 1 to reload eeprom content.
2835 + * TYPE_93C46: 1: 93c46, 0:93c66.
2836 + * LOAD_STATUS: 1:loading, 0:done.
2837 + */
2838 +#define E2PROM_CSR                     0x0004
2839 +#define E2PROM_CSR_DATA_CLOCK          FIELD32(0x00000001)
2840 +#define E2PROM_CSR_CHIP_SELECT         FIELD32(0x00000002)
2841 +#define E2PROM_CSR_DATA_IN             FIELD32(0x00000004)
2842 +#define E2PROM_CSR_DATA_OUT            FIELD32(0x00000008)
2843 +#define E2PROM_CSR_TYPE_93C46          FIELD32(0x00000020)
2844 +#define E2PROM_CSR_LOAD_STATUS         FIELD32(0x00000040)
2845 +#define E2PROM_CSR_RELOAD              FIELD32(0x00000080)
2846 +
2847 +/*
2848 + * HOST-MCU shared memory
2849 + */
2850 +#define HOST_CMD_CSR                   0x0404
2851 +#define HOST_CMD_CSR_HOST_COMMAND      FIELD32(0x000000ff)
2852 +
2853 +/*
2854 + * INT_SOURCE_CSR: Interrupt source register.
2855 + * Write one to clear corresponding bit.
2856 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2857 + */
2858 +#define INT_SOURCE_CSR                 0x0200
2859 +#define INT_SOURCE_CSR_RXDELAYINT      FIELD32(0x00000001)
2860 +#define INT_SOURCE_CSR_TXDELAYINT      FIELD32(0x00000002)
2861 +#define INT_SOURCE_CSR_RX_DONE         FIELD32(0x00000004)
2862 +#define INT_SOURCE_CSR_AC0_DMA_DONE    FIELD32(0x00000008)
2863 +#define INT_SOURCE_CSR_AC1_DMA_DONE    FIELD32(0x00000010)
2864 +#define INT_SOURCE_CSR_AC2_DMA_DONE    FIELD32(0x00000020)
2865 +#define INT_SOURCE_CSR_AC3_DMA_DONE    FIELD32(0x00000040)
2866 +#define INT_SOURCE_CSR_HCCA_DMA_DONE   FIELD32(0x00000080)
2867 +#define INT_SOURCE_CSR_MGMT_DMA_DONE   FIELD32(0x00000100)
2868 +#define INT_SOURCE_CSR_MCU_COMMAND     FIELD32(0x00000200)
2869 +#define INT_SOURCE_CSR_RXTX_COHERENT   FIELD32(0x00000400)
2870 +#define INT_SOURCE_CSR_TBTT            FIELD32(0x00000800)
2871 +#define INT_SOURCE_CSR_PRE_TBTT                FIELD32(0x00001000)
2872 +#define INT_SOURCE_CSR_TX_FIFO_STATUS  FIELD32(0x00002000)
2873 +#define INT_SOURCE_CSR_AUTO_WAKEUP     FIELD32(0x00004000)
2874 +#define INT_SOURCE_CSR_GPTIMER         FIELD32(0x00008000)
2875 +#define INT_SOURCE_CSR_RX_COHERENT     FIELD32(0x00010000)
2876 +#define INT_SOURCE_CSR_TX_COHERENT     FIELD32(0x00020000)
2877 +
2878 +/*
2879 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2880 + */
2881 +#define INT_MASK_CSR                   0x0204
2882 +#define INT_MASK_CSR_RXDELAYINT                FIELD32(0x00000001)
2883 +#define INT_MASK_CSR_TXDELAYINT                FIELD32(0x00000002)
2884 +#define INT_MASK_CSR_RX_DONE           FIELD32(0x00000004)
2885 +#define INT_MASK_CSR_AC0_DMA_DONE      FIELD32(0x00000008)
2886 +#define INT_MASK_CSR_AC1_DMA_DONE      FIELD32(0x00000010)
2887 +#define INT_MASK_CSR_AC2_DMA_DONE      FIELD32(0x00000020)
2888 +#define INT_MASK_CSR_AC3_DMA_DONE      FIELD32(0x00000040)
2889 +#define INT_MASK_CSR_HCCA_DMA_DONE     FIELD32(0x00000080)
2890 +#define INT_MASK_CSR_MGMT_DMA_DONE     FIELD32(0x00000100)
2891 +#define INT_MASK_CSR_MCU_COMMAND       FIELD32(0x00000200)
2892 +#define INT_MASK_CSR_RXTX_COHERENT     FIELD32(0x00000400)
2893 +#define INT_MASK_CSR_TBTT              FIELD32(0x00000800)
2894 +#define INT_MASK_CSR_PRE_TBTT          FIELD32(0x00001000)
2895 +#define INT_MASK_CSR_TX_FIFO_STATUS    FIELD32(0x00002000)
2896 +#define INT_MASK_CSR_AUTO_WAKEUP       FIELD32(0x00004000)
2897 +#define INT_MASK_CSR_GPTIMER           FIELD32(0x00008000)
2898 +#define INT_MASK_CSR_RX_COHERENT       FIELD32(0x00010000)
2899 +#define INT_MASK_CSR_TX_COHERENT       FIELD32(0x00020000)
2900 +
2901 +/*
2902 + * WPDMA_GLO_CFG
2903 + */
2904 +#define WPDMA_GLO_CFG                  0x0208
2905 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA    FIELD32(0x00000001)
2906 +#define WPDMA_GLO_CFG_TX_DMA_BUSY      FIELD32(0x00000002)
2907 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA    FIELD32(0x00000004)
2908 +#define WPDMA_GLO_CFG_RX_DMA_BUSY      FIELD32(0x00000008)
2909 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE        FIELD32(0x00000030)
2910 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE        FIELD32(0x00000040)
2911 +#define WPDMA_GLO_CFG_BIG_ENDIAN       FIELD32(0x00000080)
2912 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER   FIELD32(0x0000ff00)
2913 +#define WPDMA_GLO_CFG_HDR_SEG_LEN      FIELD32(0xffff0000)
2914 +
2915 +/*
2916 + * WPDMA_RST_IDX
2917 + */
2918 +#define WPDMA_RST_IDX                  0x020c
2919 +#define WPDMA_RST_IDX_DTX_IDX0         FIELD32(0x00000001)
2920 +#define WPDMA_RST_IDX_DTX_IDX1         FIELD32(0x00000002)
2921 +#define WPDMA_RST_IDX_DTX_IDX2         FIELD32(0x00000004)
2922 +#define WPDMA_RST_IDX_DTX_IDX3         FIELD32(0x00000008)
2923 +#define WPDMA_RST_IDX_DTX_IDX4         FIELD32(0x00000010)
2924 +#define WPDMA_RST_IDX_DTX_IDX5         FIELD32(0x00000020)
2925 +#define WPDMA_RST_IDX_DRX_IDX0         FIELD32(0x00010000)
2926 +
2927 +/*
2928 + * DELAY_INT_CFG
2929 + */
2930 +#define DELAY_INT_CFG                  0x0210
2931 +#define DELAY_INT_CFG_RXMAX_PTIME      FIELD32(0x000000ff)
2932 +#define DELAY_INT_CFG_RXMAX_PINT       FIELD32(0x00007f00)
2933 +#define DELAY_INT_CFG_RXDLY_INT_EN     FIELD32(0x00008000)
2934 +#define DELAY_INT_CFG_TXMAX_PTIME      FIELD32(0x00ff0000)
2935 +#define DELAY_INT_CFG_TXMAX_PINT       FIELD32(0x7f000000)
2936 +#define DELAY_INT_CFG_TXDLY_INT_EN     FIELD32(0x80000000)
2937 +
2938 +/*
2939 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
2940 + * AIFSN0: AC_BE
2941 + * AIFSN1: AC_BK
2942 + * AIFSN1: AC_VI
2943 + * AIFSN1: AC_VO
2944 + */
2945 +#define WMM_AIFSN_CFG                  0x0214
2946 +#define WMM_AIFSN_CFG_AIFSN0           FIELD32(0x0000000f)
2947 +#define WMM_AIFSN_CFG_AIFSN1           FIELD32(0x000000f0)
2948 +#define WMM_AIFSN_CFG_AIFSN2           FIELD32(0x00000f00)
2949 +#define WMM_AIFSN_CFG_AIFSN3           FIELD32(0x0000f000)
2950 +
2951 +/*
2952 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
2953 + * CWMIN0: AC_BE
2954 + * CWMIN1: AC_BK
2955 + * CWMIN1: AC_VI
2956 + * CWMIN1: AC_VO
2957 + */
2958 +#define WMM_CWMIN_CFG                  0x0218
2959 +#define WMM_CWMIN_CFG_CWMIN0           FIELD32(0x0000000f)
2960 +#define WMM_CWMIN_CFG_CWMIN1           FIELD32(0x000000f0)
2961 +#define WMM_CWMIN_CFG_CWMIN2           FIELD32(0x00000f00)
2962 +#define WMM_CWMIN_CFG_CWMIN3           FIELD32(0x0000f000)
2963 +
2964 +/*
2965 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
2966 + * CWMAX0: AC_BE
2967 + * CWMAX1: AC_BK
2968 + * CWMAX1: AC_VI
2969 + * CWMAX1: AC_VO
2970 + */
2971 +#define WMM_CWMAX_CFG                  0x021c
2972 +#define WMM_CWMAX_CFG_CWMAX0           FIELD32(0x0000000f)
2973 +#define WMM_CWMAX_CFG_CWMAX1           FIELD32(0x000000f0)
2974 +#define WMM_CWMAX_CFG_CWMAX2           FIELD32(0x00000f00)
2975 +#define WMM_CWMAX_CFG_CWMAX3           FIELD32(0x0000f000)
2976 +
2977 +/*
2978 + * AC_TXOP0: AC_BK/AC_BE TXOP register
2979 + * AC0TXOP: AC_BK in unit of 32us
2980 + * AC1TXOP: AC_BE in unit of 32us
2981 + */
2982 +#define WMM_TXOP0_CFG                  0x0220
2983 +#define WMM_TXOP0_CFG_AC0TXOP          FIELD32(0x0000ffff)
2984 +#define WMM_TXOP0_CFG_AC1TXOP          FIELD32(0xffff0000)
2985 +
2986 +/*
2987 + * AC_TXOP1: AC_VO/AC_VI TXOP register
2988 + * AC2TXOP: AC_VI in unit of 32us
2989 + * AC3TXOP: AC_VO in unit of 32us
2990 + */
2991 +#define WMM_TXOP1_CFG                  0x0224
2992 +#define WMM_TXOP1_CFG_AC2TXOP          FIELD32(0x0000ffff)
2993 +#define WMM_TXOP1_CFG_AC3TXOP          FIELD32(0xffff0000)
2994 +
2995 +/*
2996 + * RINGREG_DIFF
2997 + */
2998 +#define RINGREG_DIFF                   0x0010
2999 +
3000 +/*
3001 + * GPIO_CTRL_CFG:
3002 + */
3003 +#define GPIO_CTRL_CFG                  0x0228
3004 +#define GPIO_CTRL_CFG_BIT0             FIELD32(0x00000001)
3005 +#define GPIO_CTRL_CFG_BIT1             FIELD32(0x00000002)
3006 +#define GPIO_CTRL_CFG_BIT2             FIELD32(0x00000004)
3007 +#define GPIO_CTRL_CFG_BIT3             FIELD32(0x00000008)
3008 +#define GPIO_CTRL_CFG_BIT4             FIELD32(0x00000010)
3009 +#define GPIO_CTRL_CFG_BIT5             FIELD32(0x00000020)
3010 +#define GPIO_CTRL_CFG_BIT6             FIELD32(0x00000040)
3011 +#define GPIO_CTRL_CFG_BIT7             FIELD32(0x00000080)
3012 +#define GPIO_CTRL_CFG_BIT8             FIELD32(0x00000100)
3013 +
3014 +/*
3015 + * MCU_CMD_CFG
3016 + */
3017 +#define MCU_CMD_CFG                    0x022c
3018 +
3019 +/*
3020 + * AC_BK register offsets
3021 + */
3022 +#define TX_BASE_PTR0                   0x0230
3023 +#define TX_MAX_CNT0                    0x0234
3024 +#define TX_CTX_IDX0                    0x0238
3025 +#define TX_DTX_IDX0                    0x023c
3026 +
3027 +/*
3028 + * AC_BE register offsets
3029 + */
3030 +#define TX_BASE_PTR1                   0x0240
3031 +#define TX_MAX_CNT1                    0x0244
3032 +#define TX_CTX_IDX1                    0x0248
3033 +#define TX_DTX_IDX1                    0x024c
3034 +
3035 +/*
3036 + * AC_VI register offsets
3037 + */
3038 +#define TX_BASE_PTR2                   0x0250
3039 +#define TX_MAX_CNT2                    0x0254
3040 +#define TX_CTX_IDX2                    0x0258
3041 +#define TX_DTX_IDX2                    0x025c
3042 +
3043 +/*
3044 + * AC_VO register offsets
3045 + */
3046 +#define TX_BASE_PTR3                   0x0260
3047 +#define TX_MAX_CNT3                    0x0264
3048 +#define TX_CTX_IDX3                    0x0268
3049 +#define TX_DTX_IDX3                    0x026c
3050 +
3051 +/*
3052 + * HCCA register offsets
3053 + */
3054 +#define TX_BASE_PTR4                   0x0270
3055 +#define TX_MAX_CNT4                    0x0274
3056 +#define TX_CTX_IDX4                    0x0278
3057 +#define TX_DTX_IDX4                    0x027c
3058 +
3059 +/*
3060 + * MGMT register offsets
3061 + */
3062 +#define TX_BASE_PTR5                   0x0280
3063 +#define TX_MAX_CNT5                    0x0284
3064 +#define TX_CTX_IDX5                    0x0288
3065 +#define TX_DTX_IDX5                    0x028c
3066 +
3067 +/*
3068 + * Queue register offset macros
3069 + */
3070 +#define TX_QUEUE_REG_OFFSET            0x10
3071 +#define TX_BASE_PTR(__x)               TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3072 +#define TX_MAX_CNT(__x)                        TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3073 +#define TX_CTX_IDX(__x)                        TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3074 +#define TX_DTX_IDX(__x)                        TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3075 +
3076 +/*
3077 + * RX register offsets
3078 + */
3079 +#define RX_BASE_PTR                    0x0290
3080 +#define RX_MAX_CNT                     0x0294
3081 +#define RX_CRX_IDX                     0x0298
3082 +#define RX_DRX_IDX                     0x029c
3083 +
3084 +/*
3085 + * PBF_SYS_CTRL
3086 + * HOST_RAM_WRITE: enable Host program ram write selection
3087 + */
3088 +#define PBF_SYS_CTRL                   0x0400
3089 +#define PBF_SYS_CTRL_READY             FIELD32(0x00000080)
3090 +#define PBF_SYS_CTRL_HOST_RAM_WRITE    FIELD32(0x00010000)
3091 +
3092 +/*
3093 + * PBF  registers
3094 + * Most are for debug. Driver doesn't touch PBF register.
3095 + */
3096 +#define PBF_CFG                                0x0408
3097 +#define PBF_MAX_PCNT                   0x040c
3098 +#define PBF_CTRL                       0x0410
3099 +#define PBF_INT_STA                    0x0414
3100 +#define PBF_INT_ENA                    0x0418
3101 +
3102 +/*
3103 + * BCN_OFFSET0:
3104 + */
3105 +#define BCN_OFFSET0                    0x042c
3106 +#define BCN_OFFSET0_BCN0               FIELD32(0x000000ff)
3107 +#define BCN_OFFSET0_BCN1               FIELD32(0x0000ff00)
3108 +#define BCN_OFFSET0_BCN2               FIELD32(0x00ff0000)
3109 +#define BCN_OFFSET0_BCN3               FIELD32(0xff000000)
3110 +
3111 +/*
3112 + * BCN_OFFSET1:
3113 + */
3114 +#define BCN_OFFSET1                    0x0430
3115 +#define BCN_OFFSET1_BCN4               FIELD32(0x000000ff)
3116 +#define BCN_OFFSET1_BCN5               FIELD32(0x0000ff00)
3117 +#define BCN_OFFSET1_BCN6               FIELD32(0x00ff0000)
3118 +#define BCN_OFFSET1_BCN7               FIELD32(0xff000000)
3119 +
3120 +/*
3121 + * PBF  registers
3122 + * Most are for debug. Driver doesn't touch PBF register.
3123 + */
3124 +#define TXRXQ_PCNT                     0x0438
3125 +#define PBF_DBG                                0x043c
3126 +
3127 +/*
3128 + * MAC Control/Status Registers(CSR).
3129 + * Some values are set in TU, whereas 1 TU == 1024 us.
3130 + */
3131 +
3132 +/*
3133 + * MAC_CSR0: ASIC revision number.
3134 + * ASIC_REV: 0
3135 + * ASIC_VER: 2860
3136 + */
3137 +#define MAC_CSR0                       0x1000
3138 +#define MAC_CSR0_ASIC_REV              FIELD32(0x0000ffff)
3139 +#define MAC_CSR0_ASIC_VER              FIELD32(0xffff0000)
3140 +
3141 +/*
3142 + * MAC_SYS_CTRL:
3143 + */
3144 +#define MAC_SYS_CTRL                   0x1004
3145 +#define MAC_SYS_CTRL_RESET_CSR         FIELD32(0x00000001)
3146 +#define MAC_SYS_CTRL_RESET_BBP         FIELD32(0x00000002)
3147 +#define MAC_SYS_CTRL_ENABLE_TX         FIELD32(0x00000004)
3148 +#define MAC_SYS_CTRL_ENABLE_RX         FIELD32(0x00000008)
3149 +#define MAC_SYS_CTRL_CONTINUOUS_TX     FIELD32(0x00000010)
3150 +#define MAC_SYS_CTRL_LOOPBACK          FIELD32(0x00000020)
3151 +#define MAC_SYS_CTRL_WLAN_HALT         FIELD32(0x00000040)
3152 +#define MAC_SYS_CTRL_RX_TIMESTAMP      FIELD32(0x00000080)
3153 +
3154 +/*
3155 + * MAC_ADDR_DW0: STA MAC register 0
3156 + */
3157 +#define MAC_ADDR_DW0                   0x1008
3158 +#define MAC_ADDR_DW0_BYTE0             FIELD32(0x000000ff)
3159 +#define MAC_ADDR_DW0_BYTE1             FIELD32(0x0000ff00)
3160 +#define MAC_ADDR_DW0_BYTE2             FIELD32(0x00ff0000)
3161 +#define MAC_ADDR_DW0_BYTE3             FIELD32(0xff000000)
3162 +
3163 +/*
3164 + * MAC_ADDR_DW1: STA MAC register 1
3165 + * UNICAST_TO_ME_MASK:
3166 + * Used to mask off bits from byte 5 of the MAC address
3167 + * to determine the UNICAST_TO_ME bit for RX frames.
3168 + * The full mask is complemented by BSS_ID_MASK:
3169 + *    MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3170 + */
3171 +#define MAC_ADDR_DW1                   0x100c
3172 +#define MAC_ADDR_DW1_BYTE4             FIELD32(0x000000ff)
3173 +#define MAC_ADDR_DW1_BYTE5             FIELD32(0x0000ff00)
3174 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK        FIELD32(0x00ff0000)
3175 +
3176 +/*
3177 + * MAC_BSSID_DW0: BSSID register 0
3178 + */
3179 +#define MAC_BSSID_DW0                  0x1010
3180 +#define MAC_BSSID_DW0_BYTE0            FIELD32(0x000000ff)
3181 +#define MAC_BSSID_DW0_BYTE1            FIELD32(0x0000ff00)
3182 +#define MAC_BSSID_DW0_BYTE2            FIELD32(0x00ff0000)
3183 +#define MAC_BSSID_DW0_BYTE3            FIELD32(0xff000000)
3184 +
3185 +/*
3186 + * MAC_BSSID_DW1: BSSID register 1
3187 + * BSS_ID_MASK:
3188 + *     0: 1-BSSID mode (BSS index = 0)
3189 + *     1: 2-BSSID mode (BSS index: Byte5, bit 0)
3190 + *     2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3191 + *     3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3192 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3193 + * BSSID. This will make sure that those bits will be ignored
3194 + * when determining the MY_BSS of RX frames.
3195 + */
3196 +#define MAC_BSSID_DW1                  0x1014
3197 +#define MAC_BSSID_DW1_BYTE4            FIELD32(0x000000ff)
3198 +#define MAC_BSSID_DW1_BYTE5            FIELD32(0x0000ff00)
3199 +#define MAC_BSSID_DW1_BSS_ID_MASK      FIELD32(0x00030000)
3200 +#define MAC_BSSID_DW1_BSS_BCN_NUM      FIELD32(0x001c0000)
3201 +
3202 +/*
3203 + * MAX_LEN_CFG: Maximum frame length register.
3204 + * MAX_MPDU: rt2860b max 16k bytes
3205 + * MAX_PSDU: Maximum PSDU length
3206 + *     (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3207 + */
3208 +#define MAX_LEN_CFG                    0x1018
3209 +#define MAX_LEN_CFG_MAX_MPDU           FIELD32(0x00000fff)
3210 +#define MAX_LEN_CFG_MAX_PSDU           FIELD32(0x00003000)
3211 +#define MAX_LEN_CFG_MIN_PSDU           FIELD32(0x0000c000)
3212 +#define MAX_LEN_CFG_MIN_MPDU           FIELD32(0x000f0000)
3213 +
3214 +/*
3215 + * BBP_CSR_CFG: BBP serial control register
3216 + * VALUE: Register value to program into BBP
3217 + * REG_NUM: Selected BBP register
3218 + * READ_CONTROL: 0 write BBP, 1 read BBP
3219 + * BUSY: ASIC is busy executing BBP commands
3220 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3221 + * BBP_RW_MODE: 0 serial, 1 paralell
3222 + */
3223 +#define BBP_CSR_CFG                    0x101c
3224 +#define BBP_CSR_CFG_VALUE              FIELD32(0x000000ff)
3225 +#define BBP_CSR_CFG_REGNUM             FIELD32(0x0000ff00)
3226 +#define BBP_CSR_CFG_READ_CONTROL       FIELD32(0x00010000)
3227 +#define BBP_CSR_CFG_BUSY               FIELD32(0x00020000)
3228 +#define BBP_CSR_CFG_BBP_PAR_DUR                FIELD32(0x00040000)
3229 +#define BBP_CSR_CFG_BBP_RW_MODE                FIELD32(0x00080000)
3230 +
3231 +/*
3232 + * RF_CSR_CFG0: RF control register
3233 + * REGID_AND_VALUE: Register value to program into RF
3234 + * BITWIDTH: Selected RF register
3235 + * STANDBYMODE: 0 high when standby, 1 low when standby
3236 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3237 + * BUSY: ASIC is busy executing RF commands
3238 + */
3239 +#define RF_CSR_CFG0                    0x1020
3240 +#define RF_CSR_CFG0_REGID_AND_VALUE    FIELD32(0x00ffffff)
3241 +#define RF_CSR_CFG0_BITWIDTH           FIELD32(0x1f000000)
3242 +#define RF_CSR_CFG0_REG_VALUE_BW       FIELD32(0x1fffffff)
3243 +#define RF_CSR_CFG0_STANDBYMODE                FIELD32(0x20000000)
3244 +#define RF_CSR_CFG0_SEL                        FIELD32(0x40000000)
3245 +#define RF_CSR_CFG0_BUSY               FIELD32(0x80000000)
3246 +
3247 +/*
3248 + * RF_CSR_CFG1: RF control register
3249 + * REGID_AND_VALUE: Register value to program into RF
3250 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3251 + *        0: 3 system clock cycle (37.5usec)
3252 + *        1: 5 system clock cycle (62.5usec)
3253 + */
3254 +#define RF_CSR_CFG1                    0x1024
3255 +#define RF_CSR_CFG1_REGID_AND_VALUE    FIELD32(0x00ffffff)
3256 +#define RF_CSR_CFG1_RFGAP              FIELD32(0x1f000000)
3257 +
3258 +/*
3259 + * RF_CSR_CFG2: RF control register
3260 + * VALUE: Register value to program into RF
3261 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3262 + *        0: 3 system clock cycle (37.5usec)
3263 + *        1: 5 system clock cycle (62.5usec)
3264 + */
3265 +#define RF_CSR_CFG2                    0x1028
3266 +#define RF_CSR_CFG2_VALUE              FIELD32(0x00ffffff)
3267 +
3268 +/*
3269 + * LED_CFG: LED control
3270 + * color LED's:
3271 + *   0: off
3272 + *   1: blinking upon TX2
3273 + *   2: periodic slow blinking
3274 + *   3: always on
3275 + * LED polarity:
3276 + *   0: active low
3277 + *   1: active high
3278 + */
3279 +#define LED_CFG                                0x102c
3280 +#define LED_CFG_ON_PERIOD              FIELD32(0x000000ff)
3281 +#define LED_CFG_OFF_PERIOD             FIELD32(0x0000ff00)
3282 +#define LED_CFG_SLOW_BLINK_PERIOD      FIELD32(0x003f0000)
3283 +#define LED_CFG_R_LED_MODE             FIELD32(0x03000000)
3284 +#define LED_CFG_G_LED_MODE             FIELD32(0x0c000000)
3285 +#define LED_CFG_Y_LED_MODE             FIELD32(0x30000000)
3286 +#define LED_CFG_LED_POLAR              FIELD32(0x40000000)
3287 +
3288 +/*
3289 + * XIFS_TIME_CFG: MAC timing
3290 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3291 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3292 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3293 + *     when MAC doesn't reference BBP signal BBRXEND
3294 + * EIFS: unit 1us
3295 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3296 + *
3297 + */
3298 +#define XIFS_TIME_CFG                  0x1100
3299 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME   FIELD32(0x000000ff)
3300 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME   FIELD32(0x0000ff00)
3301 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME   FIELD32(0x000f0000)
3302 +#define XIFS_TIME_CFG_EIFS             FIELD32(0x1ff00000)
3303 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE  FIELD32(0x20000000)
3304 +
3305 +/*
3306 + * BKOFF_SLOT_CFG:
3307 + */
3308 +#define BKOFF_SLOT_CFG                 0x1104
3309 +#define BKOFF_SLOT_CFG_SLOT_TIME       FIELD32(0x000000ff)
3310 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME   FIELD32(0x0000ff00)
3311 +
3312 +/*
3313 + * NAV_TIME_CFG:
3314 + */
3315 +#define NAV_TIME_CFG                   0x1108
3316 +#define NAV_TIME_CFG_SIFS              FIELD32(0x000000ff)
3317 +#define NAV_TIME_CFG_SLOT_TIME         FIELD32(0x0000ff00)
3318 +#define NAV_TIME_CFG_EIFS              FIELD32(0x01ff0000)
3319 +#define NAV_TIME_ZERO_SIFS             FIELD32(0x02000000)
3320 +
3321 +/*
3322 + * CH_TIME_CFG: count as channel busy
3323 + */
3324 +#define CH_TIME_CFG                    0x110c
3325 +
3326 +/*
3327 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3328 + */
3329 +#define PBF_LIFE_TIMER                 0x1110
3330 +
3331 +/*
3332 + * BCN_TIME_CFG:
3333 + * BEACON_INTERVAL: in unit of 1/16 TU
3334 + * TSF_TICKING: Enable TSF auto counting
3335 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3336 + * BEACON_GEN: Enable beacon generator
3337 + */
3338 +#define BCN_TIME_CFG                   0x1114
3339 +#define BCN_TIME_CFG_BEACON_INTERVAL   FIELD32(0x0000ffff)
3340 +#define BCN_TIME_CFG_TSF_TICKING       FIELD32(0x00010000)
3341 +#define BCN_TIME_CFG_TSF_SYNC          FIELD32(0x00060000)
3342 +#define BCN_TIME_CFG_TBTT_ENABLE       FIELD32(0x00080000)
3343 +#define BCN_TIME_CFG_BEACON_GEN                FIELD32(0x00100000)
3344 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE        FIELD32(0xf0000000)
3345 +
3346 +/*
3347 + * TBTT_SYNC_CFG:
3348 + */
3349 +#define TBTT_SYNC_CFG                  0x1118
3350 +
3351 +/*
3352 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3353 + */
3354 +#define TSF_TIMER_DW0                  0x111c
3355 +#define TSF_TIMER_DW0_LOW_WORD         FIELD32(0xffffffff)
3356 +
3357 +/*
3358 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3359 + */
3360 +#define TSF_TIMER_DW1                  0x1120
3361 +#define TSF_TIMER_DW1_HIGH_WORD                FIELD32(0xffffffff)
3362 +
3363 +/*
3364 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3365 + */
3366 +#define TBTT_TIMER                     0x1124
3367 +
3368 +/*
3369 + * INT_TIMER_CFG:
3370 + */
3371 +#define INT_TIMER_CFG                  0x1128
3372 +
3373 +/*
3374 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3375 + */
3376 +#define INT_TIMER_EN                   0x112c
3377 +
3378 +/*
3379 + * CH_IDLE_STA: channel idle time
3380 + */
3381 +#define CH_IDLE_STA                    0x1130
3382 +
3383 +/*
3384 + * CH_BUSY_STA: channel busy time
3385 + */
3386 +#define CH_BUSY_STA                    0x1134
3387 +
3388 +/*
3389 + * MAC_STATUS_CFG:
3390 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3391 + *     if 1 or higher one of the 2 registers is busy.
3392 + */
3393 +#define MAC_STATUS_CFG                 0x1200
3394 +#define MAC_STATUS_CFG_BBP_RF_BUSY     FIELD32(0x00000003)
3395 +
3396 +/*
3397 + * PWR_PIN_CFG:
3398 + */
3399 +#define PWR_PIN_CFG                    0x1204
3400 +
3401 +/*
3402 + * AUTOWAKEUP_CFG: Manual power control / status register
3403 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3404 + * AUTOWAKE: 0:sleep, 1:awake
3405 + */
3406 +#define AUTOWAKEUP_CFG                 0x1208
3407 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME  FIELD32(0x000000ff)
3408 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE        FIELD32(0x00007f00)
3409 +#define AUTOWAKEUP_CFG_AUTOWAKE                FIELD32(0x00008000)
3410 +
3411 +/*
3412 + * EDCA_AC0_CFG:
3413 + */
3414 +#define EDCA_AC0_CFG                   0x1300
3415 +#define EDCA_AC0_CFG_AC_TX_OP          FIELD32(0x000000ff)
3416 +#define EDCA_AC0_CFG_AIFSN             FIELD32(0x00000f00)
3417 +#define EDCA_AC0_CFG_CWMIN             FIELD32(0x0000f000)
3418 +#define EDCA_AC0_CFG_CWMAX             FIELD32(0x000f0000)
3419 +
3420 +/*
3421 + * EDCA_AC1_CFG:
3422 + */
3423 +#define EDCA_AC1_CFG                   0x1304
3424 +#define EDCA_AC1_CFG_AC_TX_OP          FIELD32(0x000000ff)
3425 +#define EDCA_AC1_CFG_AIFSN             FIELD32(0x00000f00)
3426 +#define EDCA_AC1_CFG_CWMIN             FIELD32(0x0000f000)
3427 +#define EDCA_AC1_CFG_CWMAX             FIELD32(0x000f0000)
3428 +
3429 +/*
3430 + * EDCA_AC2_CFG:
3431 + */
3432 +#define EDCA_AC2_CFG                   0x1308
3433 +#define EDCA_AC2_CFG_AC_TX_OP          FIELD32(0x000000ff)
3434 +#define EDCA_AC2_CFG_AIFSN             FIELD32(0x00000f00)
3435 +#define EDCA_AC2_CFG_CWMIN             FIELD32(0x0000f000)
3436 +#define EDCA_AC2_CFG_CWMAX             FIELD32(0x000f0000)
3437 +
3438 +/*
3439 + * EDCA_AC3_CFG:
3440 + */
3441 +#define EDCA_AC3_CFG                   0x130c
3442 +#define EDCA_AC3_CFG_AC_TX_OP          FIELD32(0x000000ff)
3443 +#define EDCA_AC3_CFG_AIFSN             FIELD32(0x00000f00)
3444 +#define EDCA_AC3_CFG_CWMIN             FIELD32(0x0000f000)
3445 +#define EDCA_AC3_CFG_CWMAX             FIELD32(0x000f0000)
3446 +
3447 +/*
3448 + * EDCA_TID_AC_MAP:
3449 + */
3450 +#define EDCA_TID_AC_MAP                        0x1310
3451 +
3452 +/*
3453 + * TX_PWR_CFG_0:
3454 + */
3455 +#define TX_PWR_CFG_0                   0x1314
3456 +#define TX_PWR_CFG_0_1MBS              FIELD32(0x0000000f)
3457 +#define TX_PWR_CFG_0_2MBS              FIELD32(0x000000f0)
3458 +#define TX_PWR_CFG_0_55MBS             FIELD32(0x00000f00)
3459 +#define TX_PWR_CFG_0_11MBS             FIELD32(0x0000f000)
3460 +#define TX_PWR_CFG_0_6MBS              FIELD32(0x000f0000)
3461 +#define TX_PWR_CFG_0_9MBS              FIELD32(0x00f00000)
3462 +#define TX_PWR_CFG_0_12MBS             FIELD32(0x0f000000)
3463 +#define TX_PWR_CFG_0_18MBS             FIELD32(0xf0000000)
3464 +
3465 +/*
3466 + * TX_PWR_CFG_1:
3467 + */
3468 +#define TX_PWR_CFG_1                   0x1318
3469 +#define TX_PWR_CFG_1_24MBS             FIELD32(0x0000000f)
3470 +#define TX_PWR_CFG_1_36MBS             FIELD32(0x000000f0)
3471 +#define TX_PWR_CFG_1_48MBS             FIELD32(0x00000f00)
3472 +#define TX_PWR_CFG_1_54MBS             FIELD32(0x0000f000)
3473 +#define TX_PWR_CFG_1_MCS0              FIELD32(0x000f0000)
3474 +#define TX_PWR_CFG_1_MCS1              FIELD32(0x00f00000)
3475 +#define TX_PWR_CFG_1_MCS2              FIELD32(0x0f000000)
3476 +#define TX_PWR_CFG_1_MCS3              FIELD32(0xf0000000)
3477 +
3478 +/*
3479 + * TX_PWR_CFG_2:
3480 + */
3481 +#define TX_PWR_CFG_2                   0x131c
3482 +#define TX_PWR_CFG_2_MCS4              FIELD32(0x0000000f)
3483 +#define TX_PWR_CFG_2_MCS5              FIELD32(0x000000f0)
3484 +#define TX_PWR_CFG_2_MCS6              FIELD32(0x00000f00)
3485 +#define TX_PWR_CFG_2_MCS7              FIELD32(0x0000f000)
3486 +#define TX_PWR_CFG_2_MCS8              FIELD32(0x000f0000)
3487 +#define TX_PWR_CFG_2_MCS9              FIELD32(0x00f00000)
3488 +#define TX_PWR_CFG_2_MCS10             FIELD32(0x0f000000)
3489 +#define TX_PWR_CFG_2_MCS11             FIELD32(0xf0000000)
3490 +
3491 +/*
3492 + * TX_PWR_CFG_3:
3493 + */
3494 +#define TX_PWR_CFG_3                   0x1320
3495 +#define TX_PWR_CFG_3_MCS12             FIELD32(0x0000000f)
3496 +#define TX_PWR_CFG_3_MCS13             FIELD32(0x000000f0)
3497 +#define TX_PWR_CFG_3_MCS14             FIELD32(0x00000f00)
3498 +#define TX_PWR_CFG_3_MCS15             FIELD32(0x0000f000)
3499 +#define TX_PWR_CFG_3_UKNOWN1           FIELD32(0x000f0000)
3500 +#define TX_PWR_CFG_3_UKNOWN2           FIELD32(0x00f00000)
3501 +#define TX_PWR_CFG_3_UKNOWN3           FIELD32(0x0f000000)
3502 +#define TX_PWR_CFG_3_UKNOWN4           FIELD32(0xf0000000)
3503 +
3504 +/*
3505 + * TX_PWR_CFG_4:
3506 + */
3507 +#define TX_PWR_CFG_4                   0x1324
3508 +#define TX_PWR_CFG_4_UKNOWN5           FIELD32(0x0000000f)
3509 +#define TX_PWR_CFG_4_UKNOWN6           FIELD32(0x000000f0)
3510 +#define TX_PWR_CFG_4_UKNOWN7           FIELD32(0x00000f00)
3511 +#define TX_PWR_CFG_4_UKNOWN8           FIELD32(0x0000f000)
3512 +
3513 +/*
3514 + * TX_PIN_CFG:
3515 + */
3516 +#define TX_PIN_CFG                     0x1328
3517 +#define TX_PIN_CFG_PA_PE_A0_EN         FIELD32(0x00000001)
3518 +#define TX_PIN_CFG_PA_PE_G0_EN         FIELD32(0x00000002)
3519 +#define TX_PIN_CFG_PA_PE_A1_EN         FIELD32(0x00000004)
3520 +#define TX_PIN_CFG_PA_PE_G1_EN         FIELD32(0x00000008)
3521 +#define TX_PIN_CFG_PA_PE_A0_POL                FIELD32(0x00000010)
3522 +#define TX_PIN_CFG_PA_PE_G0_POL                FIELD32(0x00000020)
3523 +#define TX_PIN_CFG_PA_PE_A1_POL                FIELD32(0x00000040)
3524 +#define TX_PIN_CFG_PA_PE_G1_POL                FIELD32(0x00000080)
3525 +#define TX_PIN_CFG_LNA_PE_A0_EN                FIELD32(0x00000100)
3526 +#define TX_PIN_CFG_LNA_PE_G0_EN                FIELD32(0x00000200)
3527 +#define TX_PIN_CFG_LNA_PE_A1_EN                FIELD32(0x00000400)
3528 +#define TX_PIN_CFG_LNA_PE_G1_EN                FIELD32(0x00000800)
3529 +#define TX_PIN_CFG_LNA_PE_A0_POL       FIELD32(0x00001000)
3530 +#define TX_PIN_CFG_LNA_PE_G0_POL       FIELD32(0x00002000)
3531 +#define TX_PIN_CFG_LNA_PE_A1_POL       FIELD32(0x00004000)
3532 +#define TX_PIN_CFG_LNA_PE_G1_POL       FIELD32(0x00008000)
3533 +#define TX_PIN_CFG_RFTR_EN             FIELD32(0x00010000)
3534 +#define TX_PIN_CFG_RFTR_POL            FIELD32(0x00020000)
3535 +#define TX_PIN_CFG_TRSW_EN             FIELD32(0x00040000)
3536 +#define TX_PIN_CFG_TRSW_POL            FIELD32(0x00080000)
3537 +
3538 +/*
3539 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3540 + */
3541 +#define TX_BAND_CFG                    0x132c
3542 +#define TX_BAND_CFG_A                  FIELD32(0x00000002)
3543 +#define TX_BAND_CFG_BG                 FIELD32(0x00000004)
3544 +
3545 +/*
3546 + * TX_SW_CFG0:
3547 + */
3548 +#define TX_SW_CFG0                     0x1330
3549 +
3550 +/*
3551 + * TX_SW_CFG1:
3552 + */
3553 +#define TX_SW_CFG1                     0x1334
3554 +
3555 +/*
3556 + * TX_SW_CFG2:
3557 + */
3558 +#define TX_SW_CFG2                     0x1338
3559 +
3560 +/*
3561 + * TXOP_THRES_CFG:
3562 + */
3563 +#define TXOP_THRES_CFG                 0x133c
3564 +
3565 +/*
3566 + * TXOP_CTRL_CFG:
3567 + */
3568 +#define TXOP_CTRL_CFG                  0x1340
3569 +
3570 +/*
3571 + * TX_RTS_CFG:
3572 + * RTS_THRES: unit:byte
3573 + * RTS_FBK_EN: enable rts rate fallback
3574 + */
3575 +#define TX_RTS_CFG                     0x1344
3576 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT        FIELD32(0x000000ff)
3577 +#define TX_RTS_CFG_RTS_THRES           FIELD32(0x00ffff00)
3578 +#define TX_RTS_CFG_RTS_FBK_EN          FIELD32(0x01000000)
3579 +
3580 +/*
3581 + * TX_TIMEOUT_CFG:
3582 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3583 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3584 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3585 + *                it is recommended that:
3586 + *                (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3587 + */
3588 +#define TX_TIMEOUT_CFG                 0x1348
3589 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME   FIELD32(0x000000f0)
3590 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT  FIELD32(0x0000ff00)
3591 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT   FIELD32(0x00ff0000)
3592 +
3593 +/*
3594 + * TX_RTY_CFG:
3595 + * SHORT_RTY_LIMIT: short retry limit
3596 + * LONG_RTY_LIMIT: long retry limit
3597 + * LONG_RTY_THRE: Long retry threshoold
3598 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3599 + *                   0:expired by retry limit, 1: expired by mpdu life timer
3600 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3601 + *               0:expired by retry limit, 1: expired by mpdu life timer
3602 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3603 + */
3604 +#define TX_RTY_CFG                     0x134c
3605 +#define TX_RTY_CFG_SHORT_RTY_LIMIT     FIELD32(0x000000ff)
3606 +#define TX_RTY_CFG_LONG_RTY_LIMIT      FIELD32(0x0000ff00)
3607 +#define TX_RTY_CFG_LONG_RTY_THRE       FIELD32(0x0fff0000)
3608 +#define TX_RTY_CFG_NON_AGG_RTY_MODE    FIELD32(0x10000000)
3609 +#define TX_RTY_CFG_AGG_RTY_MODE                FIELD32(0x20000000)
3610 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE   FIELD32(0x40000000)
3611 +
3612 +/*
3613 + * TX_LINK_CFG:
3614 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3615 + * MFB_ENABLE: TX apply remote MFB 1:enable
3616 + * REMOTE_UMFS_ENABLE: remote unsolicit  MFB enable
3617 + *                     0: not apply remote remote unsolicit (MFS=7)
3618 + * TX_MRQ_EN: MCS request TX enable
3619 + * TX_RDG_EN: RDG TX enable
3620 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3621 + * REMOTE_MFB: remote MCS feedback
3622 + * REMOTE_MFS: remote MCS feedback sequence number
3623 + */
3624 +#define TX_LINK_CFG                    0x1350
3625 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME        FIELD32(0x000000ff)
3626 +#define TX_LINK_CFG_MFB_ENABLE         FIELD32(0x00000100)
3627 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3628 +#define TX_LINK_CFG_TX_MRQ_EN          FIELD32(0x00000400)
3629 +#define TX_LINK_CFG_TX_RDG_EN          FIELD32(0x00000800)
3630 +#define TX_LINK_CFG_TX_CF_ACK_EN       FIELD32(0x00001000)
3631 +#define TX_LINK_CFG_REMOTE_MFB         FIELD32(0x00ff0000)
3632 +#define TX_LINK_CFG_REMOTE_MFS         FIELD32(0xff000000)
3633 +
3634 +/*
3635 + * HT_FBK_CFG0:
3636 + */
3637 +#define HT_FBK_CFG0                    0x1354
3638 +#define HT_FBK_CFG0_HTMCS0FBK          FIELD32(0x0000000f)
3639 +#define HT_FBK_CFG0_HTMCS1FBK          FIELD32(0x000000f0)
3640 +#define HT_FBK_CFG0_HTMCS2FBK          FIELD32(0x00000f00)
3641 +#define HT_FBK_CFG0_HTMCS3FBK          FIELD32(0x0000f000)
3642 +#define HT_FBK_CFG0_HTMCS4FBK          FIELD32(0x000f0000)
3643 +#define HT_FBK_CFG0_HTMCS5FBK          FIELD32(0x00f00000)
3644 +#define HT_FBK_CFG0_HTMCS6FBK          FIELD32(0x0f000000)
3645 +#define HT_FBK_CFG0_HTMCS7FBK          FIELD32(0xf0000000)
3646 +
3647 +/*
3648 + * HT_FBK_CFG1:
3649 + */
3650 +#define HT_FBK_CFG1                    0x1358
3651 +#define HT_FBK_CFG1_HTMCS8FBK          FIELD32(0x0000000f)
3652 +#define HT_FBK_CFG1_HTMCS9FBK          FIELD32(0x000000f0)
3653 +#define HT_FBK_CFG1_HTMCS10FBK         FIELD32(0x00000f00)
3654 +#define HT_FBK_CFG1_HTMCS11FBK         FIELD32(0x0000f000)
3655 +#define HT_FBK_CFG1_HTMCS12FBK         FIELD32(0x000f0000)
3656 +#define HT_FBK_CFG1_HTMCS13FBK         FIELD32(0x00f00000)
3657 +#define HT_FBK_CFG1_HTMCS14FBK         FIELD32(0x0f000000)
3658 +#define HT_FBK_CFG1_HTMCS15FBK         FIELD32(0xf0000000)
3659 +
3660 +/*
3661 + * LG_FBK_CFG0:
3662 + */
3663 +#define LG_FBK_CFG0                    0x135c
3664 +#define LG_FBK_CFG0_OFDMMCS0FBK                FIELD32(0x0000000f)
3665 +#define LG_FBK_CFG0_OFDMMCS1FBK                FIELD32(0x000000f0)
3666 +#define LG_FBK_CFG0_OFDMMCS2FBK                FIELD32(0x00000f00)
3667 +#define LG_FBK_CFG0_OFDMMCS3FBK                FIELD32(0x0000f000)
3668 +#define LG_FBK_CFG0_OFDMMCS4FBK                FIELD32(0x000f0000)
3669 +#define LG_FBK_CFG0_OFDMMCS5FBK                FIELD32(0x00f00000)
3670 +#define LG_FBK_CFG0_OFDMMCS6FBK                FIELD32(0x0f000000)
3671 +#define LG_FBK_CFG0_OFDMMCS7FBK                FIELD32(0xf0000000)
3672 +
3673 +/*
3674 + * LG_FBK_CFG1:
3675 + */
3676 +#define LG_FBK_CFG1                    0x1360
3677 +#define LG_FBK_CFG0_CCKMCS0FBK         FIELD32(0x0000000f)
3678 +#define LG_FBK_CFG0_CCKMCS1FBK         FIELD32(0x000000f0)
3679 +#define LG_FBK_CFG0_CCKMCS2FBK         FIELD32(0x00000f00)
3680 +#define LG_FBK_CFG0_CCKMCS3FBK         FIELD32(0x0000f000)
3681 +
3682 +/*
3683 + * CCK_PROT_CFG: CCK Protection
3684 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3685 + * PROTECT_CTRL: Protection control frame type for CCK TX
3686 + *               0:none, 1:RTS/CTS, 2:CTS-to-self
3687 + * PROTECT_NAV: TXOP protection type for CCK TX
3688 + *              0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3689 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3690 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3691 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3692 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3693 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3694 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3695 + * RTS_TH_EN: RTS threshold enable on CCK TX
3696 + */
3697 +#define CCK_PROT_CFG                   0x1364
3698 +#define CCK_PROT_CFG_PROTECT_RATE      FIELD32(0x0000ffff)
3699 +#define CCK_PROT_CFG_PROTECT_CTRL      FIELD32(0x00030000)
3700 +#define CCK_PROT_CFG_PROTECT_NAV       FIELD32(0x000c0000)
3701 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK   FIELD32(0x00100000)
3702 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM  FIELD32(0x00200000)
3703 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20  FIELD32(0x00400000)
3704 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40  FIELD32(0x00800000)
3705 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20  FIELD32(0x01000000)
3706 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40  FIELD32(0x02000000)
3707 +#define CCK_PROT_CFG_RTS_TH_EN         FIELD32(0x04000000)
3708 +
3709 +/*
3710 + * OFDM_PROT_CFG: OFDM Protection
3711 + */
3712 +#define OFDM_PROT_CFG                  0x1368
3713 +#define OFDM_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3714 +#define OFDM_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3715 +#define OFDM_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3716 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3717 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3718 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3719 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3720 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3721 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3722 +#define OFDM_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3723 +
3724 +/*
3725 + * MM20_PROT_CFG: MM20 Protection
3726 + */
3727 +#define MM20_PROT_CFG                  0x136c
3728 +#define MM20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3729 +#define MM20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3730 +#define MM20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3731 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3732 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3733 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3734 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3735 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3736 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3737 +#define MM20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3738 +
3739 +/*
3740 + * MM40_PROT_CFG: MM40 Protection
3741 + */
3742 +#define MM40_PROT_CFG                  0x1370
3743 +#define MM40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3744 +#define MM40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3745 +#define MM40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3746 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3747 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3748 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3749 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3750 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3751 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3752 +#define MM40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3753 +
3754 +/*
3755 + * GF20_PROT_CFG: GF20 Protection
3756 + */
3757 +#define GF20_PROT_CFG                  0x1374
3758 +#define GF20_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3759 +#define GF20_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3760 +#define GF20_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3761 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3762 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3763 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3764 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3765 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3766 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3767 +#define GF20_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3768 +
3769 +/*
3770 + * GF40_PROT_CFG: GF40 Protection
3771 + */
3772 +#define GF40_PROT_CFG                  0x1378
3773 +#define GF40_PROT_CFG_PROTECT_RATE     FIELD32(0x0000ffff)
3774 +#define GF40_PROT_CFG_PROTECT_CTRL     FIELD32(0x00030000)
3775 +#define GF40_PROT_CFG_PROTECT_NAV      FIELD32(0x000c0000)
3776 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK  FIELD32(0x00100000)
3777 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3778 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3779 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3780 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3781 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3782 +#define GF40_PROT_CFG_RTS_TH_EN                FIELD32(0x04000000)
3783 +
3784 +/*
3785 + * EXP_CTS_TIME:
3786 + */
3787 +#define EXP_CTS_TIME                   0x137c
3788 +
3789 +/*
3790 + * EXP_ACK_TIME:
3791 + */
3792 +#define EXP_ACK_TIME                   0x1380
3793 +
3794 +/*
3795 + * RX_FILTER_CFG: RX configuration register.
3796 + */
3797 +#define RX_FILTER_CFG                  0x1400
3798 +#define RX_FILTER_CFG_DROP_CRC_ERROR   FIELD32(0x00000001)
3799 +#define RX_FILTER_CFG_DROP_PHY_ERROR   FIELD32(0x00000002)
3800 +#define RX_FILTER_CFG_DROP_NOT_TO_ME   FIELD32(0x00000004)
3801 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
3802 +#define RX_FILTER_CFG_DROP_VER_ERROR   FIELD32(0x00000010)
3803 +#define RX_FILTER_CFG_DROP_MULTICAST   FIELD32(0x00000020)
3804 +#define RX_FILTER_CFG_DROP_BROADCAST   FIELD32(0x00000040)
3805 +#define RX_FILTER_CFG_DROP_DUPLICATE   FIELD32(0x00000080)
3806 +#define RX_FILTER_CFG_DROP_CF_END_ACK  FIELD32(0x00000100)
3807 +#define RX_FILTER_CFG_DROP_CF_END      FIELD32(0x00000200)
3808 +#define RX_FILTER_CFG_DROP_ACK         FIELD32(0x00000400)
3809 +#define RX_FILTER_CFG_DROP_CTS         FIELD32(0x00000800)
3810 +#define RX_FILTER_CFG_DROP_RTS         FIELD32(0x00001000)
3811 +#define RX_FILTER_CFG_DROP_PSPOLL      FIELD32(0x00002000)
3812 +#define RX_FILTER_CFG_DROP_BA          FIELD32(0x00004000)
3813 +#define RX_FILTER_CFG_DROP_BAR         FIELD32(0x00008000)
3814 +#define RX_FILTER_CFG_DROP_CNTL                FIELD32(0x00010000)
3815 +
3816 +/*
3817 + * AUTO_RSP_CFG:
3818 + * AUTORESPONDER: 0: disable, 1: enable
3819 + * BAC_ACK_POLICY: 0:long, 1:short preamble
3820 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
3821 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
3822 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
3823 + * DUAL_CTS_EN: Power bit value in control frame
3824 + * ACK_CTS_PSM_BIT:Power bit value in control frame
3825 + */
3826 +#define AUTO_RSP_CFG                   0x1404
3827 +#define AUTO_RSP_CFG_AUTORESPONDER     FIELD32(0x00000001)
3828 +#define AUTO_RSP_CFG_BAC_ACK_POLICY    FIELD32(0x00000002)
3829 +#define AUTO_RSP_CFG_CTS_40_MMODE      FIELD32(0x00000004)
3830 +#define AUTO_RSP_CFG_CTS_40_MREF       FIELD32(0x00000008)
3831 +#define AUTO_RSP_CFG_AR_PREAMBLE       FIELD32(0x00000010)
3832 +#define AUTO_RSP_CFG_DUAL_CTS_EN       FIELD32(0x00000040)
3833 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT   FIELD32(0x00000080)
3834 +
3835 +/*
3836 + * LEGACY_BASIC_RATE:
3837 + */
3838 +#define LEGACY_BASIC_RATE              0x1408
3839 +
3840 +/*
3841 + * HT_BASIC_RATE:
3842 + */
3843 +#define HT_BASIC_RATE                  0x140c
3844 +
3845 +/*
3846 + * HT_CTRL_CFG:
3847 + */
3848 +#define HT_CTRL_CFG                    0x1410
3849 +
3850 +/*
3851 + * SIFS_COST_CFG:
3852 + */
3853 +#define SIFS_COST_CFG                  0x1414
3854 +
3855 +/*
3856 + * RX_PARSER_CFG:
3857 + * Set NAV for all received frames
3858 + */
3859 +#define RX_PARSER_CFG                  0x1418
3860 +
3861 +/*
3862 + * TX_SEC_CNT0:
3863 + */
3864 +#define TX_SEC_CNT0                    0x1500
3865 +
3866 +/*
3867 + * RX_SEC_CNT0:
3868 + */
3869 +#define RX_SEC_CNT0                    0x1504
3870 +
3871 +/*
3872 + * CCMP_FC_MUTE:
3873 + */
3874 +#define CCMP_FC_MUTE                   0x1508
3875 +
3876 +/*
3877 + * TXOP_HLDR_ADDR0:
3878 + */
3879 +#define TXOP_HLDR_ADDR0                        0x1600
3880 +
3881 +/*
3882 + * TXOP_HLDR_ADDR1:
3883 + */
3884 +#define TXOP_HLDR_ADDR1                        0x1604
3885 +
3886 +/*
3887 + * TXOP_HLDR_ET:
3888 + */
3889 +#define TXOP_HLDR_ET                   0x1608
3890 +
3891 +/*
3892 + * QOS_CFPOLL_RA_DW0:
3893 + */
3894 +#define QOS_CFPOLL_RA_DW0              0x160c
3895 +
3896 +/*
3897 + * QOS_CFPOLL_RA_DW1:
3898 + */
3899 +#define QOS_CFPOLL_RA_DW1              0x1610
3900 +
3901 +/*
3902 + * QOS_CFPOLL_QC:
3903 + */
3904 +#define QOS_CFPOLL_QC                  0x1614
3905 +
3906 +/*
3907 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
3908 + */
3909 +#define RX_STA_CNT0                    0x1700
3910 +#define RX_STA_CNT0_CRC_ERR            FIELD32(0x0000ffff)
3911 +#define RX_STA_CNT0_PHY_ERR            FIELD32(0xffff0000)
3912 +
3913 +/*
3914 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
3915 + */
3916 +#define RX_STA_CNT1                    0x1704
3917 +#define RX_STA_CNT1_FALSE_CCA          FIELD32(0x0000ffff)
3918 +#define RX_STA_CNT1_PLCP_ERR           FIELD32(0xffff0000)
3919 +
3920 +/*
3921 + * RX_STA_CNT2:
3922 + */
3923 +#define RX_STA_CNT2                    0x1708
3924 +#define RX_STA_CNT2_RX_DUPLI_COUNT     FIELD32(0x0000ffff)
3925 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW   FIELD32(0xffff0000)
3926 +
3927 +/*
3928 + * TX_STA_CNT0: TX Beacon count
3929 + */
3930 +#define TX_STA_CNT0                    0x170c
3931 +#define TX_STA_CNT0_TX_FAIL_COUNT      FIELD32(0x0000ffff)
3932 +#define TX_STA_CNT0_TX_BEACON_COUNT    FIELD32(0xffff0000)
3933 +
3934 +/*
3935 + * TX_STA_CNT1: TX tx count
3936 + */
3937 +#define TX_STA_CNT1                    0x1710
3938 +#define TX_STA_CNT1_TX_SUCCESS         FIELD32(0x0000ffff)
3939 +#define TX_STA_CNT1_TX_RETRANSMIT      FIELD32(0xffff0000)
3940 +
3941 +/*
3942 + * TX_STA_CNT2: TX tx count
3943 + */
3944 +#define TX_STA_CNT2                    0x1714
3945 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT  FIELD32(0x0000ffff)
3946 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT        FIELD32(0xffff0000)
3947 +
3948 +/*
3949 + * TX_STA_FIFO: TX Result for specific PID status fifo register
3950 + */
3951 +#define TX_STA_FIFO                    0x1718
3952 +#define TX_STA_FIFO_VALID              FIELD32(0x00000001)
3953 +#define TX_STA_FIFO_PID_TYPE           FIELD32(0x0000001e)
3954 +#define TX_STA_FIFO_TX_SUCCESS         FIELD32(0x00000020)
3955 +#define TX_STA_FIFO_TX_AGGRE           FIELD32(0x00000040)
3956 +#define TX_STA_FIFO_TX_ACK_REQUIRED    FIELD32(0x00000080)
3957 +#define TX_STA_FIFO_WCID               FIELD32(0x0000ff00)
3958 +#define TX_STA_FIFO_SUCCESS_RATE       FIELD32(0xffff0000)
3959 +
3960 +/*
3961 + * TX_AGG_CNT: Debug counter
3962 + */
3963 +#define TX_AGG_CNT                     0x171c
3964 +#define TX_AGG_CNT_NON_AGG_TX_COUNT    FIELD32(0x0000ffff)
3965 +#define TX_AGG_CNT_AGG_TX_COUNT                FIELD32(0xffff0000)
3966 +
3967 +/*
3968 + * TX_AGG_CNT0:
3969 + */
3970 +#define TX_AGG_CNT0                    0x1720
3971 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT   FIELD32(0x0000ffff)
3972 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT   FIELD32(0xffff0000)
3973 +
3974 +/*
3975 + * TX_AGG_CNT1:
3976 + */
3977 +#define TX_AGG_CNT1                    0x1724
3978 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT   FIELD32(0x0000ffff)
3979 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT   FIELD32(0xffff0000)
3980 +
3981 +/*
3982 + * TX_AGG_CNT2:
3983 + */
3984 +#define TX_AGG_CNT2                    0x1728
3985 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT   FIELD32(0x0000ffff)
3986 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT   FIELD32(0xffff0000)
3987 +
3988 +/*
3989 + * TX_AGG_CNT3:
3990 + */
3991 +#define TX_AGG_CNT3                    0x172c
3992 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT   FIELD32(0x0000ffff)
3993 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT   FIELD32(0xffff0000)
3994 +
3995 +/*
3996 + * TX_AGG_CNT4:
3997 + */
3998 +#define TX_AGG_CNT4                    0x1730
3999 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT   FIELD32(0x0000ffff)
4000 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT  FIELD32(0xffff0000)
4001 +
4002 +/*
4003 + * TX_AGG_CNT5:
4004 + */
4005 +#define TX_AGG_CNT5                    0x1734
4006 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT  FIELD32(0x0000ffff)
4007 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT  FIELD32(0xffff0000)
4008 +
4009 +/*
4010 + * TX_AGG_CNT6:
4011 + */
4012 +#define TX_AGG_CNT6                    0x1738
4013 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT  FIELD32(0x0000ffff)
4014 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT  FIELD32(0xffff0000)
4015 +
4016 +/*
4017 + * TX_AGG_CNT7:
4018 + */
4019 +#define TX_AGG_CNT7                    0x173c
4020 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT  FIELD32(0x0000ffff)
4021 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT  FIELD32(0xffff0000)
4022 +
4023 +/*
4024 + * MPDU_DENSITY_CNT:
4025 + * TX_ZERO_DEL: TX zero length delimiter count
4026 + * RX_ZERO_DEL: RX zero length delimiter count
4027 + */
4028 +#define MPDU_DENSITY_CNT               0x1740
4029 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL   FIELD32(0x0000ffff)
4030 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL   FIELD32(0xffff0000)
4031 +
4032 +/*
4033 + * Security key table memory, base address = 0x1800
4034 + */
4035 +struct hw_pairwise_ta_entry {
4036 +       u8 address[6];
4037 +       u8 reserved[2];
4038 +} __attribute__ ((packed));
4039 +
4040 +struct wcid_entry {
4041 +       u8 rx_ba_bitmat7;
4042 +       u8 rx_ba_bitmat0;
4043 +       u8 mac[6];
4044 +} __attribute__ ((packed));
4045 +
4046 +struct hw_key_entry {
4047 +       u8 key[16];
4048 +       u8 tx_mic[8];
4049 +       u8 rx_mic[8];
4050 +} __attribute__ ((packed));
4051 +
4052 +/*
4053 + * Security key table memory.
4054 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4055 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4056 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
4057 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4058 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4059 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4060 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
4061 + */
4062 +#define MAC_WCID_BASE                  0x1800
4063 +#define PAIRWISE_KEY_TABLE_BASE                0x4000
4064 +#define PAIRWISE_IVEIV_TABLE_BASE      0x6000
4065 +#define MAC_IVEIV_TABLE_BASE           0x6000
4066 +#define MAC_WCID_ATTRIBUTE_BASE                0x6800
4067 +#define SHARED_KEY_TABLE_BASE          0x6c00
4068 +#define SHARED_KEY_MODE_BASE           0x7000
4069 +
4070 +#define SHARED_KEY_ENTRY(__idx) \
4071 +       ( SHARED_KEY_TABLE_BASE + \
4072 +               ((__idx) * sizeof(struct hw_key_entry)) )
4073 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4074 +       ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4075 +#define PAIRWISE_KEY_ENTRY(__idx) \
4076 +       ( PAIRWISE_KEY_TABLE_BASE + \
4077 +               ((__idx) * sizeof(struct hw_key_entry)) )
4078 +
4079 +#define MAC_WCID_ENTRY(__idx) \
4080 +       ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
4081 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4082 +       ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4083 +
4084 +/*
4085 + * MAC_WCID_ATTRIBUTE:
4086 + * KEYTAB: 0: shared key table, 1: pairwise key table
4087 + * BSS_IDX: multipleBSS index for the WCID
4088 + */
4089 +#define MAC_WCID_ATTRIBUTE_KEYTAB      FIELD32(0x00000001)
4090 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE        FIELD32(0x0000000e)
4091 +#define MAC_WCID_ATTRIBUTE_BSS_IDX     FIELD32(0x00000070)
4092 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF    FIELD32(0x00000380)
4093 +
4094 +/*
4095 + * SHARED_KEY_MODE:
4096 + */
4097 +#define SHARED_KEY_MODE_BSS0_KEY0      FIELD32(0x00000007)
4098 +#define SHARED_KEY_MODE_BSS0_KEY1      FIELD32(0x00000070)
4099 +#define SHARED_KEY_MODE_BSS0_KEY2      FIELD32(0x00000700)
4100 +#define SHARED_KEY_MODE_BSS0_KEY3      FIELD32(0x00007000)
4101 +#define SHARED_KEY_MODE_BSS1_KEY0      FIELD32(0x00070000)
4102 +#define SHARED_KEY_MODE_BSS1_KEY1      FIELD32(0x00700000)
4103 +#define SHARED_KEY_MODE_BSS1_KEY2      FIELD32(0x07000000)
4104 +#define SHARED_KEY_MODE_BSS1_KEY3      FIELD32(0x70000000)
4105 +
4106 +/*
4107 + * HOST-MCU communication
4108 + */
4109 +
4110 +/*
4111 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4112 + */
4113 +#define H2M_MAILBOX_CSR                        0x7010
4114 +#define H2M_MAILBOX_CSR_ARG0           FIELD32(0x000000ff)
4115 +#define H2M_MAILBOX_CSR_ARG1           FIELD32(0x0000ff00)
4116 +#define H2M_MAILBOX_CSR_CMD_TOKEN      FIELD32(0x00ff0000)
4117 +#define H2M_MAILBOX_CSR_OWNER          FIELD32(0xff000000)
4118 +
4119 +/*
4120 + * H2M_MAILBOX_CID:
4121 + */
4122 +#define H2M_MAILBOX_CID                        0x7014
4123 +
4124 +/*
4125 + * H2M_MAILBOX_STATUS:
4126 + */
4127 +#define H2M_MAILBOX_STATUS             0x701c
4128 +
4129 +/*
4130 + * H2M_INT_SRC:
4131 + */
4132 +#define H2M_INT_SRC                    0x7024
4133 +
4134 +/*
4135 + * H2M_BBP_AGENT:
4136 + */
4137 +#define H2M_BBP_AGENT                  0x7028
4138 +
4139 +/*
4140 + * MCU_LEDCS: LED control for MCU Mailbox.
4141 + */
4142 +#define MCU_LEDCS_LED_MODE             FIELD8(0x1f)
4143 +#define MCU_LEDCS_POLARITY             FIELD8(0x01)
4144 +
4145 +/*
4146 + * HW_CS_CTS_BASE:
4147 + * Carrier-sense CTS frame base address.
4148 + * It's where mac stores carrier-sense frame for carrier-sense function.
4149 + */
4150 +#define HW_CS_CTS_BASE                 0x7700
4151 +
4152 +/*
4153 + * HW_DFS_CTS_BASE:
4154 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4155 + */
4156 +#define HW_DFS_CTS_BASE                        0x7780
4157 +
4158 +/*
4159 + * TXRX control registers - base address 0x3000
4160 + */
4161 +
4162 +/*
4163 + * TXRX_CSR1:
4164 + * rt2860b  UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4165 + */
4166 +#define TXRX_CSR1                      0x77d0
4167 +
4168 +/*
4169 + * HW_DEBUG_SETTING_BASE:
4170 + * since NULL frame won't be that long (256 byte)
4171 + * We steal 16 tail bytes to save debugging settings
4172 + */
4173 +#define HW_DEBUG_SETTING_BASE          0x77f0
4174 +#define HW_DEBUG_SETTING_BASE2         0x7770
4175 +
4176 +/*
4177 + * HW_BEACON_BASE
4178 + * In order to support maximum 8 MBSS and its maximum length
4179 + * is 512 bytes for each beacon
4180 + * Three section discontinue memory segments will be used.
4181 + * 1. The original region for BCN 0~3
4182 + * 2. Extract memory from FCE table for BCN 4~5
4183 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4184 + *    It occupied those memory of wcid 238~253 for BCN 6
4185 + *    and wcid 222~237 for BCN 7
4186 + *
4187 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4188 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4189 + */
4190 +#define HW_BEACON_BASE0                        0x7800
4191 +#define HW_BEACON_BASE1                        0x7a00
4192 +#define HW_BEACON_BASE2                        0x7c00
4193 +#define HW_BEACON_BASE3                        0x7e00
4194 +#define HW_BEACON_BASE4                        0x7200
4195 +#define HW_BEACON_BASE5                        0x7400
4196 +#define HW_BEACON_BASE6                        0x5dc0
4197 +#define HW_BEACON_BASE7                        0x5bc0
4198 +
4199 +#define HW_BEACON_OFFSET(__index) \
4200 +       ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4201 +         (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4202 +         (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4203 +
4204 +/*
4205 + * 8051 firmware image.
4206 + */
4207 +#define FIRMWARE_RT2860                        "rt2860.bin"
4208 +#define FIRMWARE_IMAGE_BASE            0x2000
4209 +
4210 +/*
4211 + * BBP registers.
4212 + * The wordsize of the BBP is 8 bits.
4213 + */
4214 +
4215 +/*
4216 + * BBP 1: TX Antenna
4217 + */
4218 +#define BBP1_TX_POWER                  FIELD8(0x07)
4219 +#define BBP1_TX_ANTENNA                        FIELD8(0x18)
4220 +
4221 +/*
4222 + * BBP 3: RX Antenna
4223 + */
4224 +#define BBP3_RX_ANTENNA                        FIELD8(0x18)
4225 +
4226 +/*
4227 + * RF registers
4228 + */
4229 +
4230 +/*
4231 + * RF 2
4232 + */
4233 +#define RF2_ANTENNA_RX2                        FIELD32(0x00000040)
4234 +#define RF2_ANTENNA_TX1                        FIELD32(0x00004000)
4235 +#define RF2_ANTENNA_RX1                        FIELD32(0x00020000)
4236 +
4237 +/*
4238 + * RF 3
4239 + */
4240 +#define RF3_TXPOWER_G                  FIELD32(0x00003e00)
4241 +#define RF3_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000200)
4242 +#define RF3_TXPOWER_A                  FIELD32(0x00003c00)
4243 +
4244 +/*
4245 + * RF 4
4246 + */
4247 +#define RF4_TXPOWER_G                  FIELD32(0x000007c0)
4248 +#define RF4_TXPOWER_A_7DBM_BOOST       FIELD32(0x00000040)
4249 +#define RF4_TXPOWER_A                  FIELD32(0x00000780)
4250 +#define RF4_FREQ_OFFSET                        FIELD32(0x001f8000)
4251 +#define RF4_BW40                       FIELD32(0x00200000)
4252 +
4253 +/*
4254 + * EEPROM content.
4255 + * The wordsize of the EEPROM is 16 bits.
4256 + */
4257 +
4258 +/*
4259 + * EEPROM Version
4260 + */
4261 +#define EEPROM_VERSION                 0x0001
4262 +#define EEPROM_VERSION_FAE             FIELD16(0x00ff)
4263 +#define EEPROM_VERSION_VERSION         FIELD16(0xff00)
4264 +
4265 +/*
4266 + * HW MAC address.
4267 + */
4268 +#define EEPROM_MAC_ADDR_0              0x0002
4269 +#define EEPROM_MAC_ADDR_BYTE0          FIELD16(0x00ff)
4270 +#define EEPROM_MAC_ADDR_BYTE1          FIELD16(0xff00)
4271 +#define EEPROM_MAC_ADDR_1              0x0003
4272 +#define EEPROM_MAC_ADDR_BYTE2          FIELD16(0x00ff)
4273 +#define EEPROM_MAC_ADDR_BYTE3          FIELD16(0xff00)
4274 +#define EEPROM_MAC_ADDR_2              0x0004
4275 +#define EEPROM_MAC_ADDR_BYTE4          FIELD16(0x00ff)
4276 +#define EEPROM_MAC_ADDR_BYTE5          FIELD16(0xff00)
4277 +
4278 +/*
4279 + * EEPROM ANTENNA config
4280 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4281 + * TXPATH: 1: 1T, 2: 2T
4282 + */
4283 +#define        EEPROM_ANTENNA                  0x001a
4284 +#define EEPROM_ANTENNA_RXPATH          FIELD16(0x000f)
4285 +#define EEPROM_ANTENNA_TXPATH          FIELD16(0x00f0)
4286 +#define EEPROM_ANTENNA_RF_TYPE         FIELD16(0x0f00)
4287 +
4288 +/*
4289 + * EEPROM NIC config
4290 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4291 + */
4292 +#define        EEPROM_NIC                      0x001b
4293 +#define EEPROM_NIC_HW_RADIO            FIELD16(0x0001)
4294 +#define EEPROM_NIC_DYNAMIC_TX_AGC      FIELD16(0x0002)
4295 +#define EEPROM_NIC_EXTERNAL_LNA_BG     FIELD16(0x0004)
4296 +#define EEPROM_NIC_EXTERNAL_LNA_A      FIELD16(0x0008)
4297 +#define EEPROM_NIC_CARDBUS_ACCEL       FIELD16(0x0010)
4298 +#define EEPROM_NIC_BW40M_SB_BG         FIELD16(0x0020)
4299 +#define EEPROM_NIC_BW40M_SB_A          FIELD16(0x0040)
4300 +#define EEPROM_NIC_WPS_PBC             FIELD16(0x0080)
4301 +#define EEPROM_NIC_BW40M_BG            FIELD16(0x0100)
4302 +#define EEPROM_NIC_BW40M_A             FIELD16(0x0200)
4303 +
4304 +/*
4305 + * EEPROM frequency
4306 + */
4307 +#define        EEPROM_FREQ                     0x001d
4308 +#define EEPROM_FREQ_OFFSET             FIELD16(0x00ff)
4309 +#define EEPROM_FREQ_LED_MODE           FIELD16(0x7f00)
4310 +#define EEPROM_FREQ_LED_POLARITY       FIELD16(0x1000)
4311 +
4312 +/*
4313 + * EEPROM LED
4314 + * POLARITY_RDY_G: Polarity RDY_G setting.
4315 + * POLARITY_RDY_A: Polarity RDY_A setting.
4316 + * POLARITY_ACT: Polarity ACT setting.
4317 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4318 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4319 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4320 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4321 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4322 + * LED_MODE: Led mode.
4323 + */
4324 +#define EEPROM_LED1                    0x001e
4325 +#define EEPROM_LED2                    0x001f
4326 +#define EEPROM_LED3                    0x0020
4327 +#define EEPROM_LED_POLARITY_RDY_BG     FIELD16(0x0001)
4328 +#define EEPROM_LED_POLARITY_RDY_A      FIELD16(0x0002)
4329 +#define EEPROM_LED_POLARITY_ACT                FIELD16(0x0004)
4330 +#define EEPROM_LED_POLARITY_GPIO_0     FIELD16(0x0008)
4331 +#define EEPROM_LED_POLARITY_GPIO_1     FIELD16(0x0010)
4332 +#define EEPROM_LED_POLARITY_GPIO_2     FIELD16(0x0020)
4333 +#define EEPROM_LED_POLARITY_GPIO_3     FIELD16(0x0040)
4334 +#define EEPROM_LED_POLARITY_GPIO_4     FIELD16(0x0080)
4335 +#define EEPROM_LED_LED_MODE            FIELD16(0x1f00)
4336 +
4337 +/*
4338 + * EEPROM LNA
4339 + */
4340 +#define EEPROM_LNA                     0x0022
4341 +#define EEPROM_LNA_BG                  FIELD16(0x00ff)
4342 +#define EEPROM_LNA_A0                  FIELD16(0xff00)
4343 +
4344 +/*
4345 + * EEPROM RSSI BG offset
4346 + */
4347 +#define EEPROM_RSSI_BG                 0x0023
4348 +#define EEPROM_RSSI_BG_OFFSET0         FIELD16(0x00ff)
4349 +#define EEPROM_RSSI_BG_OFFSET1         FIELD16(0xff00)
4350 +
4351 +/*
4352 + * EEPROM RSSI BG2 offset
4353 + */
4354 +#define EEPROM_RSSI_BG2                        0x0024
4355 +#define EEPROM_RSSI_BG2_OFFSET2                FIELD16(0x00ff)
4356 +#define EEPROM_RSSI_BG2_LNA_A1         FIELD16(0xff00)
4357 +
4358 +/*
4359 + * EEPROM RSSI A offset
4360 + */
4361 +#define EEPROM_RSSI_A                  0x0025
4362 +#define EEPROM_RSSI_A_OFFSET0          FIELD16(0x00ff)
4363 +#define EEPROM_RSSI_A_OFFSET1          FIELD16(0xff00)
4364 +
4365 +/*
4366 + * EEPROM RSSI A2 offset
4367 + */
4368 +#define EEPROM_RSSI_A2                 0x0026
4369 +#define EEPROM_RSSI_A2_OFFSET2         FIELD16(0x00ff)
4370 +#define EEPROM_RSSI_A2_LNA_A2          FIELD16(0xff00)
4371 +
4372 +/*
4373 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4374 + *     This is delta in 40MHZ.
4375 + * VALUE: Tx Power dalta value (MAX=4)
4376 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4377 + * TXPOWER: Enable:
4378 + */
4379 +#define EEPROM_TXPOWER_DELTA           0x0028
4380 +#define EEPROM_TXPOWER_DELTA_VALUE     FIELD16(0x003f)
4381 +#define EEPROM_TXPOWER_DELTA_TYPE      FIELD16(0x0040)
4382 +#define EEPROM_TXPOWER_DELTA_TXPOWER   FIELD16(0x0080)
4383 +
4384 +/*
4385 + * EEPROM TXPOWER 802.11G
4386 + */
4387 +#define        EEPROM_TXPOWER_BG1              0x0029
4388 +#define        EEPROM_TXPOWER_BG2              0x0030
4389 +#define EEPROM_TXPOWER_BG_SIZE         7
4390 +#define EEPROM_TXPOWER_BG_1            FIELD16(0x00ff)
4391 +#define EEPROM_TXPOWER_BG_2            FIELD16(0xff00)
4392 +
4393 +/*
4394 + * EEPROM TXPOWER 802.11A
4395 + */
4396 +#define EEPROM_TXPOWER_A1              0x003c
4397 +#define EEPROM_TXPOWER_A2              0x0053
4398 +#define EEPROM_TXPOWER_A_SIZE          6
4399 +#define EEPROM_TXPOWER_A_1             FIELD16(0x00ff)
4400 +#define EEPROM_TXPOWER_A_2             FIELD16(0xff00)
4401 +
4402 +/*
4403 + * EEPROM TXpower byrate: 20MHZ power
4404 + */
4405 +#define EEPROM_TXPOWER_BYRATE          0x006f
4406 +
4407 +/*
4408 + * EEPROM BBP.
4409 + */
4410 +#define        EEPROM_BBP_START                0x0078
4411 +#define EEPROM_BBP_SIZE                        16
4412 +#define EEPROM_BBP_VALUE               FIELD16(0x00ff)
4413 +#define EEPROM_BBP_REG_ID              FIELD16(0xff00)
4414 +
4415 +/*
4416 + * MCU mailbox commands.
4417 + */
4418 +#define MCU_SLEEP                      0x30
4419 +#define MCU_WAKEUP                     0x31
4420 +#define MCU_LED                                0x50
4421 +#define MCU_LED_STRENGTH               0x51
4422 +#define MCU_LED_1                      0x52
4423 +#define MCU_LED_2                      0x53
4424 +#define MCU_LED_3                      0x54
4425 +#define MCU_RADAR                      0x60
4426 +#define MCU_BOOT_SIGNAL                        0x72
4427 +
4428 +/*
4429 + * DMA descriptor defines.
4430 + */
4431 +#define TXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
4432 +#define TXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4433 +#define RXD_DESC_SIZE                  ( 4 * sizeof(__le32) )
4434 +#define RXWI_DESC_SIZE                 ( 4 * sizeof(__le32) )
4435 +
4436 +/*
4437 + * TX descriptor format for TX, PRIO and Beacon Ring.
4438 + */
4439 +
4440 +/*
4441 + * Word0
4442 + */
4443 +#define TXD_W0_SD_PTR0                 FIELD32(0xffffffff)
4444 +
4445 +/*
4446 + * Word1
4447 + */
4448 +#define TXD_W1_SD_LEN1                 FIELD32(0x00003fff)
4449 +#define TXD_W1_LAST_SEC1               FIELD32(0x00004000)
4450 +#define TXD_W1_BURST                   FIELD32(0x00008000)
4451 +#define TXD_W1_SD_LEN0                 FIELD32(0x3fff0000)
4452 +#define TXD_W1_LAST_SEC0               FIELD32(0x40000000)
4453 +#define TXD_W1_DMA_DONE                        FIELD32(0x80000000)
4454 +
4455 +/*
4456 + * Word2
4457 + */
4458 +#define TXD_W2_SD_PTR1                 FIELD32(0xffffffff)
4459 +
4460 +/*
4461 + * Word3
4462 + * WIV: Wireless Info Valid. 1: Driver filled WI,  0: DMA needs to copy WI
4463 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4464 + *       0:MGMT, 1:HCCA 2:EDCA
4465 + */
4466 +#define TXD_W3_WIV                     FIELD32(0x01000000)
4467 +#define TXD_W3_QSEL                    FIELD32(0x06000000)
4468 +#define TXD_W3_TCO                     FIELD32(0x20000000)
4469 +#define TXD_W3_UCO                     FIELD32(0x40000000)
4470 +#define TXD_W3_ICO                     FIELD32(0x80000000)
4471 +
4472 +/*
4473 + * TX WI structure
4474 + */
4475 +
4476 +/*
4477 + * Word0
4478 + * FRAG: 1 To inform TKIP engine this is a fragment.
4479 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4480 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4481 + * BW: Channel bandwidth 20MHz or 40 MHz
4482 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4483 + */
4484 +#define TXWI_W0_FRAG                   FIELD32(0x00000001)
4485 +#define TXWI_W0_MIMO_PS                        FIELD32(0x00000002)
4486 +#define TXWI_W0_CF_ACK                 FIELD32(0x00000004)
4487 +#define TXWI_W0_TS                     FIELD32(0x00000008)
4488 +#define TXWI_W0_AMPDU                  FIELD32(0x00000010)
4489 +#define TXWI_W0_MPDU_DENSITY           FIELD32(0x000000e0)
4490 +#define TXWI_W0_TX_OP                  FIELD32(0x00000300)
4491 +#define TXWI_W0_MCS                    FIELD32(0x007f0000)
4492 +#define TXWI_W0_BW                     FIELD32(0x00800000)
4493 +#define TXWI_W0_SHORT_GI               FIELD32(0x01000000)
4494 +#define TXWI_W0_STBC                   FIELD32(0x06000000)
4495 +#define TXWI_W0_IFS                    FIELD32(0x08000000)
4496 +#define TXWI_W0_PHYMODE                        FIELD32(0xc0000000)
4497 +
4498 +/*
4499 + * Word1
4500 + */
4501 +#define TXWI_W1_ACK                    FIELD32(0x00000001)
4502 +#define TXWI_W1_NSEQ                   FIELD32(0x00000002)
4503 +#define TXWI_W1_BW_WIN_SIZE            FIELD32(0x000000fc)
4504 +#define TXWI_W1_WIRELESS_CLI_ID                FIELD32(0x0000ff00)
4505 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4506 +#define TXWI_W1_PACKETID               FIELD32(0xf0000000)
4507 +
4508 +/*
4509 + * Word2
4510 + */
4511 +#define TXWI_W2_IV                     FIELD32(0xffffffff)
4512 +
4513 +/*
4514 + * Word3
4515 + */
4516 +#define TXWI_W3_EIV                    FIELD32(0xffffffff)
4517 +
4518 +/*
4519 + * RX descriptor format for RX Ring.
4520 + */
4521 +
4522 +/*
4523 + * Word0
4524 + */
4525 +#define RXD_W0_SDP0                    FIELD32(0xffffffff)
4526 +
4527 +/*
4528 + * Word1
4529 + */
4530 +#define RXD_W1_SDL1                    FIELD32(0x00003fff)
4531 +#define RXD_W1_SDL0                    FIELD32(0x3fff0000)
4532 +#define RXD_W1_LS0                     FIELD32(0x40000000)
4533 +#define RXD_W1_DMA_DONE                        FIELD32(0x80000000)
4534 +
4535 +/*
4536 + * Word2
4537 + */
4538 +#define RXD_W2_SDP1                    FIELD32(0xffffffff)
4539 +
4540 +/*
4541 + * Word3
4542 + * AMSDU: RX with 802.3 header, not 802.11 header.
4543 + * DECRYPTED: This frame is being decrypted.
4544 + */
4545 +#define RXD_W3_BA                      FIELD32(0x00000001)
4546 +#define RXD_W3_DATA                    FIELD32(0x00000002)
4547 +#define RXD_W3_NULLDATA                        FIELD32(0x00000004)
4548 +#define RXD_W3_FRAG                    FIELD32(0x00000008)
4549 +#define RXD_W3_UNICAST_TO_ME           FIELD32(0x00000010)
4550 +#define RXD_W3_MULTICAST               FIELD32(0x00000020)
4551 +#define RXD_W3_BROADCAST               FIELD32(0x00000040)
4552 +#define RXD_W3_MY_BSS                  FIELD32(0x00000080)
4553 +#define RXD_W3_CRC_ERROR               FIELD32(0x00000100)
4554 +#define RXD_W3_CIPHER_ERROR            FIELD32(0x00000600)
4555 +#define RXD_W3_AMSDU                   FIELD32(0x00000800)
4556 +#define RXD_W3_HTC                     FIELD32(0x00001000)
4557 +#define RXD_W3_RSSI                    FIELD32(0x00002000)
4558 +#define RXD_W3_L2PAD                   FIELD32(0x00004000)
4559 +#define RXD_W3_AMPDU                   FIELD32(0x00008000)
4560 +#define RXD_W3_DECRYPTED               FIELD32(0x00010000)
4561 +#define RXD_W3_PLCP_SIGNAL             FIELD32(0x00020000)
4562 +#define RXD_W3_PLCP_RSSI               FIELD32(0x00040000)
4563 +
4564 +/*
4565 + * RX WI structure
4566 + */
4567 +
4568 +/*
4569 + * Word0
4570 + */
4571 +#define RXWI_W0_WIRELESS_CLI_ID                FIELD32(0x000000ff)
4572 +#define RXWI_W0_KEY_INDEX              FIELD32(0x00000300)
4573 +#define RXWI_W0_BSSID                  FIELD32(0x00001c00)
4574 +#define RXWI_W0_UDF                    FIELD32(0x0000e000)
4575 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT  FIELD32(0x0fff0000)
4576 +#define RXWI_W0_TID                    FIELD32(0xf0000000)
4577 +
4578 +/*
4579 + * Word1
4580 + */
4581 +#define RXWI_W1_FRAG                   FIELD32(0x0000000f)
4582 +#define RXWI_W1_SEQUENCE               FIELD32(0x0000fff0)
4583 +#define RXWI_W1_MCS                    FIELD32(0x007f0000)
4584 +#define RXWI_W1_BW                     FIELD32(0x00800000)
4585 +#define RXWI_W1_SHORT_GI               FIELD32(0x01000000)
4586 +#define RXWI_W1_STBC                   FIELD32(0x06000000)
4587 +#define RXWI_W1_PHYMODE                        FIELD32(0xc0000000)
4588 +
4589 +/*
4590 + * Word2
4591 + */
4592 +#define RXWI_W2_RSSI0                  FIELD32(0x000000ff)
4593 +#define RXWI_W2_RSSI1                  FIELD32(0x0000ff00)
4594 +#define RXWI_W2_RSSI2                  FIELD32(0x00ff0000)
4595 +
4596 +/*
4597 + * Word3
4598 + */
4599 +#define RXWI_W3_SNR0                   FIELD32(0x000000ff)
4600 +#define RXWI_W3_SNR1                   FIELD32(0x0000ff00)
4601 +
4602 +/*
4603 + * Macro's for converting txpower from EEPROM to mac80211 value
4604 + * and from mac80211 value to register value.
4605 + */
4606 +#define MIN_G_TXPOWER  0
4607 +#define MIN_A_TXPOWER  -7
4608 +#define MAX_G_TXPOWER  31
4609 +#define MAX_A_TXPOWER  15
4610 +#define DEFAULT_TXPOWER        5
4611 +
4612 +#define TXPOWER_G_FROM_DEV(__txpower) \
4613 +       ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4614 +
4615 +#define TXPOWER_G_TO_DEV(__txpower) \
4616 +       clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4617 +
4618 +#define TXPOWER_A_FROM_DEV(__txpower) \
4619 +       ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4620 +
4621 +#define TXPOWER_A_TO_DEV(__txpower) \
4622 +       clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4623 +
4624 +#endif /* RT2800PCI_H */
4625 --- a/drivers/net/wireless/rt2x00/rt2x00.h
4626 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
4627 @@ -139,6 +139,10 @@ struct rt2x00_chip {
4628  #define RT2561         0x0302
4629  #define RT2661         0x0401
4630  #define RT2571         0x1300
4631 +#define RT2860         0x0601  /* 2.4GHz PCI/CB */
4632 +#define RT2860D                0x0681  /* 2.4GHz, 5GHz PCI/CB */
4633 +#define RT2890         0x0701  /* 2.4GHz PCIe */
4634 +#define RT2890D                0x0781  /* 2.4GHz, 5GHz PCIe */
4635
4636         u16 rf;
4637         u32 rev;