1 /******************************************************************************
3 ** FILE NAME : ifxmips_atm_danube.c
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
27 * ####################################
29 * ####################################
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <asm/delay.h>
46 * Chip Specific Head File
48 #include <asm/ifx/ifx_types.h>
49 #include <asm/ifx/ifx_regs.h>
50 #include <asm/ifx/common_routines.h>
51 #include <asm/ifx/ifx_pmu.h>
52 #include "ifxmips_atm_core.h"
53 #include "ifxmips_atm_fw_danube.h"
58 * ####################################
60 * ####################################
66 #define EMA_CMD_BUF_LEN 0x0040
67 #define EMA_CMD_BASE_ADDR (0x00001580 << 2)
68 #define EMA_DATA_BUF_LEN 0x0100
69 #define EMA_DATA_BASE_ADDR (0x00001900 << 2)
70 #define EMA_WRITE_BURST 0x2
71 #define EMA_READ_BURST 0x2
76 * ####################################
78 * ####################################
82 * Hardware Init/Uninit Functions
84 static inline void init_pmu(void);
85 static inline void uninit_pmu(void);
86 static inline void init_ema(void);
87 static inline void init_mailbox(void);
88 static inline void init_atm_tc(void);
89 static inline void clear_share_buffer(void);
94 * ####################################
96 * ####################################
102 * ####################################
104 * ####################################
107 static inline void init_pmu(void)
109 //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
110 PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
111 PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
112 PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
113 PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
114 PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
115 PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
116 DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
119 static inline void uninit_pmu(void)
121 PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
122 PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
123 PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
124 PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
125 PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
126 DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
127 PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
130 static inline void init_ema(void)
132 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
133 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
134 IFX_REG_W32(0x000000FF, EMA_IER);
135 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
138 static inline void init_mailbox(void)
140 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
141 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
142 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
143 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
146 static inline void init_atm_tc(void)
148 // for ReTX expansion in future
149 //*FFSM_CFG0 = SET_BITS(*FFSM_CFG0, 5, 0, 6); // pnum = 6
150 //*FFSM_CFG1 = SET_BITS(*FFSM_CFG1, 5, 0, 6); // pnum = 6
153 static inline void clear_share_buffer(void)
155 volatile u32 *p = SB_RAM0_ADDR(0);
158 for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
164 * Download PPE firmware binary code.
166 * src --- u32 *, binary code buffer
167 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
169 * int --- IFX_SUCCESS: Success
172 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
176 if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
177 || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
180 if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
181 IFX_REG_W32(0x00, CDM_CFG);
183 IFX_REG_W32(0x02, CDM_CFG);
186 dest = CDM_CODE_MEMORY(0, 0);
187 while ( code_dword_len-- > 0 )
188 IFX_REG_W32(*code_src++, dest++);
191 dest = CDM_DATA_MEMORY(0, 0);
192 while ( data_dword_len-- > 0 )
193 IFX_REG_W32(*data_src++, dest++);
201 * ####################################
203 * ####################################
206 extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
208 ASSERT(major != NULL, "pointer is NULL");
209 ASSERT(minor != NULL, "pointer is NULL");
211 *major = ATM_FW_VER_MAJOR;
212 *minor = ATM_FW_VER_MINOR;
215 void ifx_atm_init_chip(void)
225 clear_share_buffer();
228 void ifx_atm_uninit_chip(void)
235 * Initialize and start up PP32.
239 * int --- IFX_SUCCESS: Success
242 int ifx_pp32_start(int pp32)
246 /* download firmware */
247 ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
248 if ( ret != IFX_SUCCESS )
252 IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
254 /* idle for a while to let PP32 init itself */
268 void ifx_pp32_stop(int pp32)
271 IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);