package/b43/src/main.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "b43.h"
  45 #include "main.h"
  46 #include "debugfs.h"
  47 #include "phy.h"
  48 #include "dma.h"
  49 #include "pio.h"
  50 #include "sysfs.h"
  51 #include "xmit.h"
  52 #include "sysfs.h"
  53 #include "lo.h"
  54 #include "pcmcia.h"
  55
  56 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  57 MODULE_AUTHOR("Martin Langer");
  58 MODULE_AUTHOR("Stefano Brivio");
  59 MODULE_AUTHOR("Michael Buesch");
  60 MODULE_LICENSE("GPL");
  61
  62 extern char *nvram_get(char *name);
  63
  64 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
  65 static int modparam_pio;
  66 module_param_named(pio, modparam_pio, int, 0444);
  67 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  68 #elif defined(CONFIG_B43_DMA)
  69 # define modparam_pio   0
  70 #elif defined(CONFIG_B43_PIO)
  71 # define modparam_pio   1
  72 #endif
  73
  74 static int modparam_bad_frames_preempt;
  75 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  76 MODULE_PARM_DESC(bad_frames_preempt,
  77                  "enable(1) / disable(0) Bad Frames Preemption");
  78
  79 static int modparam_short_retry = B43_DEFAULT_SHORT_RETRY_LIMIT;
  80 module_param_named(short_retry, modparam_short_retry, int, 0444);
  81 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
  82
  83 static int modparam_long_retry = B43_DEFAULT_LONG_RETRY_LIMIT;
  84 module_param_named(long_retry, modparam_long_retry, int, 0444);
  85 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
  86
  87 static char modparam_fwpostfix[16];
  88 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  89 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  90
  91 static int modparam_hwpctl;
  92 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  93 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  94
  95 static int modparam_nohwcrypt;
  96 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  97 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  98
  99 static const struct ssb_device_id b43_ssb_tbl[] = {
 100         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
 101         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
 102         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
 103         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
 104         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
 105         SSB_DEVTABLE_END
 106 };
 107
 108 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
 109
 110 /* Channel and ratetables are shared for all devices.
 111  * They can't be const, because ieee80211 puts some precalculated
 112  * data in there. This data is the same for all devices, so we don't
 113  * get concurrency issues */
 114 #define RATETAB_ENT(_rateid, _flags) \
 115         {                                                       \
 116                 .rate   = B43_RATE_TO_BASE100KBPS(_rateid),     \
 117                 .val    = (_rateid),                            \
 118                 .val2   = (_rateid),                            \
 119                 .flags  = (_flags),                             \
 120         }
 121 static struct ieee80211_rate __b43_ratetable[] = {
 122         RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
 123         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
 124         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
 125         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
 126         RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
 127         RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
 128         RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
 129         RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
 130         RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
 131         RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
 132         RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
 133         RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
 134 };
 135
 136 #define b43_a_ratetable         (__b43_ratetable + 4)
 137 #define b43_a_ratetable_size    8
 138 #define b43_b_ratetable         (__b43_ratetable + 0)
 139 #define b43_b_ratetable_size    4
 140 #define b43_g_ratetable         (__b43_ratetable + 0)
 141 #define b43_g_ratetable_size    12
 142
 143 #define CHANTAB_ENT(_chanid, _freq) \
 144         {                                                       \
 145                 .chan   = (_chanid),                            \
 146                 .freq   = (_freq),                              \
 147                 .val    = (_chanid),                            \
 148                 .flag   = IEEE80211_CHAN_W_SCAN |               \
 149                           IEEE80211_CHAN_W_ACTIVE_SCAN |        \
 150                           IEEE80211_CHAN_W_IBSS,                \
 151                 .power_level    = 0xFF,                         \
 152                 .antenna_max    = 0xFF,                         \
 153         }
 154 static struct ieee80211_channel b43_bg_chantable[] = {
 155         CHANTAB_ENT(1, 2412),
 156         CHANTAB_ENT(2, 2417),
 157         CHANTAB_ENT(3, 2422),
 158         CHANTAB_ENT(4, 2427),
 159         CHANTAB_ENT(5, 2432),
 160         CHANTAB_ENT(6, 2437),
 161         CHANTAB_ENT(7, 2442),
 162         CHANTAB_ENT(8, 2447),
 163         CHANTAB_ENT(9, 2452),
 164         CHANTAB_ENT(10, 2457),
 165         CHANTAB_ENT(11, 2462),
 166         CHANTAB_ENT(12, 2467),
 167         CHANTAB_ENT(13, 2472),
 168         CHANTAB_ENT(14, 2484),
 169 };
 170
 171 #define b43_bg_chantable_size   ARRAY_SIZE(b43_bg_chantable)
 172 static struct ieee80211_channel b43_a_chantable[] = {
 173         CHANTAB_ENT(36, 5180),
 174         CHANTAB_ENT(40, 5200),
 175         CHANTAB_ENT(44, 5220),
 176         CHANTAB_ENT(48, 5240),
 177         CHANTAB_ENT(52, 5260),
 178         CHANTAB_ENT(56, 5280),
 179         CHANTAB_ENT(60, 5300),
 180         CHANTAB_ENT(64, 5320),
 181         CHANTAB_ENT(149, 5745),
 182         CHANTAB_ENT(153, 5765),
 183         CHANTAB_ENT(157, 5785),
 184         CHANTAB_ENT(161, 5805),
 185         CHANTAB_ENT(165, 5825),
 186 };
 187
 188 #define b43_a_chantable_size    ARRAY_SIZE(b43_a_chantable)
 189
 190 static void b43_wireless_core_exit(struct b43_wldev *dev);
 191 static int b43_wireless_core_init(struct b43_wldev *dev);
 192 static void b43_wireless_core_stop(struct b43_wldev *dev);
 193 static int b43_wireless_core_start(struct b43_wldev *dev);
 194
 195 static int b43_ratelimit(struct b43_wl *wl)
 196 {
 197         if (!wl || !wl->current_dev)
 198                 return 1;
 199         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 200                 return 1;
 201         /* We are up and running.
 202          * Ratelimit the messages to avoid DoS over the net. */
 203         return net_ratelimit();
 204 }
 205
 206 void b43info(struct b43_wl *wl, const char *fmt, ...)
 207 {
 208         va_list args;
 209
 210         if (!b43_ratelimit(wl))
 211                 return;
 212         va_start(args, fmt);
 213         printk(KERN_INFO "b43-%s: ",
 214                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 215         vprintk(fmt, args);
 216         va_end(args);
 217 }
 218
 219 void b43err(struct b43_wl *wl, const char *fmt, ...)
 220 {
 221         va_list args;
 222
 223         if (!b43_ratelimit(wl))
 224                 return;
 225         va_start(args, fmt);
 226         printk(KERN_ERR "b43-%s ERROR: ",
 227                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 228         vprintk(fmt, args);
 229         va_end(args);
 230 }
 231
 232 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 233 {
 234         va_list args;
 235
 236         if (!b43_ratelimit(wl))
 237                 return;
 238         va_start(args, fmt);
 239         printk(KERN_WARNING "b43-%s warning: ",
 240                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 241         vprintk(fmt, args);
 242         va_end(args);
 243 }
 244
 245 #if B43_DEBUG
 246 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 247 {
 248         va_list args;
 249
 250         va_start(args, fmt);
 251         printk(KERN_DEBUG "b43-%s debug: ",
 252                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 253         vprintk(fmt, args);
 254         va_end(args);
 255 }
 256 #endif /* DEBUG */
 257
 258 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 259 {
 260         u32 macctl;
 261
 262         B43_WARN_ON(offset % 4 != 0);
 263
 264         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 265         if (macctl & B43_MACCTL_BE)
 266                 val = swab32(val);
 267
 268         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 269         mmiowb();
 270         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 271 }
 272
 273 static inline
 274     void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
 275 {
 276         u32 control;
 277
 278         /* "offset" is the WORD offset. */
 279
 280         control = routing;
 281         control <<= 16;
 282         control |= offset;
 283         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 284 }
 285
 286 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 287 {
 288         u32 ret;
 289
 290         if (routing == B43_SHM_SHARED) {
 291                 B43_WARN_ON(offset & 0x0001);
 292                 if (offset & 0x0003) {
 293                         /* Unaligned access */
 294                         b43_shm_control_word(dev, routing, offset >> 2);
 295                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 296                         ret <<= 16;
 297                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 298                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 299
 300                         return ret;
 301                 }
 302                 offset >>= 2;
 303         }
 304         b43_shm_control_word(dev, routing, offset);
 305         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 306
 307         return ret;
 308 }
 309
 310 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 311 {
 312         u16 ret;
 313
 314         if (routing == B43_SHM_SHARED) {
 315                 B43_WARN_ON(offset & 0x0001);
 316                 if (offset & 0x0003) {
 317                         /* Unaligned access */
 318                         b43_shm_control_word(dev, routing, offset >> 2);
 319                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 320
 321                         return ret;
 322                 }
 323                 offset >>= 2;
 324         }
 325         b43_shm_control_word(dev, routing, offset);
 326         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 327
 328         return ret;
 329 }
 330
 331 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 332 {
 333         if (routing == B43_SHM_SHARED) {
 334                 B43_WARN_ON(offset & 0x0001);
 335                 if (offset & 0x0003) {
 336                         /* Unaligned access */
 337                         b43_shm_control_word(dev, routing, offset >> 2);
 338                         mmiowb();
 339                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 340                                     (value >> 16) & 0xffff);
 341                         mmiowb();
 342                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 343                         mmiowb();
 344                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 345                         return;
 346                 }
 347                 offset >>= 2;
 348         }
 349         b43_shm_control_word(dev, routing, offset);
 350         mmiowb();
 351         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 352 }
 353
 354 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 355 {
 356         if (routing == B43_SHM_SHARED) {
 357                 B43_WARN_ON(offset & 0x0001);
 358                 if (offset & 0x0003) {
 359                         /* Unaligned access */
 360                         b43_shm_control_word(dev, routing, offset >> 2);
 361                         mmiowb();
 362                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 363                         return;
 364                 }
 365                 offset >>= 2;
 366         }
 367         b43_shm_control_word(dev, routing, offset);
 368         mmiowb();
 369         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 370 }
 371
 372 /* Read HostFlags */
 373 u32 b43_hf_read(struct b43_wldev * dev)
 374 {
 375         u32 ret;
 376
 377         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 378         ret <<= 16;
 379         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 380
 381         return ret;
 382 }
 383
 384 /* Write HostFlags */
 385 void b43_hf_write(struct b43_wldev *dev, u32 value)
 386 {
 387         b43_shm_write16(dev, B43_SHM_SHARED,
 388                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 389         b43_shm_write16(dev, B43_SHM_SHARED,
 390                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 391 }
 392
 393 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 394 {
 395         /* We need to be careful. As we read the TSF from multiple
 396          * registers, we should take care of register overflows.
 397          * In theory, the whole tsf read process should be atomic.
 398          * We try to be atomic here, by restaring the read process,
 399          * if any of the high registers changed (overflew).
 400          */
 401         if (dev->dev->id.revision >= 3) {
 402                 u32 low, high, high2;
 403
 404                 do {
 405                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 406                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 407                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 408                 } while (unlikely(high != high2));
 409
 410                 *tsf = high;
 411                 *tsf <<= 32;
 412                 *tsf |= low;
 413         } else {
 414                 u64 tmp;
 415                 u16 v0, v1, v2, v3;
 416                 u16 test1, test2, test3;
 417
 418                 do {
 419                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 420                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 421                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 422                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 423
 424                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 425                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 426                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 427                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 428
 429                 *tsf = v3;
 430                 *tsf <<= 48;
 431                 tmp = v2;
 432                 tmp <<= 32;
 433                 *tsf |= tmp;
 434                 tmp = v1;
 435                 tmp <<= 16;
 436                 *tsf |= tmp;
 437                 *tsf |= v0;
 438         }
 439 }
 440
 441 static void b43_time_lock(struct b43_wldev *dev)
 442 {
 443         u32 macctl;
 444
 445         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 446         macctl |= B43_MACCTL_TBTTHOLD;
 447         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 448         /* Commit the write */
 449         b43_read32(dev, B43_MMIO_MACCTL);
 450 }
 451
 452 static void b43_time_unlock(struct b43_wldev *dev)
 453 {
 454         u32 macctl;
 455
 456         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 457         macctl &= ~B43_MACCTL_TBTTHOLD;
 458         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 459         /* Commit the write */
 460         b43_read32(dev, B43_MMIO_MACCTL);
 461 }
 462
 463 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 464 {
 465         /* Be careful with the in-progress timer.
 466          * First zero out the low register, so we have a full
 467          * register-overflow duration to complete the operation.
 468          */
 469         if (dev->dev->id.revision >= 3) {
 470                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 471                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 472
 473                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 474                 mmiowb();
 475                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 476                 mmiowb();
 477                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 478         } else {
 479                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 480                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 481                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 482                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 483
 484                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 485                 mmiowb();
 486                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 487                 mmiowb();
 488                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 489                 mmiowb();
 490                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 491                 mmiowb();
 492                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 493         }
 494 }
 495
 496 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 497 {
 498         b43_time_lock(dev);
 499         b43_tsf_write_locked(dev, tsf);
 500         b43_time_unlock(dev);
 501 }
 502
 503 static
 504 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 505 {
 506         static const u8 zero_addr[ETH_ALEN] = { 0 };
 507         u16 data;
 508
 509         if (!mac)
 510                 mac = zero_addr;
 511
 512         offset |= 0x0020;
 513         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 514
 515         data = mac[0];
 516         data |= mac[1] << 8;
 517         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 518         data = mac[2];
 519         data |= mac[3] << 8;
 520         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 521         data = mac[4];
 522         data |= mac[5] << 8;
 523         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 524 }
 525
 526 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 527 {
 528         const u8 *mac;
 529         const u8 *bssid;
 530         u8 mac_bssid[ETH_ALEN * 2];
 531         int i;
 532         u32 tmp;
 533
 534         bssid = dev->wl->bssid;
 535         mac = dev->wl->mac_addr;
 536
 537         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 538
 539         memcpy(mac_bssid, mac, ETH_ALEN);
 540         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 541
 542         /* Write our MAC address and BSSID to template ram */
 543         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 544                 tmp = (u32) (mac_bssid[i + 0]);
 545                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 546                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 547                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 548                 b43_ram_write(dev, 0x20 + i, tmp);
 549         }
 550 }
 551
 552 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 553 {
 554         b43_write_mac_bssid_templates(dev);
 555         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 556 }
 557
 558 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 559 {
 560         /* slot_time is in usec. */
 561         if (dev->phy.type != B43_PHYTYPE_G)
 562                 return;
 563         b43_write16(dev, 0x684, 510 + slot_time);
 564         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 565 }
 566
 567 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 568 {
 569         b43_set_slot_time(dev, 9);
 570         dev->short_slot = 1;
 571 }
 572
 573 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 574 {
 575         b43_set_slot_time(dev, 20);
 576         dev->short_slot = 0;
 577 }
 578
 579 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 580  * Returns the _previously_ enabled IRQ mask.
 581  */
 582 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 583 {
 584         u32 old_mask;
 585
 586         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 587         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 588
 589         return old_mask;
 590 }
 591
 592 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 593  * Returns the _previously_ enabled IRQ mask.
 594  */
 595 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 596 {
 597         u32 old_mask;
 598
 599         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 600         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 601
 602         return old_mask;
 603 }
 604
 605 /* Synchronize IRQ top- and bottom-half.
 606  * IRQs must be masked before calling this.
 607  * This must not be called with the irq_lock held.
 608  */
 609 static void b43_synchronize_irq(struct b43_wldev *dev)
 610 {
 611         synchronize_irq(dev->dev->irq);
 612         tasklet_kill(&dev->isr_tasklet);
 613 }
 614
 615 /* DummyTransmission function, as documented on
 616  * http://bcm-specs.sipsolutions.net/DummyTransmission
 617  */
 618 void b43_dummy_transmission(struct b43_wldev *dev)
 619 {
 620         struct b43_phy *phy = &dev->phy;
 621         unsigned int i, max_loop;
 622         u16 value;
 623         u32 buffer[5] = {
 624                 0x00000000,
 625                 0x00D40000,
 626                 0x00000000,
 627                 0x01000000,
 628                 0x00000000,
 629         };
 630
 631         switch (phy->type) {
 632         case B43_PHYTYPE_A:
 633                 max_loop = 0x1E;
 634                 buffer[0] = 0x000201CC;
 635                 break;
 636         case B43_PHYTYPE_B:
 637         case B43_PHYTYPE_G:
 638                 max_loop = 0xFA;
 639                 buffer[0] = 0x000B846E;
 640                 break;
 641         default:
 642                 B43_WARN_ON(1);
 643                 return;
 644         }
 645
 646         for (i = 0; i < 5; i++)
 647                 b43_ram_write(dev, i * 4, buffer[i]);
 648
 649         /* Commit writes */
 650         b43_read32(dev, B43_MMIO_MACCTL);
 651
 652         b43_write16(dev, 0x0568, 0x0000);
 653         b43_write16(dev, 0x07C0, 0x0000);
 654         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 655         b43_write16(dev, 0x050C, value);
 656         b43_write16(dev, 0x0508, 0x0000);
 657         b43_write16(dev, 0x050A, 0x0000);
 658         b43_write16(dev, 0x054C, 0x0000);
 659         b43_write16(dev, 0x056A, 0x0014);
 660         b43_write16(dev, 0x0568, 0x0826);
 661         b43_write16(dev, 0x0500, 0x0000);
 662         b43_write16(dev, 0x0502, 0x0030);
 663
 664         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 665                 b43_radio_write16(dev, 0x0051, 0x0017);
 666         for (i = 0x00; i < max_loop; i++) {
 667                 value = b43_read16(dev, 0x050E);
 668                 if (value & 0x0080)
 669                         break;
 670                 udelay(10);
 671         }
 672         for (i = 0x00; i < 0x0A; i++) {
 673                 value = b43_read16(dev, 0x050E);
 674                 if (value & 0x0400)
 675                         break;
 676                 udelay(10);
 677         }
 678         for (i = 0x00; i < 0x0A; i++) {
 679                 value = b43_read16(dev, 0x0690);
 680                 if (!(value & 0x0100))
 681                         break;
 682                 udelay(10);
 683         }
 684         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 685                 b43_radio_write16(dev, 0x0051, 0x0037);
 686 }
 687
 688 static void key_write(struct b43_wldev *dev,
 689                       u8 index, u8 algorithm, const u8 * key)
 690 {
 691         unsigned int i;
 692         u32 offset;
 693         u16 value;
 694         u16 kidx;
 695
 696         /* Key index/algo block */
 697         kidx = b43_kidx_to_fw(dev, index);
 698         value = ((kidx << 4) | algorithm);
 699         b43_shm_write16(dev, B43_SHM_SHARED,
 700                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 701
 702         /* Write the key to the Key Table Pointer offset */
 703         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 704         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 705                 value = key[i];
 706                 value |= (u16) (key[i + 1]) << 8;
 707                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 708         }
 709 }
 710
 711 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 712 {
 713         u32 addrtmp[2] = { 0, 0, };
 714         u8 per_sta_keys_start = 8;
 715
 716         if (b43_new_kidx_api(dev))
 717                 per_sta_keys_start = 4;
 718
 719         B43_WARN_ON(index < per_sta_keys_start);
 720         /* We have two default TX keys and possibly two default RX keys.
 721          * Physical mac 0 is mapped to physical key 4 or 8, depending
 722          * on the firmware version.
 723          * So we must adjust the index here.
 724          */
 725         index -= per_sta_keys_start;
 726
 727         if (addr) {
 728                 addrtmp[0] = addr[0];
 729                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 730                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 731                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 732                 addrtmp[1] = addr[4];
 733                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 734         }
 735
 736         if (dev->dev->id.revision >= 5) {
 737                 /* Receive match transmitter address mechanism */
 738                 b43_shm_write32(dev, B43_SHM_RCMTA,
 739                                 (index * 2) + 0, addrtmp[0]);
 740                 b43_shm_write16(dev, B43_SHM_RCMTA,
 741                                 (index * 2) + 1, addrtmp[1]);
 742         } else {
 743                 /* RXE (Receive Engine) and
 744                  * PSM (Programmable State Machine) mechanism
 745                  */
 746                 if (index < 8) {
 747                         /* TODO write to RCM 16, 19, 22 and 25 */
 748                 } else {
 749                         b43_shm_write32(dev, B43_SHM_SHARED,
 750                                         B43_SHM_SH_PSM + (index * 6) + 0,
 751                                         addrtmp[0]);
 752                         b43_shm_write16(dev, B43_SHM_SHARED,
 753                                         B43_SHM_SH_PSM + (index * 6) + 4,
 754                                         addrtmp[1]);
 755                 }
 756         }
 757 }
 758
 759 static void do_key_write(struct b43_wldev *dev,
 760                          u8 index, u8 algorithm,
 761                          const u8 * key, size_t key_len, const u8 * mac_addr)
 762 {
 763         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 764         u8 per_sta_keys_start = 8;
 765
 766         if (b43_new_kidx_api(dev))
 767                 per_sta_keys_start = 4;
 768
 769         B43_WARN_ON(index >= dev->max_nr_keys);
 770         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 771
 772         if (index >= per_sta_keys_start)
 773                 keymac_write(dev, index, NULL); /* First zero out mac. */
 774         if (key)
 775                 memcpy(buf, key, key_len);
 776         key_write(dev, index, algorithm, buf);
 777         if (index >= per_sta_keys_start)
 778                 keymac_write(dev, index, mac_addr);
 779
 780         dev->key[index].algorithm = algorithm;
 781 }
 782
 783 static int b43_key_write(struct b43_wldev *dev,
 784                          int index, u8 algorithm,
 785                          const u8 * key, size_t key_len,
 786                          const u8 * mac_addr,
 787                          struct ieee80211_key_conf *keyconf)
 788 {
 789         int i;
 790         int sta_keys_start;
 791
 792         if (key_len > B43_SEC_KEYSIZE)
 793                 return -EINVAL;
 794         for (i = 0; i < dev->max_nr_keys; i++) {
 795                 /* Check that we don't already have this key. */
 796                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 797         }
 798         if (index < 0) {
 799                 /* Either pairwise key or address is 00:00:00:00:00:00
 800                  * for transmit-only keys. Search the index. */
 801                 if (b43_new_kidx_api(dev))
 802                         sta_keys_start = 4;
 803                 else
 804                         sta_keys_start = 8;
 805                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 806                         if (!dev->key[i].keyconf) {
 807                                 /* found empty */
 808                                 index = i;
 809                                 break;
 810                         }
 811                 }
 812                 if (index < 0) {
 813                         b43err(dev->wl, "Out of hardware key memory\n");
 814                         return -ENOSPC;
 815                 }
 816         } else
 817                 B43_WARN_ON(index > 3);
 818
 819         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 820         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 821                 /* Default RX key */
 822                 B43_WARN_ON(mac_addr);
 823                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 824         }
 825         keyconf->hw_key_idx = index;
 826         dev->key[index].keyconf = keyconf;
 827
 828         return 0;
 829 }
 830
 831 static int b43_key_clear(struct b43_wldev *dev, int index)
 832 {
 833         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 834                 return -EINVAL;
 835         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 836                      NULL, B43_SEC_KEYSIZE, NULL);
 837         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 838                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 839                              NULL, B43_SEC_KEYSIZE, NULL);
 840         }
 841         dev->key[index].keyconf = NULL;
 842
 843         return 0;
 844 }
 845
 846 static void b43_clear_keys(struct b43_wldev *dev)
 847 {
 848         int i;
 849
 850         for (i = 0; i < dev->max_nr_keys; i++)
 851                 b43_key_clear(dev, i);
 852 }
 853
 854 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 855 {
 856         u32 macctl;
 857         u16 ucstat;
 858         bool hwps;
 859         bool awake;
 860         int i;
 861
 862         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 863                     (ps_flags & B43_PS_DISABLED));
 864         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 865
 866         if (ps_flags & B43_PS_ENABLED) {
 867                 hwps = 1;
 868         } else if (ps_flags & B43_PS_DISABLED) {
 869                 hwps = 0;
 870         } else {
 871                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 872                 //      and thus is not an AP and we are associated, set bit 25
 873         }
 874         if (ps_flags & B43_PS_AWAKE) {
 875                 awake = 1;
 876         } else if (ps_flags & B43_PS_ASLEEP) {
 877                 awake = 0;
 878         } else {
 879                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 880                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 881                 //      successful, set bit26
 882         }
 883
 884 /* FIXME: For now we force awake-on and hwps-off */
 885         hwps = 0;
 886         awake = 1;
 887
 888         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 889         if (hwps)
 890                 macctl |= B43_MACCTL_HWPS;
 891         else
 892                 macctl &= ~B43_MACCTL_HWPS;
 893         if (awake)
 894                 macctl |= B43_MACCTL_AWAKE;
 895         else
 896                 macctl &= ~B43_MACCTL_AWAKE;
 897         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 898         /* Commit write */
 899         b43_read32(dev, B43_MMIO_MACCTL);
 900         if (awake && dev->dev->id.revision >= 5) {
 901                 /* Wait for the microcode to wake up. */
 902                 for (i = 0; i < 100; i++) {
 903                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 904                                                 B43_SHM_SH_UCODESTAT);
 905                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 906                                 break;
 907                         udelay(10);
 908                 }
 909         }
 910 }
 911
 912 /* Turn the Analog ON/OFF */
 913 static void b43_switch_analog(struct b43_wldev *dev, int on)
 914 {
 915         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 916 }
 917
 918 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 919 {
 920         u32 tmslow;
 921         u32 macctl;
 922
 923         flags |= B43_TMSLOW_PHYCLKEN;
 924         flags |= B43_TMSLOW_PHYRESET;
 925         ssb_device_enable(dev->dev, flags);
 926         msleep(2);              /* Wait for the PLL to turn on. */
 927
 928         /* Now take the PHY out of Reset again */
 929         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 930         tmslow |= SSB_TMSLOW_FGC;
 931         tmslow &= ~B43_TMSLOW_PHYRESET;
 932         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 933         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 934         msleep(1);
 935         tmslow &= ~SSB_TMSLOW_FGC;
 936         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 937         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 938         msleep(1);
 939
 940         /* Turn Analog ON */
 941         b43_switch_analog(dev, 1);
 942
 943         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 944         macctl &= ~B43_MACCTL_GMODE;
 945         if (flags & B43_TMSLOW_GMODE)
 946                 macctl |= B43_MACCTL_GMODE;
 947         macctl |= B43_MACCTL_IHR_ENABLED;
 948         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 949 }
 950
 951 static void handle_irq_transmit_status(struct b43_wldev *dev)
 952 {
 953         u32 v0, v1;
 954         u16 tmp;
 955         struct b43_txstatus stat;
 956
 957         while (1) {
 958                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 959                 if (!(v0 & 0x00000001))
 960                         break;
 961                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 962
 963                 stat.cookie = (v0 >> 16);
 964                 stat.seq = (v1 & 0x0000FFFF);
 965                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 966                 tmp = (v0 & 0x0000FFFF);
 967                 stat.frame_count = ((tmp & 0xF000) >> 12);
 968                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 969                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 970                 stat.pm_indicated = !!(tmp & 0x0080);
 971                 stat.intermediate = !!(tmp & 0x0040);
 972                 stat.for_ampdu = !!(tmp & 0x0020);
 973                 stat.acked = !!(tmp & 0x0002);
 974
 975                 b43_handle_txstatus(dev, &stat);
 976         }
 977 }
 978
 979 static void drain_txstatus_queue(struct b43_wldev *dev)
 980 {
 981         u32 dummy;
 982
 983         if (dev->dev->id.revision < 5)
 984                 return;
 985         /* Read all entries from the microcode TXstatus FIFO
 986          * and throw them away.
 987          */
 988         while (1) {
 989                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 990                 if (!(dummy & 0x00000001))
 991                         break;
 992                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 993         }
 994 }
 995
 996 static u32 b43_jssi_read(struct b43_wldev *dev)
 997 {
 998         u32 val = 0;
 999
1000         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1001         val <<= 16;
1002         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1003
1004         return val;
1005 }
1006
1007 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1008 {
1009         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1010         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1011 }
1012
1013 static void b43_generate_noise_sample(struct b43_wldev *dev)
1014 {
1015         b43_jssi_write(dev, 0x7F7F7F7F);
1016         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1017                     b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1018                     | (1 << 4));
1019         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1020 }
1021
1022 static void b43_calculate_link_quality(struct b43_wldev *dev)
1023 {
1024         /* Top half of Link Quality calculation. */
1025
1026         if (dev->noisecalc.calculation_running)
1027                 return;
1028         dev->noisecalc.channel_at_start = dev->phy.channel;
1029         dev->noisecalc.calculation_running = 1;
1030         dev->noisecalc.nr_samples = 0;
1031
1032         b43_generate_noise_sample(dev);
1033 }
1034
1035 static void handle_irq_noise(struct b43_wldev *dev)
1036 {
1037         struct b43_phy *phy = &dev->phy;
1038         u16 tmp;
1039         u8 noise[4];
1040         u8 i, j;
1041         s32 average;
1042
1043         /* Bottom half of Link Quality calculation. */
1044
1045         B43_WARN_ON(!dev->noisecalc.calculation_running);
1046         if (dev->noisecalc.channel_at_start != phy->channel)
1047                 goto drop_calculation;
1048         *((u32 *) noise) = cpu_to_le32(b43_jssi_read(dev));
1049         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1050             noise[2] == 0x7F || noise[3] == 0x7F)
1051                 goto generate_new;
1052
1053         /* Get the noise samples. */
1054         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1055         i = dev->noisecalc.nr_samples;
1056         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1057         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1058         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1059         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1060         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1061         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1062         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1063         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1064         dev->noisecalc.nr_samples++;
1065         if (dev->noisecalc.nr_samples == 8) {
1066                 /* Calculate the Link Quality by the noise samples. */
1067                 average = 0;
1068                 for (i = 0; i < 8; i++) {
1069                         for (j = 0; j < 4; j++)
1070                                 average += dev->noisecalc.samples[i][j];
1071                 }
1072                 average /= (8 * 4);
1073                 average *= 125;
1074                 average += 64;
1075                 average /= 128;
1076                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1077                 tmp = (tmp / 128) & 0x1F;
1078                 if (tmp >= 8)
1079                         average += 2;
1080                 else
1081                         average -= 25;
1082                 if (tmp == 8)
1083                         average -= 72;
1084                 else
1085                         average -= 48;
1086
1087                 dev->stats.link_noise = average;
1088               drop_calculation:
1089                 dev->noisecalc.calculation_running = 0;
1090                 return;
1091         }
1092       generate_new:
1093         b43_generate_noise_sample(dev);
1094 }
1095
1096 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1097 {
1098         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1099                 ///TODO: PS TBTT
1100         } else {
1101                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1102                         b43_power_saving_ctl_bits(dev, 0);
1103         }
1104         dev->reg124_set_0x4 = 0;
1105         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1106                 dev->reg124_set_0x4 = 1;
1107 }
1108
1109 static void handle_irq_atim_end(struct b43_wldev *dev)
1110 {
1111         if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1112                 return;
1113         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1114                     b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1115                     | 0x4);
1116 }
1117
1118 static void handle_irq_pmq(struct b43_wldev *dev)
1119 {
1120         u32 tmp;
1121
1122         //TODO: AP mode.
1123
1124         while (1) {
1125                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1126                 if (!(tmp & 0x00000008))
1127                         break;
1128         }
1129         /* 16bit write is odd, but correct. */
1130         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1131 }
1132
1133 static void b43_write_template_common(struct b43_wldev *dev,
1134                                       const u8 * data, u16 size,
1135                                       u16 ram_offset,
1136                                       u16 shm_size_offset, u8 rate)
1137 {
1138         u32 i, tmp;
1139         struct b43_plcp_hdr4 plcp;
1140
1141         plcp.data = 0;
1142         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1143         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1144         ram_offset += sizeof(u32);
1145         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1146          * So leave the first two bytes of the next write blank.
1147          */
1148         tmp = (u32) (data[0]) << 16;
1149         tmp |= (u32) (data[1]) << 24;
1150         b43_ram_write(dev, ram_offset, tmp);
1151         ram_offset += sizeof(u32);
1152         for (i = 2; i < size; i += sizeof(u32)) {
1153                 tmp = (u32) (data[i + 0]);
1154                 if (i + 1 < size)
1155                         tmp |= (u32) (data[i + 1]) << 8;
1156                 if (i + 2 < size)
1157                         tmp |= (u32) (data[i + 2]) << 16;
1158                 if (i + 3 < size)
1159                         tmp |= (u32) (data[i + 3]) << 24;
1160                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1161         }
1162         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1163                         size + sizeof(struct b43_plcp_hdr6));
1164 }
1165
1166 static void b43_write_beacon_template(struct b43_wldev *dev,
1167                                       u16 ram_offset,
1168                                       u16 shm_size_offset, u8 rate)
1169 {
1170         int len;
1171         const u8 *data;
1172
1173         B43_WARN_ON(!dev->cached_beacon);
1174         len = min((size_t) dev->cached_beacon->len,
1175                   0x200 - sizeof(struct b43_plcp_hdr6));
1176         data = (const u8 *)(dev->cached_beacon->data);
1177         b43_write_template_common(dev, data,
1178                                   len, ram_offset, shm_size_offset, rate);
1179 }
1180
1181 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1182                                       u16 shm_offset, u16 size, u8 rate)
1183 {
1184         struct b43_plcp_hdr4 plcp;
1185         u32 tmp;
1186         __le16 dur;
1187
1188         plcp.data = 0;
1189         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1190         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1191                                                dev->wl->if_id, size,
1192                                                B43_RATE_TO_BASE100KBPS(rate));
1193         /* Write PLCP in two parts and timing for packet transfer */
1194         tmp = le32_to_cpu(plcp.data);
1195         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1196         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1197         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1198 }
1199
1200 /* Instead of using custom probe response template, this function
1201  * just patches custom beacon template by:
1202  * 1) Changing packet type
1203  * 2) Patching duration field
1204  * 3) Stripping TIM
1205  */
1206 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1207                                    u16 * dest_size, u8 rate)
1208 {
1209         const u8 *src_data;
1210         u8 *dest_data;
1211         u16 src_size, elem_size, src_pos, dest_pos;
1212         __le16 dur;
1213         struct ieee80211_hdr *hdr;
1214
1215         B43_WARN_ON(!dev->cached_beacon);
1216         src_size = dev->cached_beacon->len;
1217         src_data = (const u8 *)dev->cached_beacon->data;
1218
1219         if (unlikely(src_size < 0x24)) {
1220                 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1221                 return NULL;
1222         }
1223
1224         dest_data = kmalloc(src_size, GFP_ATOMIC);
1225         if (unlikely(!dest_data))
1226                 return NULL;
1227
1228         /* 0x24 is offset of first variable-len Information-Element
1229          * in beacon frame.
1230          */
1231         memcpy(dest_data, src_data, 0x24);
1232         src_pos = dest_pos = 0x24;
1233         for (; src_pos < src_size - 2; src_pos += elem_size) {
1234                 elem_size = src_data[src_pos + 1] + 2;
1235                 if (src_data[src_pos] != 0x05) {        /* TIM */
1236                         memcpy(dest_data + dest_pos, src_data + src_pos,
1237                                elem_size);
1238                         dest_pos += elem_size;
1239                 }
1240         }
1241         *dest_size = dest_pos;
1242         hdr = (struct ieee80211_hdr *)dest_data;
1243
1244         /* Set the frame control. */
1245         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1246                                          IEEE80211_STYPE_PROBE_RESP);
1247         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1248                                                dev->wl->if_id, *dest_size,
1249                                                B43_RATE_TO_BASE100KBPS(rate));
1250         hdr->duration_id = dur;
1251
1252         return dest_data;
1253 }
1254
1255 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1256                                           u16 ram_offset,
1257                                           u16 shm_size_offset, u8 rate)
1258 {
1259         u8 *probe_resp_data;
1260         u16 size;
1261
1262         B43_WARN_ON(!dev->cached_beacon);
1263         size = dev->cached_beacon->len;
1264         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1265         if (unlikely(!probe_resp_data))
1266                 return;
1267
1268         /* Looks like PLCP headers plus packet timings are stored for
1269          * all possible basic rates
1270          */
1271         b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1272         b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1273         b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1274         b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1275
1276         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1277         b43_write_template_common(dev, probe_resp_data,
1278                                   size, ram_offset, shm_size_offset, rate);
1279         kfree(probe_resp_data);
1280 }
1281
1282 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1283                                      struct sk_buff *beacon)
1284 {
1285         if (dev->cached_beacon)
1286                 kfree_skb(dev->cached_beacon);
1287         dev->cached_beacon = beacon;
1288
1289         return 0;
1290 }
1291
1292 static void b43_update_templates(struct b43_wldev *dev)
1293 {
1294         u32 status;
1295
1296         B43_WARN_ON(!dev->cached_beacon);
1297
1298         b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1299         b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1300         b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1301
1302         status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1303         status |= 0x03;
1304         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1305 }
1306
1307 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1308 {
1309         int err;
1310
1311         err = b43_refresh_cached_beacon(dev, beacon);
1312         if (unlikely(err))
1313                 return;
1314         b43_update_templates(dev);
1315 }
1316
1317 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1318 {
1319         u32 tmp;
1320         u16 i, len;
1321
1322         len = min((u16) ssid_len, (u16) 0x100);
1323         for (i = 0; i < len; i += sizeof(u32)) {
1324                 tmp = (u32) (ssid[i + 0]);
1325                 if (i + 1 < len)
1326                         tmp |= (u32) (ssid[i + 1]) << 8;
1327                 if (i + 2 < len)
1328                         tmp |= (u32) (ssid[i + 2]) << 16;
1329                 if (i + 3 < len)
1330                         tmp |= (u32) (ssid[i + 3]) << 24;
1331                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1332         }
1333         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1334 }
1335
1336 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1337 {
1338         b43_time_lock(dev);
1339         if (dev->dev->id.revision >= 3) {
1340                 b43_write32(dev, 0x188, (beacon_int << 16));
1341         } else {
1342                 b43_write16(dev, 0x606, (beacon_int >> 6));
1343                 b43_write16(dev, 0x610, beacon_int);
1344         }
1345         b43_time_unlock(dev);
1346 }
1347
1348 static void handle_irq_beacon(struct b43_wldev *dev)
1349 {
1350         u32 status;
1351
1352         if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1353                 return;
1354
1355         dev->irq_savedstate &= ~B43_IRQ_BEACON;
1356         status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1357
1358         if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1359                 /* ACK beacon IRQ. */
1360                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1361                 dev->irq_savedstate |= B43_IRQ_BEACON;
1362                 if (dev->cached_beacon)
1363                         kfree_skb(dev->cached_beacon);
1364                 dev->cached_beacon = NULL;
1365                 return;
1366         }
1367         if (!(status & 0x1)) {
1368                 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1369                 status |= 0x1;
1370                 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1371         }
1372         if (!(status & 0x2)) {
1373                 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1374                 status |= 0x2;
1375                 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1376         }
1377 }
1378
1379 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1380 {
1381         //TODO
1382 }
1383
1384 /* Interrupt handler bottom-half */
1385 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1386 {
1387         u32 reason;
1388         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1389         u32 merged_dma_reason = 0;
1390         int i;
1391         unsigned long flags;
1392
1393         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1394
1395         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1396
1397         reason = dev->irq_reason;
1398         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1399                 dma_reason[i] = dev->dma_reason[i];
1400                 merged_dma_reason |= dma_reason[i];
1401         }
1402
1403         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1404                 b43err(dev->wl, "MAC transmission error\n");
1405
1406         if (unlikely(reason & B43_IRQ_PHY_TXERR))
1407                 b43err(dev->wl, "PHY transmission error\n");
1408
1409         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1410                                           B43_DMAIRQ_NONFATALMASK))) {
1411                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1412                         b43err(dev->wl, "Fatal DMA error: "
1413                                "0x%08X, 0x%08X, 0x%08X, "
1414                                "0x%08X, 0x%08X, 0x%08X\n",
1415                                dma_reason[0], dma_reason[1],
1416                                dma_reason[2], dma_reason[3],
1417                                dma_reason[4], dma_reason[5]);
1418                         b43_controller_restart(dev, "DMA error");
1419                         mmiowb();
1420                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1421                         return;
1422                 }
1423                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1424                         b43err(dev->wl, "DMA error: "
1425                                "0x%08X, 0x%08X, 0x%08X, "
1426                                "0x%08X, 0x%08X, 0x%08X\n",
1427                                dma_reason[0], dma_reason[1],
1428                                dma_reason[2], dma_reason[3],
1429                                dma_reason[4], dma_reason[5]);
1430                 }
1431         }
1432
1433         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1434                 handle_irq_ucode_debug(dev);
1435         if (reason & B43_IRQ_TBTT_INDI)
1436                 handle_irq_tbtt_indication(dev);
1437         if (reason & B43_IRQ_ATIM_END)
1438                 handle_irq_atim_end(dev);
1439         if (reason & B43_IRQ_BEACON)
1440                 handle_irq_beacon(dev);
1441         if (reason & B43_IRQ_PMQ)
1442                 handle_irq_pmq(dev);
1443         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1444                 ;/* TODO */
1445         if (reason & B43_IRQ_NOISESAMPLE_OK)
1446                 handle_irq_noise(dev);
1447
1448         /* Check the DMA reason registers for received data. */
1449         if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1450                 if (b43_using_pio(dev))
1451                         b43_pio_rx(dev->pio.queue0);
1452                 else
1453                         b43_dma_rx(dev->dma.rx_ring0);
1454         }
1455         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1456         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1457         if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1458                 if (b43_using_pio(dev))
1459                         b43_pio_rx(dev->pio.queue3);
1460                 else
1461                         b43_dma_rx(dev->dma.rx_ring3);
1462         }
1463         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1464         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1465
1466         if (reason & B43_IRQ_TX_OK)
1467                 handle_irq_transmit_status(dev);
1468
1469         b43_interrupt_enable(dev, dev->irq_savedstate);
1470         mmiowb();
1471         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1472 }
1473
1474 static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1475 {
1476         u16 rxctl;
1477
1478         rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1479         if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1480                 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1481         else
1482                 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1483 }
1484
1485 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1486 {
1487         if (b43_using_pio(dev) &&
1488             (dev->dev->id.revision < 3) &&
1489             (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1490                 /* Apply a PIO specific workaround to the dma_reasons */
1491                 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1492                 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1493                 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1494                 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1495         }
1496
1497         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1498
1499         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1500         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1501         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1502         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1503         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1504         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1505 }
1506
1507 /* Interrupt handler top-half */
1508 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1509 {
1510         irqreturn_t ret = IRQ_NONE;
1511         struct b43_wldev *dev = dev_id;
1512         u32 reason;
1513
1514         if (!dev)
1515                 return IRQ_NONE;
1516
1517         spin_lock(&dev->wl->irq_lock);
1518
1519         if (b43_status(dev) < B43_STAT_STARTED)
1520                 goto out;
1521         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1522         if (reason == 0xffffffff)       /* shared IRQ */
1523                 goto out;
1524         ret = IRQ_HANDLED;
1525         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1526         if (!reason)
1527                 goto out;
1528
1529         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1530             & 0x0001DC00;
1531         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1532             & 0x0000DC00;
1533         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1534             & 0x0000DC00;
1535         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1536             & 0x0001DC00;
1537         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1538             & 0x0000DC00;
1539         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1540             & 0x0000DC00;
1541
1542         b43_interrupt_ack(dev, reason);
1543         /* disable all IRQs. They are enabled again in the bottom half. */
1544         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1545         /* save the reason code and call our bottom half. */
1546         dev->irq_reason = reason;
1547         tasklet_schedule(&dev->isr_tasklet);
1548       out:
1549         mmiowb();
1550         spin_unlock(&dev->wl->irq_lock);
1551
1552         return ret;
1553 }
1554
1555 static void b43_release_firmware(struct b43_wldev *dev)
1556 {
1557         release_firmware(dev->fw.ucode);
1558         dev->fw.ucode = NULL;
1559         release_firmware(dev->fw.pcm);
1560         dev->fw.pcm = NULL;
1561         release_firmware(dev->fw.initvals);
1562         dev->fw.initvals = NULL;
1563         release_firmware(dev->fw.initvals_band);
1564         dev->fw.initvals_band = NULL;
1565 }
1566
1567 static void b43_print_fw_helptext(struct b43_wl *wl)
1568 {
1569         b43err(wl, "You must go to "
1570                "http://linuxwireless.org/en/users/Drivers/bcm43xx#devicefirmware "
1571                "and download the correct firmware (version 4).\n");
1572 }
1573
1574 static int do_request_fw(struct b43_wldev *dev,
1575                          const char *name,
1576                          const struct firmware **fw)
1577 {
1578         const size_t plen = sizeof(modparam_fwpostfix) + 32;
1579         char path[plen];
1580         struct b43_fw_header *hdr;
1581         u32 size;
1582         int err;
1583
1584         if (!name)
1585                 return 0;
1586
1587         snprintf(path, ARRAY_SIZE(path),
1588                  "b43%s/%s.fw",
1589                  modparam_fwpostfix, name);
1590         err = request_firmware(fw, path, dev->dev->dev);
1591         if (err) {
1592                 b43err(dev->wl, "Firmware file \"%s\" not found "
1593                        "or load failed.\n", path);
1594                 return err;
1595         }
1596         if ((*fw)->size < sizeof(struct b43_fw_header))
1597                 goto err_format;
1598         hdr = (struct b43_fw_header *)((*fw)->data);
1599         switch (hdr->type) {
1600         case B43_FW_TYPE_UCODE:
1601         case B43_FW_TYPE_PCM:
1602                 size = be32_to_cpu(hdr->size);
1603                 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1604                         goto err_format;
1605                 /* fallthrough */
1606         case B43_FW_TYPE_IV:
1607                 if (hdr->ver != 1)
1608                         goto err_format;
1609                 break;
1610         default:
1611                 goto err_format;
1612         }
1613
1614         return err;
1615
1616 err_format:
1617         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1618         return -EPROTO;
1619 }
1620
1621 static int b43_request_firmware(struct b43_wldev *dev)
1622 {
1623         struct b43_firmware *fw = &dev->fw;
1624         const u8 rev = dev->dev->id.revision;
1625         const char *filename;
1626         u32 tmshigh;
1627         int err;
1628
1629         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1630         if (!fw->ucode) {
1631                 if ((rev >= 5) && (rev <= 10))
1632                         filename = "ucode5";
1633                 else if ((rev >= 11) && (rev <= 12))
1634                         filename = "ucode11";
1635                 else if (rev >= 13)
1636                         filename = "ucode13";
1637                 else
1638                         goto err_no_ucode;
1639                 err = do_request_fw(dev, filename, &fw->ucode);
1640                 if (err)
1641                         goto err_load;
1642         }
1643         if (!fw->pcm) {
1644                 if ((rev >= 5) && (rev <= 10))
1645                         filename = "pcm5";
1646                 else if (rev >= 11)
1647                         filename = NULL;
1648                 else
1649                         goto err_no_pcm;
1650                 err = do_request_fw(dev, filename, &fw->pcm);
1651                 if (err)
1652                         goto err_load;
1653         }
1654         if (!fw->initvals) {
1655                 switch (dev->phy.type) {
1656                 case B43_PHYTYPE_A:
1657                         if ((rev >= 5) && (rev <= 10)) {
1658                                 if (tmshigh & B43_TMSHIGH_GPHY)
1659                                         filename = "a0g1initvals5";
1660                                 else
1661                                         filename = "a0g0initvals5";
1662                         } else
1663                                 goto err_no_initvals;
1664                         break;
1665                 case B43_PHYTYPE_G:
1666                         if ((rev >= 5) && (rev <= 10))
1667                                 filename = "b0g0initvals5";
1668                         else if (rev >= 13)
1669                                 filename = "lp0initvals13";
1670                         else
1671                                 goto err_no_initvals;
1672                         break;
1673                 default:
1674                         goto err_no_initvals;
1675                 }
1676                 err = do_request_fw(dev, filename, &fw->initvals);
1677                 if (err)
1678                         goto err_load;
1679         }
1680         if (!fw->initvals_band) {
1681                 switch (dev->phy.type) {
1682                 case B43_PHYTYPE_A:
1683                         if ((rev >= 5) && (rev <= 10)) {
1684                                 if (tmshigh & B43_TMSHIGH_GPHY)
1685                                         filename = "a0g1bsinitvals5";
1686                                 else
1687                                         filename = "a0g0bsinitvals5";
1688                         } else if (rev >= 11)
1689                                 filename = NULL;
1690                         else
1691                                 goto err_no_initvals;
1692                         break;
1693                 case B43_PHYTYPE_G:
1694                         if ((rev >= 5) && (rev <= 10))
1695                                 filename = "b0g0bsinitvals5";
1696                         else if (rev >= 11)
1697                                 filename = NULL;
1698                         else
1699                                 goto err_no_initvals;
1700                         break;
1701                 default:
1702                         goto err_no_initvals;
1703                 }
1704                 err = do_request_fw(dev, filename, &fw->initvals_band);
1705                 if (err)
1706                         goto err_load;
1707         }
1708
1709         return 0;
1710
1711 err_load:
1712         b43_print_fw_helptext(dev->wl);
1713         goto error;
1714
1715 err_no_ucode:
1716         err = -ENODEV;
1717         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1718         goto error;
1719
1720 err_no_pcm:
1721         err = -ENODEV;
1722         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1723         goto error;
1724
1725 err_no_initvals:
1726         err = -ENODEV;
1727         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1728                "core rev %u\n", dev->phy.type, rev);
1729         goto error;
1730
1731 error:
1732         b43_release_firmware(dev);
1733         return err;
1734 }
1735
1736 static int b43_upload_microcode(struct b43_wldev *dev)
1737 {
1738         const size_t hdr_len = sizeof(struct b43_fw_header);
1739         const __be32 *data;
1740         unsigned int i, len;
1741         u16 fwrev, fwpatch, fwdate, fwtime;
1742         u32 tmp;
1743         int err = 0;
1744
1745         /* Upload Microcode. */
1746         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1747         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1748         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1749         for (i = 0; i < len; i++) {
1750                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1751                 udelay(10);
1752         }
1753
1754         if (dev->fw.pcm) {
1755                 /* Upload PCM data. */
1756                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1757                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1758                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1759                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1760                 /* No need for autoinc bit in SHM_HW */
1761                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1762                 for (i = 0; i < len; i++) {
1763                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1764                         udelay(10);
1765                 }
1766         }
1767
1768         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1769         b43_write32(dev, B43_MMIO_MACCTL,
1770                     B43_MACCTL_PSM_RUN |
1771                     B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1772
1773         /* Wait for the microcode to load and respond */
1774         i = 0;
1775         while (1) {
1776                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1777                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1778                         break;
1779                 i++;
1780                 if (i >= 50) {
1781                         b43err(dev->wl, "Microcode not responding\n");
1782                         b43_print_fw_helptext(dev->wl);
1783                         err = -ENODEV;
1784                         goto out;
1785                 }
1786                 udelay(10);
1787         }
1788         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1789
1790         /* Get and check the revisions. */
1791         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1792         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1793         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1794         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1795
1796         if (fwrev <= 0x128) {
1797                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1798                        "binary drivers older than version 4.x is unsupported. "
1799                        "You must upgrade your firmware files.\n");
1800                 b43_print_fw_helptext(dev->wl);
1801                 b43_write32(dev, B43_MMIO_MACCTL, 0);
1802                 err = -EOPNOTSUPP;
1803                 goto out;
1804         }
1805         b43dbg(dev->wl, "Loading firmware version %u.%u "
1806                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1807                fwrev, fwpatch,
1808                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1809                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1810
1811         dev->fw.rev = fwrev;
1812         dev->fw.patch = fwpatch;
1813
1814       out:
1815         return err;
1816 }
1817
1818 static int b43_write_initvals(struct b43_wldev *dev,
1819                               const struct b43_iv *ivals,
1820                               size_t count,
1821                               size_t array_size)
1822 {
1823         const struct b43_iv *iv;
1824         u16 offset;
1825         size_t i;
1826         bool bit32;
1827
1828         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1829         iv = ivals;
1830         for (i = 0; i < count; i++) {
1831                 if (array_size < sizeof(iv->offset_size))
1832                         goto err_format;
1833                 array_size -= sizeof(iv->offset_size);
1834                 offset = be16_to_cpu(iv->offset_size);
1835                 bit32 = !!(offset & B43_IV_32BIT);
1836                 offset &= B43_IV_OFFSET_MASK;
1837                 if (offset >= 0x1000)
1838                         goto err_format;
1839                 if (bit32) {
1840                         u32 value;
1841
1842                         if (array_size < sizeof(iv->data.d32))
1843                                 goto err_format;
1844                         array_size -= sizeof(iv->data.d32);
1845
1846                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1847                         b43_write32(dev, offset, value);
1848
1849                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1850                                                         sizeof(__be16) +
1851                                                         sizeof(__be32));
1852                 } else {
1853                         u16 value;
1854
1855                         if (array_size < sizeof(iv->data.d16))
1856                                 goto err_format;
1857                         array_size -= sizeof(iv->data.d16);
1858
1859                         value = be16_to_cpu(iv->data.d16);
1860                         b43_write16(dev, offset, value);
1861
1862                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1863                                                         sizeof(__be16) +
1864                                                         sizeof(__be16));
1865                 }
1866         }
1867         if (array_size)
1868                 goto err_format;
1869
1870         return 0;
1871
1872 err_format:
1873         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1874         b43_print_fw_helptext(dev->wl);
1875
1876         return -EPROTO;
1877 }
1878
1879 static int b43_upload_initvals(struct b43_wldev *dev)
1880 {
1881         const size_t hdr_len = sizeof(struct b43_fw_header);
1882         const struct b43_fw_header *hdr;
1883         struct b43_firmware *fw = &dev->fw;
1884         const struct b43_iv *ivals;
1885         size_t count;
1886         int err;
1887
1888         hdr = (const struct b43_fw_header *)(fw->initvals->data);
1889         ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1890         count = be32_to_cpu(hdr->size);
1891         err = b43_write_initvals(dev, ivals, count,
1892                                  fw->initvals->size - hdr_len);
1893         if (err)
1894                 goto out;
1895         if (fw->initvals_band) {
1896                 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1897                 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1898                 count = be32_to_cpu(hdr->size);
1899                 err = b43_write_initvals(dev, ivals, count,
1900                                          fw->initvals_band->size - hdr_len);
1901                 if (err)
1902                         goto out;
1903         }
1904 out:
1905
1906         return err;
1907 }
1908
1909 /* Initialize the GPIOs
1910  * http://bcm-specs.sipsolutions.net/GPIO
1911  */
1912 static int b43_gpio_init(struct b43_wldev *dev)
1913 {
1914         struct ssb_bus *bus = dev->dev->bus;
1915         struct ssb_device *gpiodev, *pcidev = NULL;
1916         u32 mask, set;
1917
1918         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1919                     & ~B43_MACCTL_GPOUTSMSK);
1920
1921         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1922                     | 0x000F);
1923
1924         mask = 0x0000001F;
1925         set = 0x0000000F;
1926         if (dev->dev->bus->chip_id == 0x4301) {
1927                 mask |= 0x0060;
1928                 set |= 0x0060;
1929         }
1930         if (0 /* FIXME: conditional unknown */ ) {
1931                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1932                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1933                             | 0x0100);
1934                 mask |= 0x0180;
1935                 set |= 0x0180;
1936         }
1937         if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL) {
1938                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1939                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1940                             | 0x0200);
1941                 mask |= 0x0200;
1942                 set |= 0x0200;
1943         }
1944         if (dev->dev->id.revision >= 2)
1945                 mask |= 0x0010; /* FIXME: This is redundant. */
1946
1947 #ifdef CONFIG_SSB_DRIVER_PCICORE
1948         pcidev = bus->pcicore.dev;
1949 #endif
1950         gpiodev = bus->chipco.dev ? : pcidev;
1951         if (!gpiodev)
1952                 return 0;
1953         ssb_write32(gpiodev, B43_GPIO_CONTROL,
1954                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1955                      & mask) | set);
1956
1957         return 0;
1958 }
1959
1960 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1961 static void b43_gpio_cleanup(struct b43_wldev *dev)
1962 {
1963         struct ssb_bus *bus = dev->dev->bus;
1964         struct ssb_device *gpiodev, *pcidev = NULL;
1965
1966 #ifdef CONFIG_SSB_DRIVER_PCICORE
1967         pcidev = bus->pcicore.dev;
1968 #endif
1969         gpiodev = bus->chipco.dev ? : pcidev;
1970         if (!gpiodev)
1971                 return;
1972         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1973 }
1974
1975 /* http://bcm-specs.sipsolutions.net/EnableMac */
1976 void b43_mac_enable(struct b43_wldev *dev)
1977 {
1978         dev->mac_suspended--;
1979         B43_WARN_ON(dev->mac_suspended < 0);
1980         B43_WARN_ON(irqs_disabled());
1981         if (dev->mac_suspended == 0) {
1982                 b43_write32(dev, B43_MMIO_MACCTL,
1983                             b43_read32(dev, B43_MMIO_MACCTL)
1984                             | B43_MACCTL_ENABLED);
1985                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1986                             B43_IRQ_MAC_SUSPENDED);
1987                 /* Commit writes */
1988                 b43_read32(dev, B43_MMIO_MACCTL);
1989                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1990                 b43_power_saving_ctl_bits(dev, 0);
1991
1992                 /* Re-enable IRQs. */
1993                 spin_lock_irq(&dev->wl->irq_lock);
1994                 b43_interrupt_enable(dev, dev->irq_savedstate);
1995                 spin_unlock_irq(&dev->wl->irq_lock);
1996         }
1997 }
1998
1999 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2000 void b43_mac_suspend(struct b43_wldev *dev)
2001 {
2002         int i;
2003         u32 tmp;
2004
2005         might_sleep();
2006         B43_WARN_ON(irqs_disabled());
2007         B43_WARN_ON(dev->mac_suspended < 0);
2008
2009         if (dev->mac_suspended == 0) {
2010                 /* Mask IRQs before suspending MAC. Otherwise
2011                  * the MAC stays busy and won't suspend. */
2012                 spin_lock_irq(&dev->wl->irq_lock);
2013                 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2014                 spin_unlock_irq(&dev->wl->irq_lock);
2015                 b43_synchronize_irq(dev);
2016                 dev->irq_savedstate = tmp;
2017
2018                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2019                 b43_write32(dev, B43_MMIO_MACCTL,
2020                             b43_read32(dev, B43_MMIO_MACCTL)
2021                             & ~B43_MACCTL_ENABLED);
2022                 /* force pci to flush the write */
2023                 b43_read32(dev, B43_MMIO_MACCTL);
2024                 for (i = 40; i; i--) {
2025                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2026                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2027                                 goto out;
2028                         msleep(1);
2029                 }
2030                 b43err(dev->wl, "MAC suspend failed\n");
2031         }
2032 out:
2033         dev->mac_suspended++;
2034 }
2035
2036 static void b43_adjust_opmode(struct b43_wldev *dev)
2037 {
2038         struct b43_wl *wl = dev->wl;
2039         u32 ctl;
2040         u16 cfp_pretbtt;
2041
2042         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2043         /* Reset status to STA infrastructure mode. */
2044         ctl &= ~B43_MACCTL_AP;
2045         ctl &= ~B43_MACCTL_KEEP_CTL;
2046         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2047         ctl &= ~B43_MACCTL_KEEP_BAD;
2048         ctl &= ~B43_MACCTL_PROMISC;
2049         ctl &= ~B43_MACCTL_BEACPROMISC;
2050         ctl |= B43_MACCTL_INFRA;
2051
2052         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2053                 ctl |= B43_MACCTL_AP;
2054         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2055                 ctl &= ~B43_MACCTL_INFRA;
2056
2057         if (wl->filter_flags & FIF_CONTROL)
2058                 ctl |= B43_MACCTL_KEEP_CTL;
2059         if (wl->filter_flags & FIF_FCSFAIL)
2060                 ctl |= B43_MACCTL_KEEP_BAD;
2061         if (wl->filter_flags & FIF_PLCPFAIL)
2062                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2063         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2064                 ctl |= B43_MACCTL_PROMISC;
2065         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2066                 ctl |= B43_MACCTL_BEACPROMISC;
2067
2068         /* Workaround: On old hardware the HW-MAC-address-filter
2069          * doesn't work properly, so always run promisc in filter
2070          * it in software. */
2071         if (dev->dev->id.revision <= 4)
2072                 ctl |= B43_MACCTL_PROMISC;
2073
2074         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2075
2076         cfp_pretbtt = 2;
2077         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2078                 if (dev->dev->bus->chip_id == 0x4306 &&
2079                     dev->dev->bus->chip_rev == 3)
2080                         cfp_pretbtt = 100;
2081                 else
2082                         cfp_pretbtt = 50;
2083         }
2084         b43_write16(dev, 0x612, cfp_pretbtt);
2085 }
2086
2087 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2088 {
2089         u16 offset;
2090
2091         if (is_ofdm) {
2092                 offset = 0x480;
2093                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2094         } else {
2095                 offset = 0x4C0;
2096                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2097         }
2098         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2099                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2100 }
2101
2102 static void b43_rate_memory_init(struct b43_wldev *dev)
2103 {
2104         switch (dev->phy.type) {
2105         case B43_PHYTYPE_A:
2106         case B43_PHYTYPE_G:
2107                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2108                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2109                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2110                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2111                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2112                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2113                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2114                 if (dev->phy.type == B43_PHYTYPE_A)
2115                         break;
2116                 /* fallthrough */
2117         case B43_PHYTYPE_B:
2118                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2119                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2120                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2121                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2122                 break;
2123         default:
2124                 B43_WARN_ON(1);
2125         }
2126 }
2127
2128 /* Set the TX-Antenna for management frames sent by firmware. */
2129 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2130 {
2131         u16 ant = 0;
2132         u16 tmp;
2133
2134         switch (antenna) {
2135         case B43_ANTENNA0:
2136                 ant |= B43_TX4_PHY_ANT0;
2137                 break;
2138         case B43_ANTENNA1:
2139                 ant |= B43_TX4_PHY_ANT1;
2140                 break;
2141         case B43_ANTENNA_AUTO:
2142                 ant |= B43_TX4_PHY_ANTLAST;
2143                 break;
2144         default:
2145                 B43_WARN_ON(1);
2146         }
2147
2148         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2149
2150         /* For Beacons */
2151         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2152         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2153         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2154         /* For ACK/CTS */
2155         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2156         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2157         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2158         /* For Probe Resposes */
2159         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2160         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2161         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2162 }
2163
2164 /* This is the opposite of b43_chip_init() */
2165 static void b43_chip_exit(struct b43_wldev *dev)
2166 {
2167         b43_radio_turn_off(dev, 1);
2168         b43_leds_exit(dev);
2169         b43_gpio_cleanup(dev);
2170         /* firmware is released later */
2171 }
2172
2173 /* Initialize the chip
2174  * http://bcm-specs.sipsolutions.net/ChipInit
2175  */
2176 static int b43_chip_init(struct b43_wldev *dev)
2177 {
2178         struct b43_phy *phy = &dev->phy;
2179         int err, tmp;
2180         u32 value32;
2181         u16 value16;
2182
2183         b43_write32(dev, B43_MMIO_MACCTL,
2184                     B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2185
2186         err = b43_request_firmware(dev);
2187         if (err)
2188                 goto out;
2189         err = b43_upload_microcode(dev);
2190         if (err)
2191                 goto out;       /* firmware is released later */
2192
2193         err = b43_gpio_init(dev);
2194         if (err)
2195                 goto out;       /* firmware is released later */
2196         b43_leds_init(dev);
2197
2198         err = b43_upload_initvals(dev);
2199         if (err)
2200                 goto err_leds_exit;
2201         b43_radio_turn_on(dev);
2202
2203         b43_write16(dev, 0x03E6, 0x0000);
2204         err = b43_phy_init(dev);
2205         if (err)
2206                 goto err_radio_off;
2207
2208         /* Select initial Interference Mitigation. */
2209         tmp = phy->interfmode;
2210         phy->interfmode = B43_INTERFMODE_NONE;
2211         b43_radio_set_interference_mitigation(dev, tmp);
2212
2213         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2214         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2215
2216         if (phy->type == B43_PHYTYPE_B) {
2217                 value16 = b43_read16(dev, 0x005E);
2218                 value16 |= 0x0004;
2219                 b43_write16(dev, 0x005E, value16);
2220         }
2221         b43_write32(dev, 0x0100, 0x01000000);
2222         if (dev->dev->id.revision < 5)
2223                 b43_write32(dev, 0x010C, 0x01000000);
2224
2225         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2226                     & ~B43_MACCTL_INFRA);
2227         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2228                     | B43_MACCTL_INFRA);
2229
2230         if (b43_using_pio(dev)) {
2231                 b43_write32(dev, 0x0210, 0x00000100);
2232                 b43_write32(dev, 0x0230, 0x00000100);
2233                 b43_write32(dev, 0x0250, 0x00000100);
2234                 b43_write32(dev, 0x0270, 0x00000100);
2235                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2236         }
2237
2238         /* Probe Response Timeout value */
2239         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2240         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2241
2242         /* Initially set the wireless operation mode. */
2243         b43_adjust_opmode(dev);
2244
2245         if (dev->dev->id.revision < 3) {
2246                 b43_write16(dev, 0x060E, 0x0000);
2247                 b43_write16(dev, 0x0610, 0x8000);
2248                 b43_write16(dev, 0x0604, 0x0000);
2249                 b43_write16(dev, 0x0606, 0x0200);
2250         } else {
2251                 b43_write32(dev, 0x0188, 0x80000000);
2252                 b43_write32(dev, 0x018C, 0x02000000);
2253         }
2254         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2255         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2256         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2257         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2258         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2259         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2260         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2261
2262         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2263         value32 |= 0x00100000;
2264         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2265
2266         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2267                     dev->dev->bus->chipco.fast_pwrup_delay);
2268
2269         err = 0;
2270         b43dbg(dev->wl, "Chip initialized\n");
2271 out:
2272         return err;
2273
2274 err_radio_off:
2275         b43_radio_turn_off(dev, 1);
2276 err_leds_exit:
2277         b43_leds_exit(dev);
2278         b43_gpio_cleanup(dev);
2279         return err;
2280 }
2281
2282 static void b43_periodic_every120sec(struct b43_wldev *dev)
2283 {
2284         struct b43_phy *phy = &dev->phy;
2285
2286         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2287                 return;
2288
2289         b43_mac_suspend(dev);
2290         b43_lo_g_measure(dev);
2291         b43_mac_enable(dev);
2292         if (b43_has_hardware_pctl(phy))
2293                 b43_lo_g_ctl_mark_all_unused(dev);
2294 }
2295
2296 static void b43_periodic_every60sec(struct b43_wldev *dev)
2297 {
2298         struct b43_phy *phy = &dev->phy;
2299
2300         if (!b43_has_hardware_pctl(phy))
2301                 b43_lo_g_ctl_mark_all_unused(dev);
2302         if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
2303                 b43_mac_suspend(dev);
2304                 b43_calc_nrssi_slope(dev);
2305                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2306                         u8 old_chan = phy->channel;
2307
2308                         /* VCO Calibration */
2309                         if (old_chan >= 8)
2310                                 b43_radio_selectchannel(dev, 1, 0);
2311                         else
2312                                 b43_radio_selectchannel(dev, 13, 0);
2313                         b43_radio_selectchannel(dev, old_chan, 0);
2314                 }
2315                 b43_mac_enable(dev);
2316         }
2317 }
2318
2319 static void b43_periodic_every30sec(struct b43_wldev *dev)
2320 {
2321         /* Update device statistics. */
2322         b43_calculate_link_quality(dev);
2323 }
2324
2325 static void b43_periodic_every15sec(struct b43_wldev *dev)
2326 {
2327         struct b43_phy *phy = &dev->phy;
2328
2329         if (phy->type == B43_PHYTYPE_G) {
2330                 //TODO: update_aci_moving_average
2331                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2332                         b43_mac_suspend(dev);
2333                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2334                                 if (0 /*TODO: bunch of conditions */ ) {
2335                                         b43_radio_set_interference_mitigation
2336                                             (dev, B43_INTERFMODE_MANUALWLAN);
2337                                 }
2338                         } else if (1 /*TODO*/) {
2339                                 /*
2340                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2341                                    b43_radio_set_interference_mitigation(dev,
2342                                    B43_INTERFMODE_NONE);
2343                                    }
2344                                  */
2345                         }
2346                         b43_mac_enable(dev);
2347                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2348                            phy->rev == 1) {
2349                         //TODO: implement rev1 workaround
2350                 }
2351         }
2352         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2353         //TODO for APHY (temperature?)
2354 }
2355
2356 static void do_periodic_work(struct b43_wldev *dev)
2357 {
2358         unsigned int state;
2359
2360         state = dev->periodic_state;
2361         if (state % 8 == 0)
2362                 b43_periodic_every120sec(dev);
2363         if (state % 4 == 0)
2364                 b43_periodic_every60sec(dev);
2365         if (state % 2 == 0)
2366                 b43_periodic_every30sec(dev);
2367         b43_periodic_every15sec(dev);
2368 }
2369
2370 /* Periodic work locking policy:
2371  *      The whole periodic work handler is protected by
2372  *      wl->mutex. If another lock is needed somewhere in the
2373  *      pwork callchain, it's aquired in-place, where it's needed.
2374  */
2375 static void b43_periodic_work_handler(struct work_struct *work)
2376 {
2377         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2378                                              periodic_work.work);
2379         struct b43_wl *wl = dev->wl;
2380         unsigned long delay;
2381
2382         mutex_lock(&wl->mutex);
2383
2384         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2385                 goto out;
2386         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2387                 goto out_requeue;
2388
2389         do_periodic_work(dev);
2390
2391         dev->periodic_state++;
2392 out_requeue:
2393         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2394                 delay = msecs_to_jiffies(50);
2395         else
2396                 delay = round_jiffies(HZ * 15);
2397         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2398 out:
2399         mutex_unlock(&wl->mutex);
2400 }
2401
2402 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2403 {
2404         struct delayed_work *work = &dev->periodic_work;
2405
2406         dev->periodic_state = 0;
2407         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2408         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2409 }
2410
2411 /* Validate access to the chip (SHM) */
2412 static int b43_validate_chipaccess(struct b43_wldev *dev)
2413 {
2414         u32 value;
2415         u32 shm_backup;
2416
2417         shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2418         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2419         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2420                 goto error;
2421         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2422         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2423                 goto error;
2424         b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
2425
2426         value = b43_read32(dev, B43_MMIO_MACCTL);
2427         if ((value | B43_MACCTL_GMODE) !=
2428             (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2429                 goto error;
2430
2431         value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2432         if (value)
2433                 goto error;
2434
2435         return 0;
2436       error:
2437         b43err(dev->wl, "Failed to validate the chipaccess\n");
2438         return -ENODEV;
2439 }
2440
2441 static void b43_security_init(struct b43_wldev *dev)
2442 {
2443         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2444         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2445         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2446         /* KTP is a word address, but we address SHM bytewise.
2447          * So multiply by two.
2448          */
2449         dev->ktp *= 2;
2450         if (dev->dev->id.revision >= 5) {
2451                 /* Number of RCMTA address slots */
2452                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2453         }
2454         b43_clear_keys(dev);
2455 }
2456
2457 static int b43_rng_read(struct hwrng *rng, u32 * data)
2458 {
2459         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2460         unsigned long flags;
2461
2462         /* Don't take wl->mutex here, as it could deadlock with
2463          * hwrng internal locking. It's not needed to take
2464          * wl->mutex here, anyway. */
2465
2466         spin_lock_irqsave(&wl->irq_lock, flags);
2467         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2468         spin_unlock_irqrestore(&wl->irq_lock, flags);
2469
2470         return (sizeof(u16));
2471 }
2472
2473 static void b43_rng_exit(struct b43_wl *wl)
2474 {
2475         if (wl->rng_initialized)
2476                 hwrng_unregister(&wl->rng);
2477 }
2478
2479 static int b43_rng_init(struct b43_wl *wl)
2480 {
2481         int err;
2482
2483         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2484                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2485         wl->rng.name = wl->rng_name;
2486         wl->rng.data_read = b43_rng_read;
2487         wl->rng.priv = (unsigned long)wl;
2488         wl->rng_initialized = 1;
2489         err = hwrng_register(&wl->rng);
2490         if (err) {
2491                 wl->rng_initialized = 0;
2492                 b43err(wl, "Failed to register the random "
2493                        "number generator (%d)\n", err);
2494         }
2495
2496         return err;
2497 }
2498
2499 static int b43_tx(struct ieee80211_hw *hw,
2500                   struct sk_buff *skb, struct ieee80211_tx_control *ctl)
2501 {
2502         struct b43_wl *wl = hw_to_b43_wl(hw);
2503         struct b43_wldev *dev = wl->current_dev;
2504         int err = -ENODEV;
2505         unsigned long flags;
2506
2507         if (unlikely(!dev))
2508                 goto out;
2509         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2510                 goto out;
2511         /* DMA-TX is done without a global lock. */
2512         if (b43_using_pio(dev)) {
2513                 spin_lock_irqsave(&wl->irq_lock, flags);
2514                 err = b43_pio_tx(dev, skb, ctl);
2515                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2516         } else
2517                 err = b43_dma_tx(dev, skb, ctl);
2518       out:
2519         if (unlikely(err))
2520                 return NETDEV_TX_BUSY;
2521         return NETDEV_TX_OK;
2522 }
2523
2524 static int b43_conf_tx(struct ieee80211_hw *hw,
2525                        int queue,
2526                        const struct ieee80211_tx_queue_params *params)
2527 {
2528         return 0;
2529 }
2530
2531 static int b43_get_tx_stats(struct ieee80211_hw *hw,
2532                             struct ieee80211_tx_queue_stats *stats)
2533 {
2534         struct b43_wl *wl = hw_to_b43_wl(hw);
2535         struct b43_wldev *dev = wl->current_dev;
2536         unsigned long flags;
2537         int err = -ENODEV;
2538
2539         if (!dev)
2540                 goto out;
2541         spin_lock_irqsave(&wl->irq_lock, flags);
2542         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2543                 if (b43_using_pio(dev))
2544                         b43_pio_get_tx_stats(dev, stats);
2545                 else
2546                         b43_dma_get_tx_stats(dev, stats);
2547                 err = 0;
2548         }
2549         spin_unlock_irqrestore(&wl->irq_lock, flags);
2550       out:
2551         return err;
2552 }
2553
2554 static int b43_get_stats(struct ieee80211_hw *hw,
2555                          struct ieee80211_low_level_stats *stats)
2556 {
2557         struct b43_wl *wl = hw_to_b43_wl(hw);
2558         unsigned long flags;
2559
2560         spin_lock_irqsave(&wl->irq_lock, flags);
2561         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2562         spin_unlock_irqrestore(&wl->irq_lock, flags);
2563
2564         return 0;
2565 }
2566
2567 static const char *phymode_to_string(unsigned int phymode)
2568 {
2569         switch (phymode) {
2570         case B43_PHYMODE_A:
2571                 return "A";
2572         case B43_PHYMODE_B:
2573                 return "B";
2574         case B43_PHYMODE_G:
2575                 return "G";
2576         default:
2577                 B43_WARN_ON(1);
2578         }
2579         return "";
2580 }
2581
2582 static int find_wldev_for_phymode(struct b43_wl *wl,
2583                                   unsigned int phymode,
2584                                   struct b43_wldev **dev, bool * gmode)
2585 {
2586         struct b43_wldev *d;
2587
2588         list_for_each_entry(d, &wl->devlist, list) {
2589                 if (d->phy.possible_phymodes & phymode) {
2590                         /* Ok, this device supports the PHY-mode.
2591                          * Now figure out how the gmode bit has to be
2592                          * set to support it. */
2593                         if (phymode == B43_PHYMODE_A)
2594                                 *gmode = 0;
2595                         else
2596                                 *gmode = 1;
2597                         *dev = d;
2598
2599                         return 0;
2600                 }
2601         }
2602
2603         return -ESRCH;
2604 }
2605
2606 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2607 {
2608         struct ssb_device *sdev = dev->dev;
2609         u32 tmslow;
2610
2611         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2612         tmslow &= ~B43_TMSLOW_GMODE;
2613         tmslow |= B43_TMSLOW_PHYRESET;
2614         tmslow |= SSB_TMSLOW_FGC;
2615         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2616         msleep(1);
2617
2618         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2619         tmslow &= ~SSB_TMSLOW_FGC;
2620         tmslow |= B43_TMSLOW_PHYRESET;
2621         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2622         msleep(1);
2623 }
2624
2625 /* Expects wl->mutex locked */
2626 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2627 {
2628         struct b43_wldev *up_dev;
2629         struct b43_wldev *down_dev;
2630         int err;
2631         bool gmode = 0;
2632         int prev_status;
2633
2634         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2635         if (err) {
2636                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2637                        phymode_to_string(new_mode));
2638                 return err;
2639         }
2640         if ((up_dev == wl->current_dev) &&
2641             (!!wl->current_dev->phy.gmode == !!gmode)) {
2642                 /* This device is already running. */
2643                 return 0;
2644         }
2645         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2646                phymode_to_string(new_mode));
2647         down_dev = wl->current_dev;
2648
2649         prev_status = b43_status(down_dev);
2650         /* Shutdown the currently running core. */
2651         if (prev_status >= B43_STAT_STARTED)
2652                 b43_wireless_core_stop(down_dev);
2653         if (prev_status >= B43_STAT_INITIALIZED)
2654                 b43_wireless_core_exit(down_dev);
2655
2656         if (down_dev != up_dev) {
2657                 /* We switch to a different core, so we put PHY into
2658                  * RESET on the old core. */
2659                 b43_put_phy_into_reset(down_dev);
2660         }
2661
2662         /* Now start the new core. */
2663         up_dev->phy.gmode = gmode;
2664         if (prev_status >= B43_STAT_INITIALIZED) {
2665                 err = b43_wireless_core_init(up_dev);
2666                 if (err) {
2667                         b43err(wl, "Fatal: Could not initialize device for "
2668                                "newly selected %s-PHY mode\n",
2669                                phymode_to_string(new_mode));
2670                         goto init_failure;
2671                 }
2672         }
2673         if (prev_status >= B43_STAT_STARTED) {
2674                 err = b43_wireless_core_start(up_dev);
2675                 if (err) {
2676                         b43err(wl, "Fatal: Coult not start device for "
2677                                "newly selected %s-PHY mode\n",
2678                                phymode_to_string(new_mode));
2679                         b43_wireless_core_exit(up_dev);
2680                         goto init_failure;
2681                 }
2682         }
2683         B43_WARN_ON(b43_status(up_dev) != prev_status);
2684
2685         wl->current_dev = up_dev;
2686
2687         return 0;
2688       init_failure:
2689         /* Whoops, failed to init the new core. No core is operating now. */
2690         wl->current_dev = NULL;
2691         return err;
2692 }
2693
2694 static int b43_antenna_from_ieee80211(u8 antenna)
2695 {
2696         switch (antenna) {
2697         case 0:         /* default/diversity */
2698                 return B43_ANTENNA_DEFAULT;
2699         case 1:         /* Antenna 0 */
2700                 return B43_ANTENNA0;
2701         case 2:         /* Antenna 1 */
2702                 return B43_ANTENNA1;
2703         default:
2704                 return B43_ANTENNA_DEFAULT;
2705         }
2706 }
2707
2708 static int b43_dev_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2709 {
2710         struct b43_wl *wl = hw_to_b43_wl(hw);
2711         struct b43_wldev *dev;
2712         struct b43_phy *phy;
2713         unsigned long flags;
2714         unsigned int new_phymode = 0xFFFF;
2715         int antenna_tx;
2716         int antenna_rx;
2717         int err = 0;
2718         u32 savedirqs;
2719
2720         antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx);
2721         antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx);
2722
2723         mutex_lock(&wl->mutex);
2724
2725         /* Switch the PHY mode (if necessary). */
2726         switch (conf->phymode) {
2727         case MODE_IEEE80211A:
2728                 new_phymode = B43_PHYMODE_A;
2729                 break;
2730         case MODE_IEEE80211B:
2731                 new_phymode = B43_PHYMODE_B;
2732                 break;
2733         case MODE_IEEE80211G:
2734                 new_phymode = B43_PHYMODE_G;
2735                 break;
2736         default:
2737                 B43_WARN_ON(1);
2738         }
2739         err = b43_switch_phymode(wl, new_phymode);
2740         if (err)
2741                 goto out_unlock_mutex;
2742         dev = wl->current_dev;
2743         phy = &dev->phy;
2744
2745         /* Disable IRQs while reconfiguring the device.
2746          * This makes it possible to drop the spinlock throughout
2747          * the reconfiguration process. */
2748         spin_lock_irqsave(&wl->irq_lock, flags);
2749         if (b43_status(dev) < B43_STAT_STARTED) {
2750                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2751                 goto out_unlock_mutex;
2752         }
2753         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2754         spin_unlock_irqrestore(&wl->irq_lock, flags);
2755         b43_synchronize_irq(dev);
2756
2757         /* Switch to the requested channel.
2758          * The firmware takes care of races with the TX handler. */
2759         if (conf->channel_val != phy->channel)
2760                 b43_radio_selectchannel(dev, conf->channel_val, 0);
2761
2762         /* Enable/Disable ShortSlot timing. */
2763         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2764             dev->short_slot) {
2765                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2766                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2767                         b43_short_slot_timing_enable(dev);
2768                 else
2769                         b43_short_slot_timing_disable(dev);
2770         }
2771
2772         /* Adjust the desired TX power level. */
2773         if (conf->power_level != 0) {
2774                 if (conf->power_level != phy->power_level) {
2775                         phy->power_level = conf->power_level;
2776                         b43_phy_xmitpower(dev);
2777                 }
2778         }
2779
2780         /* Antennas for RX and management frame TX. */
2781         b43_mgmtframe_txantenna(dev, antenna_tx);
2782         b43_set_rx_antenna(dev, antenna_rx);
2783
2784         /* Update templates for AP mode. */
2785         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2786                 b43_set_beacon_int(dev, conf->beacon_int);
2787
2788         if (!!conf->radio_enabled != phy->radio_on) {
2789                 if (conf->radio_enabled) {
2790                         b43_radio_turn_on(dev);
2791                         b43info(dev->wl, "Radio turned on by software\n");
2792                         if (!dev->radio_hw_enable) {
2793                                 b43info(dev->wl, "The hardware RF-kill button "
2794                                         "still turns the radio physically off. "
2795                                         "Press the button to turn it on.\n");
2796                         }
2797                 } else {
2798                         b43_radio_turn_off(dev, 0);
2799                         b43info(dev->wl, "Radio turned off by software\n");
2800                 }
2801         }
2802
2803         spin_lock_irqsave(&wl->irq_lock, flags);
2804         b43_interrupt_enable(dev, savedirqs);
2805         mmiowb();
2806         spin_unlock_irqrestore(&wl->irq_lock, flags);
2807       out_unlock_mutex:
2808         mutex_unlock(&wl->mutex);
2809
2810         return err;
2811 }
2812
2813 static int b43_dev_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2814                            const u8 *local_addr, const u8 *addr,
2815                            struct ieee80211_key_conf *key)
2816 {
2817         struct b43_wl *wl = hw_to_b43_wl(hw);
2818         struct b43_wldev *dev = wl->current_dev;
2819         unsigned long flags;
2820         u8 algorithm;
2821         u8 index;
2822         int err = -EINVAL;
2823
2824         if (modparam_nohwcrypt)
2825                 return -ENOSPC; /* User disabled HW-crypto */
2826
2827         if (!dev)
2828                 return -ENODEV;
2829         switch (key->alg) {
2830         case ALG_WEP:
2831                 if (key->keylen == 5)
2832                         algorithm = B43_SEC_ALGO_WEP40;
2833                 else
2834                         algorithm = B43_SEC_ALGO_WEP104;
2835                 break;
2836         case ALG_TKIP:
2837                 algorithm = B43_SEC_ALGO_TKIP;
2838                 break;
2839         case ALG_CCMP:
2840                 algorithm = B43_SEC_ALGO_AES;
2841                 break;
2842         default:
2843                 B43_WARN_ON(1);
2844                 goto out;
2845         }
2846
2847         index = (u8) (key->keyidx);
2848         if (index > 3)
2849                 goto out;
2850
2851         mutex_lock(&wl->mutex);
2852         spin_lock_irqsave(&wl->irq_lock, flags);
2853
2854         if (b43_status(dev) < B43_STAT_INITIALIZED) {
2855                 err = -ENODEV;
2856                 goto out_unlock;
2857         }
2858
2859         switch (cmd) {
2860         case SET_KEY:
2861                 if (algorithm == B43_SEC_ALGO_TKIP) {
2862                         /* FIXME: No TKIP hardware encryption for now. */
2863                         err = -EOPNOTSUPP;
2864                         goto out_unlock;
2865                 }
2866
2867                 if (is_broadcast_ether_addr(addr)) {
2868                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2869                         err = b43_key_write(dev, index, algorithm,
2870                                             key->key, key->keylen, NULL, key);
2871                 } else {
2872                         /*
2873                          * either pairwise key or address is 00:00:00:00:00:00
2874                          * for transmit-only keys
2875                          */
2876                         err = b43_key_write(dev, -1, algorithm,
2877                                             key->key, key->keylen, addr, key);
2878                 }
2879                 if (err)
2880                         goto out_unlock;
2881
2882                 if (algorithm == B43_SEC_ALGO_WEP40 ||
2883                     algorithm == B43_SEC_ALGO_WEP104) {
2884                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2885                 } else {
2886                         b43_hf_write(dev,
2887                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2888                 }
2889                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2890                 break;
2891         case DISABLE_KEY: {
2892                 err = b43_key_clear(dev, key->hw_key_idx);
2893                 if (err)
2894                         goto out_unlock;
2895                 break;
2896         }
2897         default:
2898                 B43_WARN_ON(1);
2899         }
2900 out_unlock:
2901         spin_unlock_irqrestore(&wl->irq_lock, flags);
2902         mutex_unlock(&wl->mutex);
2903 out:
2904         if (!err) {
2905                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2906                        "mac: " MAC_FMT "\n",
2907                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2908                        MAC_ARG(addr));
2909         }
2910         return err;
2911 }
2912
2913 static void b43_configure_filter(struct ieee80211_hw *hw,
2914                                  unsigned int changed, unsigned int *fflags,
2915                                  int mc_count, struct dev_addr_list *mc_list)
2916 {
2917         struct b43_wl *wl = hw_to_b43_wl(hw);
2918         struct b43_wldev *dev = wl->current_dev;
2919         unsigned long flags;
2920
2921         if (!dev) {
2922                 *fflags = 0;
2923                 return;
2924         }
2925
2926         spin_lock_irqsave(&wl->irq_lock, flags);
2927         *fflags &= FIF_PROMISC_IN_BSS |
2928                   FIF_ALLMULTI |
2929                   FIF_FCSFAIL |
2930                   FIF_PLCPFAIL |
2931                   FIF_CONTROL |
2932                   FIF_OTHER_BSS |
2933                   FIF_BCN_PRBRESP_PROMISC;
2934
2935         changed &= FIF_PROMISC_IN_BSS |
2936                    FIF_ALLMULTI |
2937                    FIF_FCSFAIL |
2938                    FIF_PLCPFAIL |
2939                    FIF_CONTROL |
2940                    FIF_OTHER_BSS |
2941                    FIF_BCN_PRBRESP_PROMISC;
2942
2943         wl->filter_flags = *fflags;
2944
2945         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2946                 b43_adjust_opmode(dev);
2947         spin_unlock_irqrestore(&wl->irq_lock, flags);
2948 }
2949
2950 static int b43_config_interface(struct ieee80211_hw *hw,
2951                                 int if_id, struct ieee80211_if_conf *conf)
2952 {
2953         struct b43_wl *wl = hw_to_b43_wl(hw);
2954         struct b43_wldev *dev = wl->current_dev;
2955         unsigned long flags;
2956
2957         if (!dev)
2958                 return -ENODEV;
2959         mutex_lock(&wl->mutex);
2960         spin_lock_irqsave(&wl->irq_lock, flags);
2961         B43_WARN_ON(wl->if_id != if_id);
2962         if (conf->bssid)
2963                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2964         else
2965                 memset(wl->bssid, 0, ETH_ALEN);
2966         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2967                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2968                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2969                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2970                         if (conf->beacon)
2971                                 b43_refresh_templates(dev, conf->beacon);
2972                 }
2973                 b43_write_mac_bssid_templates(dev);
2974         }
2975         spin_unlock_irqrestore(&wl->irq_lock, flags);
2976         mutex_unlock(&wl->mutex);
2977
2978         return 0;
2979 }
2980
2981 /* Locking: wl->mutex */
2982 static void b43_wireless_core_stop(struct b43_wldev *dev)
2983 {
2984         struct b43_wl *wl = dev->wl;
2985         unsigned long flags;
2986
2987         if (b43_status(dev) < B43_STAT_STARTED)
2988                 return;
2989         b43_set_status(dev, B43_STAT_INITIALIZED);
2990
2991         mutex_unlock(&wl->mutex);
2992         /* Must unlock as it would otherwise deadlock. No races here.
2993          * Cancel the possibly running self-rearming periodic work. */
2994         cancel_delayed_work_sync(&dev->periodic_work);
2995         mutex_lock(&wl->mutex);
2996
2997         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
2998
2999         /* Disable and sync interrupts. */
3000         spin_lock_irqsave(&wl->irq_lock, flags);
3001         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3002         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3003         spin_unlock_irqrestore(&wl->irq_lock, flags);
3004         b43_synchronize_irq(dev);
3005
3006         b43_mac_suspend(dev);
3007         free_irq(dev->dev->irq, dev);
3008         b43dbg(wl, "Wireless interface stopped\n");
3009 }
3010
3011 /* Locking: wl->mutex */
3012 static int b43_wireless_core_start(struct b43_wldev *dev)
3013 {
3014         int err;
3015
3016         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3017
3018         drain_txstatus_queue(dev);
3019         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3020                           IRQF_SHARED, KBUILD_MODNAME, dev);
3021         if (err) {
3022                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3023                 goto out;
3024         }
3025
3026         /* We are ready to run. */
3027         b43_set_status(dev, B43_STAT_STARTED);
3028
3029         /* Start data flow (TX/RX). */
3030         b43_mac_enable(dev);
3031         b43_interrupt_enable(dev, dev->irq_savedstate);
3032         ieee80211_start_queues(dev->wl->hw);
3033
3034         /* Start maintainance work */
3035         b43_periodic_tasks_setup(dev);
3036
3037         b43dbg(dev->wl, "Wireless interface started\n");
3038       out:
3039         return err;
3040 }
3041
3042 /* Get PHY and RADIO versioning numbers */
3043 static int b43_phy_versioning(struct b43_wldev *dev)
3044 {
3045         struct b43_phy *phy = &dev->phy;
3046         u32 tmp;
3047         u8 analog_type;
3048         u8 phy_type;
3049         u8 phy_rev;
3050         u16 radio_manuf;
3051         u16 radio_ver;
3052         u16 radio_rev;
3053         int unsupported = 0;
3054
3055         /* Get PHY versioning */
3056         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3057         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3058         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3059         phy_rev = (tmp & B43_PHYVER_VERSION);
3060         switch (phy_type) {
3061         case B43_PHYTYPE_A:
3062                 if (phy_rev >= 4)
3063                         unsupported = 1;
3064                 break;
3065         case B43_PHYTYPE_B:
3066                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3067                     && phy_rev != 7)
3068                         unsupported = 1;
3069                 break;
3070         case B43_PHYTYPE_G:
3071                 if (phy_rev > 8)
3072                         unsupported = 1;
3073                 break;
3074         default:
3075                 unsupported = 1;
3076         };
3077         if (unsupported) {
3078                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3079                        "(Analog %u, Type %u, Revision %u)\n",
3080                        analog_type, phy_type, phy_rev);
3081                 return -EOPNOTSUPP;
3082         }
3083         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3084                analog_type, phy_type, phy_rev);
3085
3086         /* Get RADIO versioning */
3087         if (dev->dev->bus->chip_id == 0x4317) {
3088                 if (dev->dev->bus->chip_rev == 0)
3089                         tmp = 0x3205017F;
3090                 else if (dev->dev->bus->chip_rev == 1)
3091                         tmp = 0x4205017F;
3092                 else
3093                         tmp = 0x5205017F;
3094         } else {
3095                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3096                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3097                 tmp <<= 16;
3098                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3099                 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3100         }
3101         radio_manuf = (tmp & 0x00000FFF);
3102         radio_ver = (tmp & 0x0FFFF000) >> 12;
3103         radio_rev = (tmp & 0xF0000000) >> 28;
3104         switch (phy_type) {
3105         case B43_PHYTYPE_A:
3106                 if (radio_ver != 0x2060)
3107                         unsupported = 1;
3108                 if (radio_rev != 1)
3109                         unsupported = 1;
3110                 if (radio_manuf != 0x17F)
3111                         unsupported = 1;
3112                 break;
3113         case B43_PHYTYPE_B:
3114                 if ((radio_ver & 0xFFF0) != 0x2050)
3115                         unsupported = 1;
3116                 break;
3117         case B43_PHYTYPE_G:
3118                 if (radio_ver != 0x2050)
3119                         unsupported = 1;
3120                 break;
3121         default:
3122                 B43_WARN_ON(1);
3123         }
3124         if (unsupported) {
3125                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3126                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3127                        radio_manuf, radio_ver, radio_rev);
3128                 return -EOPNOTSUPP;
3129         }
3130         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3131                radio_manuf, radio_ver, radio_rev);
3132
3133         phy->radio_manuf = radio_manuf;
3134         phy->radio_ver = radio_ver;
3135         phy->radio_rev = radio_rev;
3136
3137         phy->analog = analog_type;
3138         phy->type = phy_type;
3139         phy->rev = phy_rev;
3140
3141         return 0;
3142 }
3143
3144 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3145                                       struct b43_phy *phy)
3146 {
3147         struct b43_txpower_lo_control *lo;
3148         int i;
3149
3150         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3151         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3152
3153         /* Flags */
3154         phy->locked = 0;
3155
3156         phy->aci_enable = 0;
3157         phy->aci_wlan_automatic = 0;
3158         phy->aci_hw_rssi = 0;
3159
3160         phy->radio_off_context.valid = 0;
3161
3162         lo = phy->lo_control;
3163         if (lo) {
3164                 memset(lo, 0, sizeof(*(phy->lo_control)));
3165                 lo->rebuild = 1;
3166                 lo->tx_bias = 0xFF;
3167         }
3168         phy->max_lb_gain = 0;
3169         phy->trsw_rx_gain = 0;
3170         phy->txpwr_offset = 0;
3171
3172         /* NRSSI */
3173         phy->nrssislope = 0;
3174         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3175                 phy->nrssi[i] = -1000;
3176         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3177                 phy->nrssi_lt[i] = i;
3178
3179         phy->lofcal = 0xFFFF;
3180         phy->initval = 0xFFFF;
3181
3182         spin_lock_init(&phy->lock);
3183         phy->interfmode = B43_INTERFMODE_NONE;
3184         phy->channel = 0xFF;
3185
3186         phy->hardware_power_control = !!modparam_hwpctl;
3187 }
3188
3189 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3190 {
3191         /* Flags */
3192         dev->reg124_set_0x4 = 0;
3193         /* Assume the radio is enabled. If it's not enabled, the state will
3194          * immediately get fixed on the first periodic work run. */
3195         dev->radio_hw_enable = 1;
3196
3197         /* Stats */
3198         memset(&dev->stats, 0, sizeof(dev->stats));
3199
3200         setup_struct_phy_for_init(dev, &dev->phy);
3201
3202         /* IRQ related flags */
3203         dev->irq_reason = 0;
3204         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3205         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3206
3207         dev->mac_suspended = 1;
3208
3209         /* Noise calculation context */
3210         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3211 }
3212
3213 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3214 {
3215         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3216         u32 hf;
3217
3218         if (!(sprom->r1.boardflags_lo & B43_BFL_BTCOEXIST))
3219                 return;
3220         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3221                 return;
3222
3223         hf = b43_hf_read(dev);
3224         if (sprom->r1.boardflags_lo & B43_BFL_BTCMOD)
3225                 hf |= B43_HF_BTCOEXALT;
3226         else
3227                 hf |= B43_HF_BTCOEX;
3228         b43_hf_write(dev, hf);
3229         //TODO
3230 }
3231
3232 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3233 {                               //TODO
3234 }
3235
3236 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3237 {
3238 #ifdef CONFIG_SSB_DRIVER_PCICORE
3239         struct ssb_bus *bus = dev->dev->bus;
3240         u32 tmp;
3241
3242         if (bus->pcicore.dev &&
3243             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3244             bus->pcicore.dev->id.revision <= 5) {
3245                 /* IMCFGLO timeouts workaround. */
3246                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3247                 tmp &= ~SSB_IMCFGLO_REQTO;
3248                 tmp &= ~SSB_IMCFGLO_SERTO;
3249                 switch (bus->bustype) {
3250                 case SSB_BUSTYPE_PCI:
3251                 case SSB_BUSTYPE_PCMCIA:
3252                         tmp |= 0x32;
3253                         break;
3254                 case SSB_BUSTYPE_SSB:
3255                         tmp |= 0x53;
3256                         break;
3257                 }
3258                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3259         }
3260 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3261 }
3262
3263 /* Shutdown a wireless core */
3264 /* Locking: wl->mutex */
3265 static void b43_wireless_core_exit(struct b43_wldev *dev)
3266 {
3267         struct b43_phy *phy = &dev->phy;
3268
3269         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3270         if (b43_status(dev) != B43_STAT_INITIALIZED)
3271                 return;
3272         b43_set_status(dev, B43_STAT_UNINIT);
3273
3274         mutex_unlock(&dev->wl->mutex);
3275         b43_rfkill_exit(dev);
3276         mutex_lock(&dev->wl->mutex);
3277
3278         b43_rng_exit(dev->wl);
3279         b43_pio_free(dev);
3280         b43_dma_free(dev);
3281         b43_chip_exit(dev);
3282         b43_radio_turn_off(dev, 1);
3283         b43_switch_analog(dev, 0);
3284         if (phy->dyn_tssi_tbl)
3285                 kfree(phy->tssi2dbm);
3286         kfree(phy->lo_control);
3287         phy->lo_control = NULL;
3288         ssb_device_disable(dev->dev, 0);
3289         ssb_bus_may_powerdown(dev->dev->bus);
3290 }
3291
3292 /* Initialize a wireless core */
3293 static int b43_wireless_core_init(struct b43_wldev *dev)
3294 {
3295         struct b43_wl *wl = dev->wl;
3296         struct ssb_bus *bus = dev->dev->bus;
3297         struct ssb_sprom *sprom = &bus->sprom;
3298         struct b43_phy *phy = &dev->phy;
3299         int err;
3300         u32 hf, tmp;
3301
3302         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3303
3304         err = ssb_bus_powerup(bus, 0);
3305         if (err)
3306                 goto out;
3307         if (!ssb_device_is_enabled(dev->dev)) {
3308                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3309                 b43_wireless_core_reset(dev, tmp);
3310         }
3311
3312         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3313                 phy->lo_control =
3314                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3315                 if (!phy->lo_control) {
3316                         err = -ENOMEM;
3317                         goto err_busdown;
3318                 }
3319         }
3320         setup_struct_wldev_for_init(dev);
3321
3322         err = b43_phy_init_tssi2dbm_table(dev);
3323         if (err)
3324                 goto err_kfree_lo_control;
3325
3326         /* Enable IRQ routing to this device. */
3327         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3328
3329         b43_imcfglo_timeouts_workaround(dev);
3330         b43_bluetooth_coext_disable(dev);
3331         b43_phy_early_init(dev);
3332         err = b43_chip_init(dev);
3333         if (err)
3334                 goto err_kfree_tssitbl;
3335         b43_shm_write16(dev, B43_SHM_SHARED,
3336                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3337         hf = b43_hf_read(dev);
3338         if (phy->type == B43_PHYTYPE_G) {
3339                 hf |= B43_HF_SYMW;
3340                 if (phy->rev == 1)
3341                         hf |= B43_HF_GDCW;
3342                 if (sprom->r1.boardflags_lo & B43_BFL_PACTRL)
3343                         hf |= B43_HF_OFDMPABOOST;
3344         } else if (phy->type == B43_PHYTYPE_B) {
3345                 hf |= B43_HF_SYMW;
3346                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3347                         hf &= ~B43_HF_GDCW;
3348         }
3349         b43_hf_write(dev, hf);
3350
3351         /* Short/Long Retry Limit.
3352          * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
3353          * the chip-internal counter.
3354          */
3355         tmp = limit_value(modparam_short_retry, 0, 0xF);
3356         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, tmp);
3357         tmp = limit_value(modparam_long_retry, 0, 0xF);
3358         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, tmp);
3359
3360         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3361         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3362
3363         /* Disable sending probe responses from firmware.
3364          * Setting the MaxTime to one usec will always trigger
3365          * a timeout, so we never send any probe resp.
3366          * A timeout of zero is infinite. */
3367         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3368
3369         b43_rate_memory_init(dev);
3370
3371         /* Minimum Contention Window */
3372         if (phy->type == B43_PHYTYPE_B) {
3373                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3374         } else {
3375                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3376         }
3377         /* Maximum Contention Window */
3378         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3379
3380         do {
3381                 if (b43_using_pio(dev)) {
3382                         err = b43_pio_init(dev);
3383                 } else {
3384                         err = b43_dma_init(dev);
3385                         if (!err)
3386                                 b43_qos_init(dev);
3387                 }
3388         } while (err == -EAGAIN);
3389         if (err)
3390                 goto err_chip_exit;
3391
3392 //FIXME
3393 #if 1
3394         b43_write16(dev, 0x0612, 0x0050);
3395         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3396         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3397 #endif
3398
3399         b43_bluetooth_coext_enable(dev);
3400
3401         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3402         memset(wl->bssid, 0, ETH_ALEN);
3403         memset(wl->mac_addr, 0, ETH_ALEN);
3404         b43_upload_card_macaddress(dev);
3405         b43_security_init(dev);
3406         b43_rfkill_init(dev);
3407         b43_rng_init(wl);
3408
3409         b43_set_status(dev, B43_STAT_INITIALIZED);
3410
3411       out:
3412         return err;
3413
3414       err_chip_exit:
3415         b43_chip_exit(dev);
3416       err_kfree_tssitbl:
3417         if (phy->dyn_tssi_tbl)
3418                 kfree(phy->tssi2dbm);
3419       err_kfree_lo_control:
3420         kfree(phy->lo_control);
3421         phy->lo_control = NULL;
3422       err_busdown:
3423         ssb_bus_may_powerdown(bus);
3424         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3425         return err;
3426 }
3427
3428 static int b43_add_interface(struct ieee80211_hw *hw,
3429                              struct ieee80211_if_init_conf *conf)
3430 {
3431         struct b43_wl *wl = hw_to_b43_wl(hw);
3432         struct b43_wldev *dev;
3433         unsigned long flags;
3434         int err = -EOPNOTSUPP;
3435
3436         /* TODO: allow WDS/AP devices to coexist */
3437
3438         if (conf->type != IEEE80211_IF_TYPE_AP &&
3439             conf->type != IEEE80211_IF_TYPE_STA &&
3440             conf->type != IEEE80211_IF_TYPE_WDS &&
3441             conf->type != IEEE80211_IF_TYPE_IBSS)
3442                 return -EOPNOTSUPP;
3443
3444         mutex_lock(&wl->mutex);
3445         if (wl->operating)
3446                 goto out_mutex_unlock;
3447
3448         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3449
3450         dev = wl->current_dev;
3451         wl->operating = 1;
3452         wl->if_id = conf->if_id;
3453         wl->if_type = conf->type;
3454         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3455
3456         spin_lock_irqsave(&wl->irq_lock, flags);
3457         b43_adjust_opmode(dev);
3458         b43_upload_card_macaddress(dev);
3459         spin_unlock_irqrestore(&wl->irq_lock, flags);
3460
3461         err = 0;
3462  out_mutex_unlock:
3463         mutex_unlock(&wl->mutex);
3464
3465         return err;
3466 }
3467
3468 static void b43_remove_interface(struct ieee80211_hw *hw,
3469                                  struct ieee80211_if_init_conf *conf)
3470 {
3471         struct b43_wl *wl = hw_to_b43_wl(hw);
3472         struct b43_wldev *dev = wl->current_dev;
3473         unsigned long flags;
3474
3475         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3476
3477         mutex_lock(&wl->mutex);
3478
3479         B43_WARN_ON(!wl->operating);
3480         B43_WARN_ON(wl->if_id != conf->if_id);
3481
3482         wl->operating = 0;
3483
3484         spin_lock_irqsave(&wl->irq_lock, flags);
3485         b43_adjust_opmode(dev);
3486         memset(wl->mac_addr, 0, ETH_ALEN);
3487         b43_upload_card_macaddress(dev);
3488         spin_unlock_irqrestore(&wl->irq_lock, flags);
3489
3490         mutex_unlock(&wl->mutex);
3491 }
3492
3493 static int b43_start(struct ieee80211_hw *hw)
3494 {
3495         struct b43_wl *wl = hw_to_b43_wl(hw);
3496         struct b43_wldev *dev = wl->current_dev;
3497         int did_init = 0;
3498         int err;
3499
3500         mutex_lock(&wl->mutex);
3501
3502         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3503                 err = b43_wireless_core_init(dev);
3504                 if (err)
3505                         goto out_mutex_unlock;
3506                 did_init = 1;
3507         }
3508
3509         if (b43_status(dev) < B43_STAT_STARTED) {
3510                 err = b43_wireless_core_start(dev);
3511                 if (err) {
3512                         if (did_init)
3513                                 b43_wireless_core_exit(dev);
3514                         goto out_mutex_unlock;
3515                 }
3516         }
3517
3518  out_mutex_unlock:
3519         mutex_unlock(&wl->mutex);
3520
3521         return err;
3522 }
3523
3524 void b43_stop(struct ieee80211_hw *hw)
3525 {
3526         struct b43_wl *wl = hw_to_b43_wl(hw);
3527         struct b43_wldev *dev = wl->current_dev;
3528
3529         mutex_lock(&wl->mutex);
3530         if (b43_status(dev) >= B43_STAT_STARTED)
3531                 b43_wireless_core_stop(dev);
3532         b43_wireless_core_exit(dev);
3533         mutex_unlock(&wl->mutex);
3534 }
3535
3536 static const struct ieee80211_ops b43_hw_ops = {
3537         .tx = b43_tx,
3538         .conf_tx = b43_conf_tx,
3539         .add_interface = b43_add_interface,
3540         .remove_interface = b43_remove_interface,
3541         .config = b43_dev_config,
3542         .config_interface = b43_config_interface,
3543         .configure_filter = b43_configure_filter,
3544         .set_key = b43_dev_set_key,
3545         .get_stats = b43_get_stats,
3546         .get_tx_stats = b43_get_tx_stats,
3547         .start = b43_start,
3548         .stop = b43_stop,
3549 };
3550
3551 /* Hard-reset the chip. Do not call this directly.
3552  * Use b43_controller_restart()
3553  */
3554 static void b43_chip_reset(struct work_struct *work)
3555 {
3556         struct b43_wldev *dev =
3557             container_of(work, struct b43_wldev, restart_work);
3558         struct b43_wl *wl = dev->wl;
3559         int err = 0;
3560         int prev_status;
3561
3562         mutex_lock(&wl->mutex);
3563
3564         prev_status = b43_status(dev);
3565         /* Bring the device down... */
3566         if (prev_status >= B43_STAT_STARTED)
3567                 b43_wireless_core_stop(dev);
3568         if (prev_status >= B43_STAT_INITIALIZED)
3569                 b43_wireless_core_exit(dev);
3570
3571         /* ...and up again. */
3572         if (prev_status >= B43_STAT_INITIALIZED) {
3573                 err = b43_wireless_core_init(dev);
3574                 if (err)
3575                         goto out;
3576         }
3577         if (prev_status >= B43_STAT_STARTED) {
3578                 err = b43_wireless_core_start(dev);
3579                 if (err) {
3580                         b43_wireless_core_exit(dev);
3581                         goto out;
3582                 }
3583         }
3584       out:
3585         mutex_unlock(&wl->mutex);
3586         if (err)
3587                 b43err(wl, "Controller restart FAILED\n");
3588         else
3589                 b43info(wl, "Controller restarted\n");
3590 }
3591
3592 static int b43_setup_modes(struct b43_wldev *dev,
3593                            int have_aphy, int have_bphy, int have_gphy)
3594 {
3595         struct ieee80211_hw *hw = dev->wl->hw;
3596         struct ieee80211_hw_mode *mode;
3597         struct b43_phy *phy = &dev->phy;
3598         int cnt = 0;
3599         int err;
3600
3601 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3602         have_aphy = 0;
3603
3604         phy->possible_phymodes = 0;
3605         for (; 1; cnt++) {
3606                 if (have_aphy) {
3607                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3608                         mode = &phy->hwmodes[cnt];
3609
3610                         mode->mode = MODE_IEEE80211A;
3611                         mode->num_channels = b43_a_chantable_size;
3612                         mode->channels = b43_a_chantable;
3613                         mode->num_rates = b43_a_ratetable_size;
3614                         mode->rates = b43_a_ratetable;
3615                         err = ieee80211_register_hwmode(hw, mode);
3616                         if (err)
3617                                 return err;
3618
3619                         phy->possible_phymodes |= B43_PHYMODE_A;
3620                         have_aphy = 0;
3621                         continue;
3622                 }
3623                 if (have_bphy) {
3624                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3625                         mode = &phy->hwmodes[cnt];
3626
3627                         mode->mode = MODE_IEEE80211B;
3628                         mode->num_channels = b43_bg_chantable_size;
3629                         mode->channels = b43_bg_chantable;
3630                         mode->num_rates = b43_b_ratetable_size;
3631                         mode->rates = b43_b_ratetable;
3632                         err = ieee80211_register_hwmode(hw, mode);
3633                         if (err)
3634                                 return err;
3635
3636                         phy->possible_phymodes |= B43_PHYMODE_B;
3637                         have_bphy = 0;
3638                         continue;
3639                 }
3640                 if (have_gphy) {
3641                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3642                         mode = &phy->hwmodes[cnt];
3643
3644                         mode->mode = MODE_IEEE80211G;
3645                         mode->num_channels = b43_bg_chantable_size;
3646                         mode->channels = b43_bg_chantable;
3647                         mode->num_rates = b43_g_ratetable_size;
3648                         mode->rates = b43_g_ratetable;
3649                         err = ieee80211_register_hwmode(hw, mode);
3650                         if (err)
3651                                 return err;
3652
3653                         phy->possible_phymodes |= B43_PHYMODE_G;
3654                         have_gphy = 0;
3655                         continue;
3656                 }
3657                 break;
3658         }
3659
3660         return 0;
3661 }
3662
3663 static void b43_wireless_core_detach(struct b43_wldev *dev)
3664 {
3665         b43_rfkill_free(dev);
3666         /* We release firmware that late to not be required to re-request
3667          * is all the time when we reinit the core. */
3668         b43_release_firmware(dev);
3669 }
3670
3671 static int b43_wireless_core_attach(struct b43_wldev *dev)
3672 {
3673         struct b43_wl *wl = dev->wl;
3674         struct ssb_bus *bus = dev->dev->bus;
3675         struct pci_dev *pdev = bus->host_pci;
3676         int err;
3677         int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3678         u32 tmp;
3679
3680         /* Do NOT do any device initialization here.
3681          * Do it in wireless_core_init() instead.
3682          * This function is for gathering basic information about the HW, only.
3683          * Also some structs may be set up here. But most likely you want to have
3684          * that in core_init(), too.
3685          */
3686
3687         err = ssb_bus_powerup(bus, 0);
3688         if (err) {
3689                 b43err(wl, "Bus powerup failed\n");
3690                 goto out;
3691         }
3692         /* Get the PHY type. */
3693         if (dev->dev->id.revision >= 5) {
3694                 u32 tmshigh;
3695
3696                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3697                 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3698                 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3699                 if (!have_aphy && !have_gphy)
3700                         have_bphy = 1;
3701         } else if (dev->dev->id.revision == 4) {
3702                 have_gphy = 1;
3703                 have_aphy = 1;
3704         } else
3705                 have_bphy = 1;
3706
3707         dev->phy.gmode = (have_gphy || have_bphy);
3708         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3709         b43_wireless_core_reset(dev, tmp);
3710
3711         err = b43_phy_versioning(dev);
3712         if (err)
3713                 goto err_powerdown;
3714         /* Check if this device supports multiband. */
3715         if (!pdev ||
3716             (pdev->device != 0x4312 &&
3717              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3718                 /* No multiband support. */
3719                 have_aphy = 0;
3720                 have_bphy = 0;
3721                 have_gphy = 0;
3722                 switch (dev->phy.type) {
3723                 case B43_PHYTYPE_A:
3724                         have_aphy = 1;
3725                         break;
3726                 case B43_PHYTYPE_B:
3727                         have_bphy = 1;
3728                         break;
3729                 case B43_PHYTYPE_G:
3730                         have_gphy = 1;
3731                         break;
3732                 default:
3733                         B43_WARN_ON(1);
3734                 }
3735         }
3736         dev->phy.gmode = (have_gphy || have_bphy);
3737         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3738         b43_wireless_core_reset(dev, tmp);
3739
3740         err = b43_validate_chipaccess(dev);
3741         if (err)
3742                 goto err_powerdown;
3743         err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3744         if (err)
3745                 goto err_powerdown;
3746
3747         /* Now set some default "current_dev" */
3748         if (!wl->current_dev)
3749                 wl->current_dev = dev;
3750         INIT_WORK(&dev->restart_work, b43_chip_reset);
3751         b43_rfkill_alloc(dev);
3752
3753         b43_radio_turn_off(dev, 1);
3754         b43_switch_analog(dev, 0);
3755         ssb_device_disable(dev->dev, 0);
3756         ssb_bus_may_powerdown(bus);
3757
3758 out:
3759         return err;
3760
3761 err_powerdown:
3762         ssb_bus_may_powerdown(bus);
3763         return err;
3764 }
3765
3766 static void b43_one_core_detach(struct ssb_device *dev)
3767 {
3768         struct b43_wldev *wldev;
3769         struct b43_wl *wl;
3770
3771         wldev = ssb_get_drvdata(dev);
3772         wl = wldev->wl;
3773         cancel_work_sync(&wldev->restart_work);
3774         b43_debugfs_remove_device(wldev);
3775         b43_wireless_core_detach(wldev);
3776         list_del(&wldev->list);
3777         wl->nr_devs--;
3778         ssb_set_drvdata(dev, NULL);
3779         kfree(wldev);
3780 }
3781
3782 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3783 {
3784         struct b43_wldev *wldev;
3785         struct pci_dev *pdev;
3786         int err = -ENOMEM;
3787
3788         if (!list_empty(&wl->devlist)) {
3789                 /* We are not the first core on this chip. */
3790                 pdev = dev->bus->host_pci;
3791                 /* Only special chips support more than one wireless
3792                  * core, although some of the other chips have more than
3793                  * one wireless core as well. Check for this and
3794                  * bail out early.
3795                  */
3796                 if (!pdev ||
3797                     ((pdev->device != 0x4321) &&
3798                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3799                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3800                         return -ENODEV;
3801                 }
3802         }
3803
3804         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3805         if (!wldev)
3806                 goto out;
3807
3808         wldev->dev = dev;
3809         wldev->wl = wl;
3810         b43_set_status(wldev, B43_STAT_UNINIT);
3811         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3812         tasklet_init(&wldev->isr_tasklet,
3813                      (void (*)(unsigned long))b43_interrupt_tasklet,
3814                      (unsigned long)wldev);
3815         if (modparam_pio)
3816                 wldev->__using_pio = 1;
3817         INIT_LIST_HEAD(&wldev->list);
3818
3819         err = b43_wireless_core_attach(wldev);
3820         if (err)
3821                 goto err_kfree_wldev;
3822
3823         list_add(&wldev->list, &wl->devlist);
3824         wl->nr_devs++;
3825         ssb_set_drvdata(dev, wldev);
3826         b43_debugfs_add_device(wldev);
3827
3828       out:
3829         return err;
3830
3831       err_kfree_wldev:
3832         kfree(wldev);
3833         return err;
3834 }
3835
3836 static void b43_sprom_fixup(struct ssb_bus *bus)
3837 {
3838         /* boardflags workarounds */
3839         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3840             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3841                 bus->sprom.r1.boardflags_lo |= B43_BFL_BTCOEXIST;
3842         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3843             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3844                 bus->sprom.r1.boardflags_lo |= B43_BFL_PACTRL;
3845
3846         /* Handle case when gain is not set in sprom */
3847         if (bus->sprom.r1.antenna_gain_a == 0xFF)
3848                 bus->sprom.r1.antenna_gain_a = 2;
3849         if (bus->sprom.r1.antenna_gain_bg == 0xFF)
3850                 bus->sprom.r1.antenna_gain_bg = 2;
3851
3852         /* Convert Antennagain values to Q5.2 */
3853         bus->sprom.r1.antenna_gain_a <<= 2;
3854         bus->sprom.r1.antenna_gain_bg <<= 2;
3855 }
3856
3857 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3858 {
3859         struct ieee80211_hw *hw = wl->hw;
3860
3861         ssb_set_devtypedata(dev, NULL);
3862         ieee80211_free_hw(hw);
3863 }
3864
3865 static int b43_wireless_init(struct ssb_device *dev)
3866 {
3867         struct ssb_sprom *sprom = &dev->bus->sprom;
3868         struct ieee80211_hw *hw;
3869         struct b43_wl *wl;
3870         int err = -ENOMEM;
3871
3872         b43_sprom_fixup(dev->bus);
3873
3874         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3875         if (!hw) {
3876                 b43err(NULL, "Could not allocate ieee80211 device\n");
3877                 goto out;
3878         }
3879
3880         /* fill hw info */
3881         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
3882         hw->max_signal = 100;
3883         hw->max_rssi = -110;
3884         hw->max_noise = -110;
3885         hw->queues = 1;         /* FIXME: hardware has more queues */
3886         SET_IEEE80211_DEV(hw, dev->dev);
3887         if (is_valid_ether_addr(sprom->r1.et1mac))
3888                 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
3889         else
3890                 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
3891
3892         /* Get and initialize struct b43_wl */
3893         wl = hw_to_b43_wl(hw);
3894         memset(wl, 0, sizeof(*wl));
3895         wl->hw = hw;
3896         spin_lock_init(&wl->irq_lock);
3897         spin_lock_init(&wl->leds_lock);
3898         mutex_init(&wl->mutex);
3899         INIT_LIST_HEAD(&wl->devlist);
3900
3901         ssb_set_devtypedata(dev, wl);
3902         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3903         err = 0;
3904       out:
3905         return err;
3906 }
3907
3908 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3909 {
3910         struct b43_wl *wl;
3911         int err;
3912         int first = 0;
3913
3914         wl = ssb_get_devtypedata(dev);
3915         if (!wl) {
3916                 /* Probing the first core. Must setup common struct b43_wl */
3917                 first = 1;
3918                 err = b43_wireless_init(dev);
3919                 if (err)
3920                         goto out;
3921                 wl = ssb_get_devtypedata(dev);
3922                 B43_WARN_ON(!wl);
3923         }
3924         err = b43_one_core_attach(dev, wl);
3925         if (err)
3926                 goto err_wireless_exit;
3927
3928         if (first) {
3929                 err = ieee80211_register_hw(wl->hw);
3930                 if (err)
3931                         goto err_one_core_detach;
3932         }
3933
3934       out:
3935         return err;
3936
3937       err_one_core_detach:
3938         b43_one_core_detach(dev);
3939       err_wireless_exit:
3940         if (first)
3941                 b43_wireless_exit(dev, wl);
3942         return err;
3943 }
3944
3945 static void b43_remove(struct ssb_device *dev)
3946 {
3947         struct b43_wl *wl = ssb_get_devtypedata(dev);
3948         struct b43_wldev *wldev = ssb_get_drvdata(dev);
3949
3950         B43_WARN_ON(!wl);
3951         if (wl->current_dev == wldev)
3952                 ieee80211_unregister_hw(wl->hw);
3953
3954         b43_one_core_detach(dev);
3955
3956         if (list_empty(&wl->devlist)) {
3957                 /* Last core on the chip unregistered.
3958                  * We can destroy common struct b43_wl.
3959                  */
3960                 b43_wireless_exit(dev, wl);
3961         }
3962 }
3963
3964 /* Perform a hardware reset. This can be called from any context. */
3965 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
3966 {
3967         /* Must avoid requeueing, if we are in shutdown. */
3968         if (b43_status(dev) < B43_STAT_INITIALIZED)
3969                 return;
3970         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
3971         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3972 }
3973
3974 #ifdef CONFIG_PM
3975
3976 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
3977 {
3978         struct b43_wldev *wldev = ssb_get_drvdata(dev);
3979         struct b43_wl *wl = wldev->wl;
3980
3981         b43dbg(wl, "Suspending...\n");
3982
3983         mutex_lock(&wl->mutex);
3984         wldev->suspend_init_status = b43_status(wldev);
3985         if (wldev->suspend_init_status >= B43_STAT_STARTED)
3986                 b43_wireless_core_stop(wldev);
3987         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
3988                 b43_wireless_core_exit(wldev);
3989         mutex_unlock(&wl->mutex);
3990
3991         b43dbg(wl, "Device suspended.\n");
3992
3993         return 0;
3994 }
3995
3996 static int b43_resume(struct ssb_device *dev)
3997 {
3998         struct b43_wldev *wldev = ssb_get_drvdata(dev);
3999         struct b43_wl *wl = wldev->wl;
4000         int err = 0;
4001
4002         b43dbg(wl, "Resuming...\n");
4003
4004         mutex_lock(&wl->mutex);
4005         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4006                 err = b43_wireless_core_init(wldev);
4007                 if (err) {
4008                         b43err(wl, "Resume failed at core init\n");
4009                         goto out;
4010                 }
4011         }
4012         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4013                 err = b43_wireless_core_start(wldev);
4014                 if (err) {
4015                         b43_wireless_core_exit(wldev);
4016                         b43err(wl, "Resume failed at core start\n");
4017                         goto out;
4018                 }
4019         }
4020         mutex_unlock(&wl->mutex);
4021
4022         b43dbg(wl, "Device resumed.\n");
4023       out:
4024         return err;
4025 }
4026
4027 #else /* CONFIG_PM */
4028 # define b43_suspend    NULL
4029 # define b43_resume     NULL
4030 #endif /* CONFIG_PM */
4031
4032 static struct ssb_driver b43_ssb_driver = {
4033         .name           = KBUILD_MODNAME,
4034         .id_table       = b43_ssb_tbl,
4035         .probe          = b43_probe,
4036         .remove         = b43_remove,
4037         .suspend        = b43_suspend,
4038         .resume         = b43_resume,
4039 };
4040
4041 static int __init b43_init(void)
4042 {
4043         int err;
4044
4045         b43_debugfs_init();
4046         err = b43_pcmcia_init();
4047         if (err)
4048                 goto err_dfs_exit;
4049         err = ssb_driver_register(&b43_ssb_driver);
4050         if (err)
4051                 goto err_pcmcia_exit;
4052
4053         return err;
4054
4055 err_pcmcia_exit:
4056         b43_pcmcia_exit();
4057 err_dfs_exit:
4058         b43_debugfs_exit();
4059         return err;
4060 }
4061
4062 static void __exit b43_exit(void)
4063 {
4064         ssb_driver_unregister(&b43_ssb_driver);
4065         b43_pcmcia_exit();
4066         b43_debugfs_exit();
4067 }
4068
4069 module_init(b43_init)
4070 module_exit(b43_exit)