From a19b113fc05b46605f9ff57c2d15b047d6c392aa Mon Sep 17 00:00:00 2001 From: John Crispin Date: Fri, 3 Aug 2012 09:54:02 +0200 Subject: [PATCH 09/25] ethernet support --- drivers/net/ethernet/Kconfig | 18 ++ drivers/net/ethernet/Makefile | 3 + drivers/net/ethernet/lantiq_etop.c | 419 ++++++++++++++++++++++++++---------- net/ipv4/Kconfig | 7 + net/ipv4/Makefile | 1 + 5 files changed, 332 insertions(+), 116 deletions(-) diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index 3474a61..1d91eb6 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -85,6 +85,24 @@ config LANTIQ_ETOP ---help--- Support for the MII0 inside the Lantiq SoC +config LANTIQ_VRX200 + tristate "Lantiq SoC vrx200 driver" + depends on SOC_TYPE_XWAY + ---help--- + Support for the MII0 inside the Lantiq SoC + +config LANTIQ_SVIP_ETH + default y + tristate "Lantiq SoC SVIP Ethernet driver" + depends on SOC_SVIP + help + Support for the MII0 inside the Lantiq SVIP SoC + +config LANTIQ_SVIP_VIRTUAL_ETH + default y + tristate "Lantiq SoC SVIP Virtual Ethernet driver" + depends on SOC_SVIP + source "drivers/net/ethernet/marvell/Kconfig" source "drivers/net/ethernet/mellanox/Kconfig" source "drivers/net/ethernet/micrel/Kconfig" diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index 08d5f03..c8fb1b3 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -36,6 +36,9 @@ obj-$(CONFIG_IP1000) += icplus/ obj-$(CONFIG_JME) += jme.o obj-$(CONFIG_KORINA) += korina.o obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o +obj-$(CONFIG_LANTIQ_VRX200) += lantiq_vrx200.o +obj-$(CONFIG_LANTIQ_SVIP_ETH) += svip_eth.o +obj-$(CONFIG_LANTIQ_SVIP_VIRTUAL_ETH) += svip_virtual_eth.o obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c index 85e2c6c..97ddb09 100644 --- a/drivers/net/ethernet/lantiq_etop.c +++ b/drivers/net/ethernet/lantiq_etop.c @@ -36,6 +36,7 @@ #include #include #include +#include #include @@ -71,25 +72,55 @@ #define ETOP_MII_REVERSE 0xe #define ETOP_PLEN_UNDER 0x40 #define ETOP_CGEN 0x800 - -/* use 2 static channels for TX/RX */ -#define LTQ_ETOP_TX_CHANNEL 1 -#define LTQ_ETOP_RX_CHANNEL 6 -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) +#define ETOP_CFG_MII0 0x01 + +#define LTQ_GBIT_MDIO_CTL 0xCC +#define LTQ_GBIT_MDIO_DATA 0xd0 +#define LTQ_GBIT_GCTL0 0x68 +#define LTQ_GBIT_PMAC_HD_CTL 0x8c +#define LTQ_GBIT_P0_CTL 0x4 +#define LTQ_GBIT_PMAC_RX_IPG 0xa8 + +#define PMAC_HD_CTL_AS (1 << 19) +#define PMAC_HD_CTL_RXSH (1 << 22) + +/* Switch Enable (0=disable, 1=enable) */ +#define GCTL0_SE 0x80000000 +/* Disable MDIO auto polling (0=disable, 1=enable) */ +#define PX_CTL_DMDIO 0x00400000 + +/* register information for the gbit's MDIO bus */ +#define MDIO_XR9_REQUEST 0x00008000 +#define MDIO_XR9_READ 0x00000800 +#define MDIO_XR9_WRITE 0x00000400 +#define MDIO_XR9_REG_MASK 0x1f +#define MDIO_XR9_ADDR_MASK 0x1f +#define MDIO_XR9_RD_MASK 0xffff +#define MDIO_XR9_REG_OFFSET 0 +#define MDIO_XR9_ADDR_OFFSET 5 +#define MDIO_XR9_WR_OFFSET 16 + +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ +#define ltq_has_gbit() (ltq_is_ar9() || ltq_is_vr9()) #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) #define ltq_etop_w32_mask(x, y, z) \ ltq_w32_mask(x, y, ltq_etop_membase + (z)) +#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) +#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) +#define ltq_gbit_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_gbit_membase + (z)) + #define DRV_VERSION "1.0" static void __iomem *ltq_etop_membase; +static void __iomem *ltq_gbit_membase; struct ltq_etop_chan { - int idx; int tx_free; + int irq; struct net_device *netdev; struct napi_struct napi; struct ltq_dma_channel dma; @@ -105,12 +136,20 @@ struct ltq_etop_priv { struct mii_bus *mii_bus; struct phy_device *phydev; - struct ltq_etop_chan ch[MAX_DMA_CHAN]; - int tx_free[MAX_DMA_CHAN >> 1]; + struct ltq_etop_chan txch; + struct ltq_etop_chan rxch; spinlock_t lock; + + struct clk *clk_ppe; + struct clk *clk_switch; + struct clk *clk_ephy; + struct clk *clk_ephycgu; }; +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, + int phy_reg, u16 phy_data); + static int ltq_etop_alloc_skb(struct ltq_etop_chan *ch) { @@ -159,8 +198,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget) { struct ltq_etop_chan *ch = container_of(napi, struct ltq_etop_chan, napi); + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); int rx = 0; int complete = 0; + unsigned long flags; while ((rx < budget) && !complete) { struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; @@ -174,7 +215,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget) } if (complete || !rx) { napi_complete(&ch->napi); + spin_lock_irqsave(&priv->lock, flags); ltq_dma_ack_irq(&ch->dma); + spin_unlock_irqrestore(&priv->lock, flags); } return rx; } @@ -186,7 +229,7 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget) container_of(napi, struct ltq_etop_chan, napi); struct ltq_etop_priv *priv = netdev_priv(ch->netdev); struct netdev_queue *txq = - netdev_get_tx_queue(ch->netdev, ch->idx >> 1); + netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); unsigned long flags; spin_lock_irqsave(&priv->lock, flags); @@ -204,7 +247,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget) if (netif_tx_queue_stopped(txq)) netif_tx_start_queue(txq); napi_complete(&ch->napi); + spin_lock_irqsave(&priv->lock, flags); ltq_dma_ack_irq(&ch->dma); + spin_unlock_irqrestore(&priv->lock, flags); return 1; } @@ -212,9 +257,10 @@ static irqreturn_t ltq_etop_dma_irq(int irq, void *_priv) { struct ltq_etop_priv *priv = _priv; - int ch = irq - LTQ_DMA_CH0_INT; - - napi_schedule(&priv->ch[ch].napi); + if (irq == priv->txch.dma.irq) + napi_schedule(&priv->txch.napi); + else + napi_schedule(&priv->rxch.napi); return IRQ_HANDLED; } @@ -226,7 +272,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) ltq_dma_free(&ch->dma); if (ch->dma.irq) free_irq(ch->dma.irq, priv); - if (IS_RX(ch->idx)) { + if (ch == &priv->txch) { int desc; for (desc = 0; desc < LTQ_DESC_NUM; desc++) dev_kfree_skb_any(ch->skb[ch->dma.desc]); @@ -237,23 +283,56 @@ static void ltq_etop_hw_exit(struct net_device *dev) { struct ltq_etop_priv *priv = netdev_priv(dev); - int i; - ltq_pmu_disable(PMU_PPE); - for (i = 0; i < MAX_DMA_CHAN; i++) - if (IS_TX(i) || IS_RX(i)) - ltq_etop_free_channel(dev, &priv->ch[i]); + clk_disable(priv->clk_ppe); + + if (ltq_has_gbit()) + clk_disable(priv->clk_switch); + + if (ltq_is_ase()) { + clk_disable(priv->clk_ephy); + clk_disable(priv->clk_ephycgu); + } + + ltq_etop_free_channel(dev, &priv->txch); + ltq_etop_free_channel(dev, &priv->rxch); +} + +static void +ltq_etop_gbit_init(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + + clk_enable(priv->clk_switch); + + ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); + /** Disable MDIO auto polling mode */ + ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); + /* set 1522 packet size */ + ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); + /* disable pmac & dmac headers */ + ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, + LTQ_GBIT_PMAC_HD_CTL); + /* Due to traffic halt when burst length 8, + replace default IPG value with 0x3B */ + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); } static int ltq_etop_hw_init(struct net_device *dev) { struct ltq_etop_priv *priv = netdev_priv(dev); - int i; + unsigned int mii_mode = priv->pldata->mii_mode; - ltq_pmu_enable(PMU_PPE); + clk_enable(priv->clk_ppe); - switch (priv->pldata->mii_mode) { + if (ltq_has_gbit()) { + ltq_etop_gbit_init(dev); + /* force the etops link to the gbit to MII */ + mii_mode = PHY_INTERFACE_MODE_MII; + } + + switch (mii_mode) { case PHY_INTERFACE_MODE_RMII: ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE, LTQ_ETOP_CFG); @@ -265,6 +344,18 @@ ltq_etop_hw_init(struct net_device *dev) break; default: + if (ltq_is_ase()) { + clk_enable(priv->clk_ephy); + /* disable external MII */ + ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); + /* enable clock for internal PHY */ + clk_enable(priv->clk_ephycgu); + /* we need to write this magic to the internal phy to + make it work */ + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); + pr_info("Selected EPHY mode\n"); + break; + } netdev_err(dev, "unknown mii mode %d\n", priv->pldata->mii_mode); return -ENOTSUPP; @@ -273,31 +364,51 @@ ltq_etop_hw_init(struct net_device *dev) /* enable crc generation */ ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); + return 0; +} + +static int +ltq_etop_dma_init(struct net_device *dev) +{ + struct ltq_etop_priv *priv = netdev_priv(dev); + int tx = 1; + int rx = ((ltq_is_ase()) ? (5) : \ + ((ltq_is_ar9()) ? (0) : (6))); + int tx_irq = LTQ_DMA_ETOP + tx; + int rx_irq = LTQ_DMA_ETOP + rx; + int err; + ltq_dma_init_port(DMA_PORT_ETOP); - for (i = 0; i < MAX_DMA_CHAN; i++) { - int irq = LTQ_DMA_CH0_INT + i; - struct ltq_etop_chan *ch = &priv->ch[i]; - - ch->idx = ch->dma.nr = i; - - if (IS_TX(i)) { - ltq_dma_alloc_tx(&ch->dma); - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, - "etop_tx", priv); - } else if (IS_RX(i)) { - ltq_dma_alloc_rx(&ch->dma); - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; - ch->dma.desc++) - if (ltq_etop_alloc_skb(ch)) - return -ENOMEM; - ch->dma.desc = 0; - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, - "etop_rx", priv); + priv->txch.dma.nr = tx; + ltq_dma_alloc_tx(&priv->txch.dma); + err = request_irq(tx_irq, ltq_etop_dma_irq, IRQF_DISABLED, + "eth_tx", priv); + if (err) { + netdev_err(dev, "failed to allocate tx irq\n"); + goto err_out; + } + priv->txch.dma.irq = tx_irq; + + priv->rxch.dma.nr = rx; + ltq_dma_alloc_rx(&priv->rxch.dma); + for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; + priv->rxch.dma.desc++) { + if (ltq_etop_alloc_skb(&priv->rxch)) { + netdev_err(dev, "failed to allocate skbs\n"); + err = -ENOMEM; + goto err_out; } - ch->dma.irq = irq; } - return 0; + priv->rxch.dma.desc = 0; + err = request_irq(rx_irq, ltq_etop_dma_irq, IRQF_DISABLED, + "eth_rx", priv); + if (err) + netdev_err(dev, "failed to allocate rx irq\n"); + else + priv->rxch.dma.irq = rx_irq; +err_out: + return err; } static void @@ -313,7 +424,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { struct ltq_etop_priv *priv = netdev_priv(dev); - return phy_ethtool_gset(priv->phydev, cmd); + if (priv->phydev) + return phy_ethtool_gset(priv->phydev, cmd); + else + return 0; } static int @@ -321,7 +435,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) { struct ltq_etop_priv *priv = netdev_priv(dev); - return phy_ethtool_sset(priv->phydev, cmd); + if (priv->phydev) + return phy_ethtool_sset(priv->phydev, cmd); + else + return 0; } static int @@ -329,7 +446,10 @@ ltq_etop_nway_reset(struct net_device *dev) { struct ltq_etop_priv *priv = netdev_priv(dev); - return phy_start_aneg(priv->phydev); + if (priv->phydev) + return phy_start_aneg(priv->phydev); + else + return 0; } static const struct ethtool_ops ltq_etop_ethtool_ops = { @@ -340,6 +460,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = { }; static int +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, + int phy_reg, u16 phy_data) +{ + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | + (phy_data << MDIO_XR9_WR_OFFSET) | + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); + + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) + ; + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) + ; + return 0; +} + +static int +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) +{ + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); + + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) + ; + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) + ; + val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; + return val; +} + +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) { u32 val = MDIO_REQUEST | @@ -380,14 +533,11 @@ ltq_etop_mdio_probe(struct net_device *dev) { struct ltq_etop_priv *priv = netdev_priv(dev); struct phy_device *phydev = NULL; - int phy_addr; - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { - if (priv->mii_bus->phy_map[phy_addr]) { - phydev = priv->mii_bus->phy_map[phy_addr]; - break; - } - } + if (ltq_is_ase()) + phydev = priv->mii_bus->phy_map[8]; + else + phydev = priv->mii_bus->phy_map[0]; if (!phydev) { netdev_err(dev, "no PHY found\n"); @@ -409,6 +559,9 @@ ltq_etop_mdio_probe(struct net_device *dev) | SUPPORTED_Autoneg | SUPPORTED_MII | SUPPORTED_TP); + if (ltq_has_gbit()) + phydev->supported &= SUPPORTED_1000baseT_Half + | SUPPORTED_1000baseT_Full; phydev->advertising = phydev->supported; priv->phydev = phydev; @@ -434,8 +587,13 @@ ltq_etop_mdio_init(struct net_device *dev) } priv->mii_bus->priv = dev; - priv->mii_bus->read = ltq_etop_mdio_rd; - priv->mii_bus->write = ltq_etop_mdio_wr; + if (ltq_has_gbit()) { + priv->mii_bus->read = ltq_etop_mdio_rd_xr9; + priv->mii_bus->write = ltq_etop_mdio_wr_xr9; + } else { + priv->mii_bus->read = ltq_etop_mdio_rd; + priv->mii_bus->write = ltq_etop_mdio_wr; + } priv->mii_bus->name = "ltq_mii"; snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", priv->pdev->name, priv->pdev->id); @@ -484,17 +642,19 @@ static int ltq_etop_open(struct net_device *dev) { struct ltq_etop_priv *priv = netdev_priv(dev); - int i; + unsigned long flags; - for (i = 0; i < MAX_DMA_CHAN; i++) { - struct ltq_etop_chan *ch = &priv->ch[i]; + napi_enable(&priv->txch.napi); + napi_enable(&priv->rxch.napi); + + spin_lock_irqsave(&priv->lock, flags); + ltq_dma_open(&priv->txch.dma); + ltq_dma_open(&priv->rxch.dma); + spin_unlock_irqrestore(&priv->lock, flags); + + if (priv->phydev) + phy_start(priv->phydev); - if (!IS_TX(i) && (!IS_RX(i))) - continue; - ltq_dma_open(&ch->dma); - napi_enable(&ch->napi); - } - phy_start(priv->phydev); netif_tx_start_all_queues(dev); return 0; } @@ -503,18 +663,19 @@ static int ltq_etop_stop(struct net_device *dev) { struct ltq_etop_priv *priv = netdev_priv(dev); - int i; + unsigned long flags; netif_tx_stop_all_queues(dev); - phy_stop(priv->phydev); - for (i = 0; i < MAX_DMA_CHAN; i++) { - struct ltq_etop_chan *ch = &priv->ch[i]; + if (priv->phydev) + phy_stop(priv->phydev); + napi_disable(&priv->txch.napi); + napi_disable(&priv->rxch.napi); + + spin_lock_irqsave(&priv->lock, flags); + ltq_dma_close(&priv->txch.dma); + ltq_dma_close(&priv->rxch.dma); + spin_unlock_irqrestore(&priv->lock, flags); - if (!IS_RX(i) && !IS_TX(i)) - continue; - napi_disable(&ch->napi); - ltq_dma_close(&ch->dma); - } return 0; } @@ -524,16 +685,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) int queue = skb_get_queue_mapping(skb); struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); struct ltq_etop_priv *priv = netdev_priv(dev); - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; - int len; + struct ltq_dma_desc *desc = + &priv->txch.dma.desc_base[priv->txch.dma.desc]; unsigned long flags; u32 byte_offset; + int len; len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { - dev_kfree_skb_any(skb); + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || + priv->txch.skb[priv->txch.dma.desc]) { netdev_err(dev, "tx ring full\n"); netif_tx_stop_queue(txq); return NETDEV_TX_BUSY; @@ -541,7 +702,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) /* dma needs to start on a 16 byte aligned address */ byte_offset = CPHYSADDR(skb->data) % 16; - ch->skb[ch->dma.desc] = skb; + priv->txch.skb[priv->txch.dma.desc] = skb; dev->trans_start = jiffies; @@ -551,11 +712,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) wmb(); desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); - ch->dma.desc++; - ch->dma.desc %= LTQ_DESC_NUM; + priv->txch.dma.desc++; + priv->txch.dma.desc %= LTQ_DESC_NUM; spin_unlock_irqrestore(&priv->lock, flags); - if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) + if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) netif_tx_stop_queue(txq); return NETDEV_TX_OK; @@ -640,6 +801,10 @@ ltq_etop_init(struct net_device *dev) err = ltq_etop_hw_init(dev); if (err) goto err_hw; + err = ltq_etop_dma_init(dev); + if (err) + goto err_hw; + ltq_etop_change_mtu(dev, 1500); memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); @@ -652,9 +817,10 @@ ltq_etop_init(struct net_device *dev) if (err) goto err_netdev; ltq_etop_set_multicast_list(dev); - err = ltq_etop_mdio_init(dev); - if (err) - goto err_netdev; + if (!ltq_etop_mdio_init(dev)) + dev->ethtool_ops = <q_etop_ethtool_ops; + else + pr_warn("etop: mdio probe failed\n");; return 0; err_netdev: @@ -674,6 +840,9 @@ ltq_etop_tx_timeout(struct net_device *dev) err = ltq_etop_hw_init(dev); if (err) goto err_hw; + err = ltq_etop_dma_init(dev); + if (err) + goto err_hw; dev->trans_start = jiffies; netif_wake_queue(dev); return; @@ -697,14 +866,13 @@ static const struct net_device_ops ltq_eth_netdev_ops = { .ndo_tx_timeout = ltq_etop_tx_timeout, }; -static int __init +static int __devinit ltq_etop_probe(struct platform_device *pdev) { struct net_device *dev; struct ltq_etop_priv *priv; - struct resource *res; + struct resource *res, *gbit_res; int err; - int i; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { @@ -730,27 +898,62 @@ ltq_etop_probe(struct platform_device *pdev) goto err_out; } + if (ltq_has_gbit()) { + gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!gbit_res) { + dev_err(&pdev->dev, "failed to get gbit resource\n"); + err = -ENOENT; + goto err_out; + } + ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, + gbit_res->start, resource_size(gbit_res)); + if (!ltq_gbit_membase) { + dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", + pdev->id); + err = -ENOMEM; + goto err_out; + } + if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") || + ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) { + dev_err(&pdev->dev, "failed to request MDIO gpios\n"); + err = -EBUSY; + goto err_out; + } + } + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); strcpy(dev->name, "eth%d"); dev->netdev_ops = <q_eth_netdev_ops; - dev->ethtool_ops = <q_etop_ethtool_ops; priv = netdev_priv(dev); priv->res = res; priv->pdev = pdev; priv->pldata = dev_get_platdata(&pdev->dev); priv->netdev = dev; - spin_lock_init(&priv->lock); - for (i = 0; i < MAX_DMA_CHAN; i++) { - if (IS_TX(i)) - netif_napi_add(dev, &priv->ch[i].napi, - ltq_etop_poll_tx, 8); - else if (IS_RX(i)) - netif_napi_add(dev, &priv->ch[i].napi, - ltq_etop_poll_rx, 32); - priv->ch[i].netdev = dev; + priv->clk_ppe = clk_get(&pdev->dev, NULL); + if (IS_ERR(priv->clk_ppe)) + return PTR_ERR(priv->clk_ppe); + if (ltq_has_gbit()) { + priv->clk_switch = clk_get(&pdev->dev, "switch"); + if (IS_ERR(priv->clk_switch)) + return PTR_ERR(priv->clk_switch); + } + if (ltq_is_ase()) { + priv->clk_ephy = clk_get(&pdev->dev, "ephy"); + if (IS_ERR(priv->clk_ephy)) + return PTR_ERR(priv->clk_ephy); + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); + if (IS_ERR(priv->clk_ephycgu)) + return PTR_ERR(priv->clk_ephycgu); } + spin_lock_init(&priv->lock); + + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); + priv->txch.netdev = dev; + priv->rxch.netdev = dev; + err = register_netdev(dev); if (err) goto err_free; @@ -779,6 +982,7 @@ ltq_etop_remove(struct platform_device *pdev) } static struct platform_driver ltq_mii_driver = { + .probe = ltq_etop_probe, .remove = __devexit_p(ltq_etop_remove), .driver = { .name = "ltq_etop", @@ -786,24 +990,7 @@ static struct platform_driver ltq_mii_driver = { }, }; -int __init -init_ltq_etop(void) -{ - int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); - - if (ret) - pr_err("ltq_etop: Error registering platfom driver!"); - return ret; -} - -static void __exit -exit_ltq_etop(void) -{ - platform_driver_unregister(<q_mii_driver); -} - -module_init(init_ltq_etop); -module_exit(exit_ltq_etop); +module_platform_driver(ltq_mii_driver); MODULE_AUTHOR("John Crispin "); MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig index d183262..7d444e0 100644 --- a/net/ipv4/Kconfig +++ b/net/ipv4/Kconfig @@ -630,3 +630,10 @@ config TCP_MD5SIG on the Internet. If unsure, say N. + +config SVIP_NAT + bool "Include SVIP NAT" + depends on SOC_SVIP + default y + ---help--- + Include the SVIP NAT. diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile index ff75d3b..1d57fe0 100644 --- a/net/ipv4/Makefile +++ b/net/ipv4/Makefile @@ -53,3 +53,4 @@ obj-$(CONFIG_NETLABEL) += cipso_ipv4.o obj-$(CONFIG_XFRM) += xfrm4_policy.o xfrm4_state.o xfrm4_input.o \ xfrm4_output.o +obj-$(CONFIG_SVIP_NAT) += svip_nat.o -- 1.7.9.1