From 99f9c105d7d220028836ff94614e74ea7cbc7870 Mon Sep 17 00:00:00 2001 From: juhosg Date: Mon, 2 Sep 2013 16:09:12 +0000 Subject: ar71xx: configure OBS4 line on TL-WR841N-v8/MR3420v2 It also fixes USB Power on MR3420v2. This time we took the information from the source of GPL: http://www.mail-archive.com/openwrt-devel@lists.openwrt.org/msg18970.html Confirmed and tested: https://dev.openwrt.org/ticket/13201#comment:41 Thanks to oguretsagressive for testing. Signed-off-by: Dmytro git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37878 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c index e376ae5a42..6d2654b184 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v8.c @@ -132,8 +132,14 @@ static void __init tl_ap123_setup(void) u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); - /* Disable JTAG, enabling GPIOs 0-4 */ - ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE); + /* Disable JTAG, enabling GPIOs 0-3 */ + /* Configure OBS4 line, for GPIO 4*/ + ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, + AR934X_GPIO_FUNC_CLK_OBS4_EN); + + /* config gpio4 as normal gpio function */ + ath79_gpio_output_select(TL_MR3420V2_GPIO_USB_POWER, + AR934X_GPIO_OUT_GPIO); ath79_register_m25p80(&tl_wr841n_v8_flash_data); -- cgit v1.2.3