From 4cca99b95fc7be5f90a94b5b41b45c5c32360a38 Mon Sep 17 00:00:00 2001 From: jow Date: Tue, 7 Feb 2012 21:56:51 +0000 Subject: 8139cp: backport patches to make driver stable again List of patches that Jo-Philipp groveled out of git. Redux: defuzzed. Signed-off-by: Philip Prindeville git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30366 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../x86/patches-3.2/901-8139cp_eeprom_delay.patch | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 target/linux/x86/patches-3.2/901-8139cp_eeprom_delay.patch (limited to 'target/linux/x86/patches-3.2/901-8139cp_eeprom_delay.patch') diff --git a/target/linux/x86/patches-3.2/901-8139cp_eeprom_delay.patch b/target/linux/x86/patches-3.2/901-8139cp_eeprom_delay.patch new file mode 100644 index 0000000000..388755d266 --- /dev/null +++ b/target/linux/x86/patches-3.2/901-8139cp_eeprom_delay.patch @@ -0,0 +1,37 @@ +From 7d03f5a48e4d90854275b06433626243b3b3db17 Mon Sep 17 00:00:00 2001 +From: Jason Wang +Date: Fri, 30 Dec 2011 23:44:33 +0000 +Subject: [PATCH] 8139cp/8139too: do not read into reserved registers + +delay_eeprom() use long read for Cfg9346 register(offset 0x50) which may read +into the area of reserved register(offset 0x53). Use byte read instead. + +Signed-off-by: Jason Wang +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/realtek/8139cp.c | 2 +- + drivers/net/ethernet/realtek/8139too.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/realtek/8139cp.c ++++ b/drivers/net/ethernet/realtek/8139cp.c +@@ -1590,7 +1590,7 @@ static int cp_set_mac_address(struct net + No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. + */ + +-#define eeprom_delay() readl(ee_addr) ++#define eeprom_delay() readb(ee_addr) + + /* The EEPROM commands include the alway-set leading bit. */ + #define EE_EXTEND_CMD (4) +--- a/drivers/net/ethernet/realtek/8139too.c ++++ b/drivers/net/ethernet/realtek/8139too.c +@@ -1122,7 +1122,7 @@ static void __devexit rtl8139_remove_one + No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. + */ + +-#define eeprom_delay() (void)RTL_R32(Cfg9346) ++#define eeprom_delay() (void)RTL_R8(Cfg9346) + + /* The EEPROM commands include the alway-set leading bit. */ + #define EE_WRITE_CMD (5) -- cgit v1.2.3