From 9b11307b07431bac96f8c8e4367a3747942d5751 Mon Sep 17 00:00:00 2001 From: blogic Date: Sat, 2 Jun 2007 00:46:02 +0000 Subject: add initial support for the crisarchitecture used on foxboards to openwrt git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7439 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../etrax-2.6/image/e100boot/src/sbl/reg_des.h | 141 +++++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 target/linux/etrax-2.6/image/e100boot/src/sbl/reg_des.h (limited to 'target/linux/etrax-2.6/image/e100boot/src/sbl/reg_des.h') diff --git a/target/linux/etrax-2.6/image/e100boot/src/sbl/reg_des.h b/target/linux/etrax-2.6/image/e100boot/src/sbl/reg_des.h new file mode 100644 index 0000000000..dcc0133bc1 --- /dev/null +++ b/target/linux/etrax-2.6/image/e100boot/src/sbl/reg_des.h @@ -0,0 +1,141 @@ +struct reg_des { + char *name; + unsigned int addr; +} reg_des[] = { + { "R_WAITSTATES", 0xb0000000 }, + { "R_BUS_CONFIG", 0xb0000004 }, + { "R_BUS_STATUS", 0xb0000004 }, + { "R_DRAM_TIMING", 0xb0000008 }, + { "R_SDRAM_TIMING", 0xb0000008 }, + { "R_DRAM_CONFIG", 0xb000000c }, + { "R_SDRAM_CONFIG", 0xb000000c }, + { "R_EXT_DMA_0_CMD", 0xb0000010 }, + { "R_EXT_DMA_0_STAT", 0xb0000010 }, + { "R_EXT_DMA_0_ADDR", 0xb0000014 }, + { "R_EXT_DMA_1_CMD", 0xb0000018 }, + { "R_EXT_DMA_1_STAT", 0xb0000018 }, + { "R_EXT_DMA_1_ADDR", 0xb000001c }, + { "R_TIMER_CTRL", 0xb0000020 }, + { "R_TIMER_DATA", 0xb0000020 }, + { "R_WATCHDOG", 0xb0000024 }, + { "R_SHARED_RAM_CONFIG", 0xb0000040 }, + { "R_SHARED_RAM_ADDR", 0xb0000044 }, + { "R_GEN_CONFIG", 0xb000002c }, + { "R_PORT_G_DATA", 0xb0000028 }, + { "R_PORT_PA_SET", 0xb0000030 }, + { "R_PORT_PA_READ", 0xb0000030 }, + { "R_PORT_PB_SET", 0xb0000038 }, + { "R_PORT_PB_READ", 0xb0000038 }, + { "R_SERIAL0_CTRL", 0xb0000060 }, + { "R_SERIAL0_READ", 0xb0000060 }, + { "R_SERIAL0_XOFF", 0xb0000064 }, + { "R_SERIAL1_CTRL", 0xb0000068 }, + { "R_SERIAL1_READ", 0xb0000068 }, + { "R_SERIAL1_XOFF", 0xb000006c }, + { "R_SERIAL2_CTRL", 0xb0000070 }, + { "R_SERIAL2_READ", 0xb0000070 }, + { "R_SERIAL2_XOFF", 0xb0000074 }, + { "R_SERIAL3_CTRL", 0xb0000078 }, + { "R_SERIAL3_READ", 0xb0000078 }, + { "R_SERIAL3_XOFF", 0xb000007c }, + { "R_NETWORK_SA_0", 0xb0000080 }, + { "R_NETWORK_SA_1", 0xb0000084 }, + { "R_NETWORK_SA_2", 0xb0000088 }, + { "R_NETWORK_GA_0", 0xb000008c }, + { "R_NETWORK_GA_1", 0xb0000090 }, + { "R_NETWORK_REC_CONFIG", 0xb0000094 }, + { "R_NETWORK_GEN_CONFIG", 0xb0000098 }, + { "R_NETWORK_TR_CTRL", 0xb000009c }, + { "R_NETWORK_MGM_CTRL", 0xb00000a0 }, + { "R_NETWORK_STAT", 0xb00000a0 }, + { "R_REC_COUNTERS", 0xb00000a4 }, + { "R_TR_COUNTERS", 0xb00000a8 }, + { "R_PHY_COUNTERS", 0xb00000ac }, + { "R_PAR0_CTRL_DATA", 0xb0000040 }, + { "R_PAR0_STATUS_DATA", 0xb0000040 }, + { "R_PAR0_CONFIG", 0xb0000044 }, + { "R_PAR0_DELAY", 0xb0000048 }, + { "R_PAR1_CTRL_DATA", 0xb0000050 }, + { "R_PAR1_STATUS_DATA", 0xb0000050 }, + { "R_PAR1_CONFIG", 0xb0000054 }, + { "R_PAR1_DELAY", 0xb0000058 }, + { "R_ATA_CTRL_DATA", 0xb0000040 }, + { "R_ATA_STATUS_DATA", 0xb0000040 }, + { "R_ATA_CONFIG", 0xb0000044 }, + { "R_ATA_TRANSFER_CNT", 0xb0000048 }, + { "R_SCSI0_CTRL", 0xb0000044 }, + { "R_SCSI0_CMD_DATA", 0xb0000040 }, + { "R_SCSI0_STATUS", 0xb0000048 }, + { "R_SCSI1_CTRL", 0xb0000054 }, + { "R_SCSI1_CMD_DATA", 0xb0000050 }, + { "R_SCSI1_STATUS", 0xb0000058 }, + { "R_IRQ_MASK0_RD", 0xb00000c0 }, + { "R_IRQ_MASK0_CLR", 0xb00000c0 }, + { "R_IRQ_READ0", 0xb00000c4 }, + { "R_IRQ_MASK0_SET", 0xb00000c4 }, + { "R_IRQ_MASK1_RD", 0xb00000c8 }, + { "R_IRQ_MASK1_CLR", 0xb00000c8 }, + { "R_IRQ_READ1", 0xb00000cc }, + { "R_IRQ_MASK1_SET", 0xb00000cc }, + { "R_IRQ_MASK2_RD", 0xb00000d0 }, + { "R_IRQ_MASK2_CLR", 0xb00000d0 }, + { "R_IRQ_READ2", 0xb00000d4 }, + { "R_IRQ_MASK2_SET", 0xb00000d4 }, + { "R_VECT_MASK_RD", 0xb00000d8 }, + { "R_VECT_MASK_CLR", 0xb00000d8 }, + { "R_VECT_READ", 0xb00000dc }, + { "R_VECT_MASK_SET", 0xb00000dc }, + { "R_SET_EOP", 0xb000003c }, + { "R_DMA_CH0_HWSW", 0xb0000100 }, + { "R_DMA_CH0_DESCR", 0xb000010c }, + { "R_DMA_CH0_NEXT", 0xb0000104 }, + { "R_DMA_CH0_BUF", 0xb0000108 }, + { "R_DMA_CH0_FIRST", 0xb00001a0 }, + { "R_DMA_CH1_HWSW", 0xb0000110 }, + { "R_DMA_CH1_DESCR", 0xb000011c }, + { "R_DMA_CH1_NEXT", 0xb0000114 }, + { "R_DMA_CH1_BUF", 0xb0000118 }, + { "R_DMA_CH1_FIRST", 0xb00001a4 }, + { "R_DMA_CH2_HWSW", 0xb0000120 }, + { "R_DMA_CH2_DESCR", 0xb000012c }, + { "R_DMA_CH2_NEXT", 0xb0000124 }, + { "R_DMA_CH2_BUF", 0xb0000128 }, + { "R_DMA_CH2_FIRST", 0xb00001a8 }, + { "R_DMA_CH3_HWSW", 0xb0000130 }, + { "R_DMA_CH3_DESCR", 0xb000013c }, + { "R_DMA_CH3_NEXT", 0xb0000134 }, + { "R_DMA_CH3_BUF", 0xb0000138 }, + { "R_DMA_CH3_FIRST", 0xb00001ac }, + { "R_DMA_CH4_HWSW", 0xb0000140 }, + { "R_DMA_CH4_DESCR", 0xb000014c }, + { "R_DMA_CH4_NEXT", 0xb0000144 }, + { "R_DMA_CH4_BUF", 0xb0000148 }, + { "R_DMA_CH4_FIRST", 0xb00001b0 }, + { "R_DMA_CH5_HWSW", 0xb0000150 }, + { "R_DMA_CH5_DESCR", 0xb000015c }, + { "R_DMA_CH5_NEXT", 0xb0000154 }, + { "R_DMA_CH5_BUF", 0xb0000158 }, + { "R_DMA_CH5_FIRST", 0xb00001b4 }, + { "R_DMA_CH6_HWSW", 0xb0000160 }, + { "R_DMA_CH6_DESCR", 0xb000016c }, + { "R_DMA_CH6_NEXT", 0xb0000164 }, + { "R_DMA_CH6_BUF", 0xb0000168 }, + { "R_DMA_CH6_FIRST", 0xb00001b8 }, + { "R_DMA_CH7_HWSW", 0xb0000170 }, + { "R_DMA_CH7_DESCR", 0xb000017c }, + { "R_DMA_CH7_NEXT", 0xb0000174 }, + { "R_DMA_CH7_BUF", 0xb0000178 }, + { "R_DMA_CH7_FIRST", 0xb00001bc }, + { "R_DMA_CH8_HWSW", 0xb0000180 }, + { "R_DMA_CH8_DESCR", 0xb000018c }, + { "R_DMA_CH8_NEXT", 0xb0000184 }, + { "R_DMA_CH8_BUF", 0xb0000188 }, + { "R_DMA_CH8_FIRST", 0xb00001c0 }, + { "R_DMA_CH9_HWSW", 0xb0000190 }, + { "R_DMA_CH9_DESCR", 0xb000019c }, + { "R_DMA_CH9_NEXT", 0xb0000194 }, + { "R_DMA_CH9_BUF", 0xb0000198 }, + { "R_DMA_CH9_FIRST", 0xb00001c4 }, + { "R_TEST_MODE", 0xb00000fc }, + { NULL, 0 } +}; -- cgit v1.2.3