From a8293d35f81e24aea9cec55f13b8abf5bd28bff0 Mon Sep 17 00:00:00 2001 From: nbd Date: Mon, 12 Aug 2013 17:26:03 +0000 Subject: ar71xx: ethernet: reduce tx and rx DMA ring size to improve cache footprint 256 entries is a bit excessive, even for gigabit speeds Signed-off-by: Felix Fietkau git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37762 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target/linux/ar71xx/files') diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h index 6d51e722b0..83607b38bf 100644 --- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h +++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h @@ -58,8 +58,8 @@ #define AG71XX_TX_RING_SIZE_DEFAULT 64 #define AG71XX_RX_RING_SIZE_DEFAULT 128 -#define AG71XX_TX_RING_SIZE_MAX 256 -#define AG71XX_RX_RING_SIZE_MAX 256 +#define AG71XX_TX_RING_SIZE_MAX 128 +#define AG71XX_RX_RING_SIZE_MAX 128 #ifdef CONFIG_AG71XX_DEBUG #define DBG(fmt, args...) pr_debug(fmt, ## args) -- cgit v1.2.3