X-Git-Url: https://git.enpas.org/?a=blobdiff_plain;f=target%2Flinux%2Fimx6%2Fpatches-3.10%2F110-gw5400-a.patch;h=ddb796c3973fe2c36985d86d38e2dedc1507da1a;hb=693dae95f763467e009af16c19aed08bf897c2b0;hp=ac0721d925baa57e746726c7e5619cd75e88bb36;hpb=ca415bb17643239f67221ece170d26e9682e61ff;p=openwrt.git

diff --git a/target/linux/imx6/patches-3.10/110-gw5400-a.patch b/target/linux/imx6/patches-3.10/110-gw5400-a.patch
index ac0721d925..ddb796c397 100644
--- a/target/linux/imx6/patches-3.10/110-gw5400-a.patch
+++ b/target/linux/imx6/patches-3.10/110-gw5400-a.patch
@@ -25,7 +25,38 @@
  				};
  
  				ecspi1 {
-@@ -205,6 +213,12 @@
+@@ -187,6 +195,30 @@
+ 							MX6Q_PAD_SD4_DAT0__NAND_DQS      0x00b1
+ 						>;
+ 					};
++
++					/* No strobe */
++					pinctrl_gpmi_nand_2: gpmi-nand-2 {
++						fsl,pins = <
++							MX6Q_PAD_NANDF_CLE__NAND_CLE     0xb0b1
++							MX6Q_PAD_NANDF_ALE__NAND_ALE     0xb0b1
++							MX6Q_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
++							MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
++							MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
++							MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
++							MX6Q_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
++							MX6Q_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
++							MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
++							MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
++							MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
++							MX6Q_PAD_NANDF_D1__NAND_DATA01   0xb0b1
++							MX6Q_PAD_NANDF_D2__NAND_DATA02   0xb0b1
++							MX6Q_PAD_NANDF_D3__NAND_DATA03   0xb0b1
++							MX6Q_PAD_NANDF_D4__NAND_DATA04   0xb0b1
++							MX6Q_PAD_NANDF_D5__NAND_DATA05   0xb0b1
++							MX6Q_PAD_NANDF_D6__NAND_DATA06   0xb0b1
++							MX6Q_PAD_NANDF_D7__NAND_DATA07   0xb0b1
++						>;
++					};
+ 				};
+ 
+ 				i2c1 {
+@@ -205,6 +237,12 @@
  							MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
  						>;
  					};
@@ -38,7 +69,7 @@
  				};
  
  				i2c3 {
-@@ -214,6 +228,12 @@
+@@ -214,6 +252,12 @@
  							MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
  						>;
  					};
@@ -51,7 +82,7 @@
  				};
  
  				uart1 {
-@@ -223,6 +243,12 @@
+@@ -223,6 +267,12 @@
  							MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
  						>;
  					};
@@ -64,7 +95,7 @@
  				};
  
  				uart2 {
-@@ -232,6 +258,21 @@
+@@ -232,6 +282,21 @@
  							MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
  						>;
  					};
@@ -86,7 +117,7 @@
  				};
  
  				uart4 {
-@@ -242,6 +283,15 @@
+@@ -242,6 +307,15 @@
  						>;
  					};
  				};
@@ -102,89 +133,3 @@
  
  				usbotg {
  					pinctrl_usbotg_1: usbotggrp-1 {
---- a/arch/arm/mach-imx/mach-imx6q.c
-+++ b/arch/arm/mach-imx/mach-imx6q.c
-@@ -25,6 +25,7 @@
- #include <linux/of_irq.h>
- #include <linux/of_platform.h>
- #include <linux/opp.h>
-+#include <linux/pci.h>
- #include <linux/phy.h>
- #include <linux/regmap.h>
- #include <linux/micrel_phy.h>
-@@ -145,6 +146,65 @@ static void __init imx6q_sabrelite_init(
- 	imx6q_sabrelite_cko1_setup();
- }
- 
-+/*
-+ * fixup for PEX 8909 bridge to configure GPIO1-7 as output High
-+ * as they are used for slots1-7 PERST#
-+ */
-+static void mx6_ventana_pciesw_early_fixup(struct pci_dev *dev)
-+{
-+	u32 dw;
-+
-+	if (!of_machine_is_compatible("gw,ventana"))
-+		return;
-+
-+	if (dev->devfn != 0)
-+		return;
-+
-+	pci_read_config_dword(dev, 0x62c, &dw);
-+	dw |= 0xaaa8; // GPIO1-7 outputs
-+	pci_write_config_dword(dev, 0x62c, dw);
-+
-+	pci_read_config_dword(dev, 0x644, &dw);
-+	dw |= 0xfe;   // GPIO1-7 output high
-+	pci_write_config_dword(dev, 0x644, dw);
-+}
-+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609,
-+	mx6_ventana_pciesw_early_fixup);
-+
-+/*
-+ * configure PCIe core clock and PCIe ref clock
-+ *
-+ * TODO: disable CLK1 output and use CLK2 input from si52147 as PCIe ref
-+ */
-+static void __init imx6q_ventana_pcie_setup(void)
-+{
-+	struct clk *axi_sel, *axi, *ref;
-+
-+	axi_sel = clk_get_sys(NULL, "pcie_axi_sel");
-+	axi = clk_get_sys(NULL, "axi");
-+	ref = clk_get_sys(NULL, "pcie_ref_125m");
-+	if (IS_ERR(axi_sel) || IS_ERR(axi) || IS_ERR(ref)) {
-+		pr_err("pcie setup failed - can't get clocks\n");
-+		goto put_clk;
-+	}
-+	clk_set_parent(axi_sel, axi);
-+	clk_prepare_enable(ref);
-+
-+put_clk:
-+	if (!IS_ERR(axi_sel))
-+		clk_put(axi_sel);
-+	if (!IS_ERR(axi))
-+		clk_put(axi);
-+	if (!IS_ERR(ref))
-+		clk_put(ref);
-+}
-+
-+static void __init imx6q_ventana_init(void)
-+{
-+	imx6q_ventana_pcie_setup();
-+	imx6q_sabrelite_cko1_setup();
-+}
-+
- static void __init imx6q_1588_init(void)
- {
- 	struct regmap *gpr;
-@@ -163,6 +223,9 @@ static void __init imx6q_usb_init(void)
- 
- static void __init imx6q_init_machine(void)
- {
-+	if (of_machine_is_compatible("gw,ventana"))
-+		imx6q_ventana_init();
-+
- 	if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
- 		imx6q_sabrelite_init();
-