1 From cb6050998de262d5acf2207c5451d4f5995a5bff Mon Sep 17 00:00:00 2001
2 From: Chen-Yu Tsai <wens@csie.org>
3 Date: Mon, 3 Feb 2014 09:51:44 +0800
4 Subject: [PATCH] ARM: dts: sun7i: rename clock node names to clk@N
6 Device tree naming conventions state that node names should match
7 node function. Change fully functioning clock nodes to match and
8 add clock-output-names to all sunxi clock nodes.
10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
13 arch/arm/boot/dts/sun7i-a20.dtsi | 25 +++++++++++++++++--------
14 1 file changed, 17 insertions(+), 8 deletions(-)
16 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
17 index fe0fe47..cefd7ac 100644
18 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
19 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
24 - osc24M: osc24M@01c20050 {
25 + osc24M: clk@01c20050 {
27 compatible = "allwinner,sun4i-osc-clk";
28 reg = <0x01c20050 0x4>;
29 clock-frequency = <24000000>;
30 + clock-output-names = "osc24M";
35 clock-output-names = "osc32k";
38 - pll1: pll1@01c20000 {
39 + pll1: clk@01c20000 {
41 compatible = "allwinner,sun4i-pll1-clk";
42 reg = <0x01c20000 0x4>;
44 + clock-output-names = "pll1";
47 - pll4: pll4@01c20018 {
48 + pll4: clk@01c20018 {
50 compatible = "allwinner,sun4i-pll1-clk";
51 reg = <0x01c20018 0x4>;
53 + clock-output-names = "pll4";
56 - pll5: pll5@01c20020 {
57 + pll5: clk@01c20020 {
59 compatible = "allwinner,sun4i-pll5-clk";
60 reg = <0x01c20020 0x4>;
62 clock-output-names = "pll5_ddr", "pll5_other";
65 - pll6: pll6@01c20028 {
66 + pll6: clk@01c20028 {
68 compatible = "allwinner,sun4i-pll6-clk";
69 reg = <0x01c20028 0x4>;
71 compatible = "allwinner,sun4i-cpu-clk";
72 reg = <0x01c20054 0x4>;
73 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
74 + clock-output-names = "cpu";
79 compatible = "allwinner,sun4i-axi-clk";
80 reg = <0x01c20054 0x4>;
82 + clock-output-names = "axi";
87 compatible = "allwinner,sun4i-ahb-clk";
88 reg = <0x01c20054 0x4>;
90 + clock-output-names = "ahb";
93 - ahb_gates: ahb_gates@01c20060 {
94 + ahb_gates: clk@01c20060 {
96 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
97 reg = <0x01c20060 0x8>;
99 compatible = "allwinner,sun4i-apb0-clk";
100 reg = <0x01c20054 0x4>;
102 + clock-output-names = "apb0";
105 - apb0_gates: apb0_gates@01c20068 {
106 + apb0_gates: clk@01c20068 {
108 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
109 reg = <0x01c20068 0x4>;
111 compatible = "allwinner,sun4i-apb1-mux-clk";
112 reg = <0x01c20058 0x4>;
113 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
114 + clock-output-names = "apb1_mux";
117 apb1: apb1@01c20058 {
119 compatible = "allwinner,sun4i-apb1-clk";
120 reg = <0x01c20058 0x4>;
121 clocks = <&apb1_mux>;
122 + clock-output-names = "apb1";
125 - apb1_gates: apb1_gates@01c2006c {
126 + apb1_gates: clk@01c2006c {
128 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
129 reg = <0x01c2006c 0x4>;