1 From 6f5002c91f35f6b171bc608b87b3f2b55451f32b Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
3 Date: Sun, 3 Nov 2013 10:30:13 +0100
4 Subject: [PATCH] ARM: sun6i: Add SMP support for the Allwinner A31
6 The A31 is a quad Cortex-A7. Add the logic to use the IPs used to
7 control the CPU configuration and the CPU power so that we can bring up
8 secondary CPUs at boot.
10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
12 arch/arm/mach-sunxi/Makefile | 1 +
13 arch/arm/mach-sunxi/common.h | 19 +++++++
14 arch/arm/mach-sunxi/headsmp.S | 9 +++
15 arch/arm/mach-sunxi/platsmp.c | 124 ++++++++++++++++++++++++++++++++++++++++++
16 arch/arm/mach-sunxi/sunxi.c | 3 +
17 5 files changed, 156 insertions(+)
18 create mode 100644 arch/arm/mach-sunxi/common.h
19 create mode 100644 arch/arm/mach-sunxi/headsmp.S
20 create mode 100644 arch/arm/mach-sunxi/platsmp.c
22 --- a/arch/arm/mach-sunxi/Makefile
23 +++ b/arch/arm/mach-sunxi/Makefile
25 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
26 +obj-$(CONFIG_SMP) += platsmp.o headsmp.o
28 +++ b/arch/arm/mach-sunxi/common.h
31 + * Core functions for Allwinner SoCs
33 + * Copyright (C) 2013 Maxime Ripard
35 + * Maxime Ripard <maxime.ripard@free-electrons.com>
37 + * This file is licensed under the terms of the GNU General Public
38 + * License version 2. This program is licensed "as is" without any
39 + * warranty of any kind, whether express or implied.
42 +#ifndef __ARCH_SUNXI_COMMON_H_
43 +#define __ARCH_SUNXI_COMMON_H_
45 +void sun6i_secondary_startup(void);
46 +extern struct smp_operations sun6i_smp_ops;
48 +#endif /* __ARCH_SUNXI_COMMON_H_ */
50 +++ b/arch/arm/mach-sunxi/headsmp.S
52 +#include <linux/linkage.h>
53 +#include <linux/init.h>
55 + .section ".text.head", "ax"
57 +ENTRY(sun6i_secondary_startup)
58 + msr cpsr_fsxc, #0xd3
60 +ENDPROC(sun6i_secondary_startup)
62 +++ b/arch/arm/mach-sunxi/platsmp.c
65 + * SMP support for Allwinner SoCs
67 + * Copyright (C) 2013 Maxime Ripard
69 + * Maxime Ripard <maxime.ripard@free-electrons.com>
72 + * Copyright (C) 2012-2013 Allwinner Ltd.
74 + * This file is licensed under the terms of the GNU General Public
75 + * License version 2. This program is licensed "as is" without any
76 + * warranty of any kind, whether express or implied.
79 +#include <linux/delay.h>
80 +#include <linux/init.h>
81 +#include <linux/io.h>
82 +#include <linux/memory.h>
83 +#include <linux/of.h>
84 +#include <linux/of_address.h>
85 +#include <linux/smp.h>
89 +#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu) ((cpu) * 0x40 + 0x64)
90 +#define CPUCFG_CPU_RST_CTRL_REG(cpu) (((cpu) + 1) * 0x40)
91 +#define CPUCFG_CPU_CTRL_REG(cpu) (((cpu) + 1) * 0x40 + 0x04)
92 +#define CPUCFG_CPU_STATUS_REG(cpu) (((cpu) + 1) * 0x40 + 0x08)
93 +#define CPUCFG_GEN_CTRL_REG 0x184
94 +#define CPUCFG_PRIVATE0_REG 0x1a4
95 +#define CPUCFG_PRIVATE1_REG 0x1a8
96 +#define CPUCFG_DBG_CTL0_REG 0x1e0
97 +#define CPUCFG_DBG_CTL1_REG 0x1e4
99 +#define PRCM_CPU_PWROFF_REG 0x100
100 +#define PRCM_CPU_PWR_CLAMP_REG(cpu) (((cpu) * 4) + 0x140)
102 +static void __iomem *cpucfg_membase;
103 +static void __iomem *prcm_membase;
105 +static DEFINE_SPINLOCK(cpu_lock);
107 +static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
109 + struct device_node *node;
111 + node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
113 + pr_err("Missing A31 PRCM node in the device tree\n");
117 + prcm_membase = of_iomap(node, 0);
118 + if (!prcm_membase) {
119 + pr_err("Couldn't map A31 PRCM registers\n");
123 + node = of_find_compatible_node(NULL, NULL,
124 + "allwinner,sun6i-a31-cpuconfig");
126 + pr_err("Missing A31 CPU config node in the device tree\n");
130 + cpucfg_membase = of_iomap(node, 0);
131 + if (!cpucfg_membase)
132 + pr_err("Couldn't map A31 CPU config registers\n");
136 +static int sun6i_smp_boot_secondary(unsigned int cpu,
137 + struct task_struct *idle)
142 + if (!(prcm_membase && cpucfg_membase))
145 + spin_lock(&cpu_lock);
147 + /* Set CPU boot address */
148 + writel(virt_to_phys(sun6i_secondary_startup),
149 + cpucfg_membase + CPUCFG_PRIVATE0_REG);
151 + /* Assert the CPU core in reset */
152 + writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
154 + /* Assert the L1 cache in reset */
155 + reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
156 + writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
158 + /* Disable external debug access */
159 + reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
160 + writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
162 + /* Power up the CPU */
163 + for (i = 0; i <= 8; i++)
164 + writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
167 + /* Clear CPU power-off gating */
168 + reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
169 + writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
172 + /* Deassert the CPU core reset */
173 + writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
175 + /* Enable back the external debug accesses */
176 + reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
177 + writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
179 + spin_unlock(&cpu_lock);
184 +struct smp_operations sun6i_smp_ops __initdata = {
185 + .smp_prepare_cpus = sun6i_smp_prepare_cpus,
186 + .smp_boot_secondary = sun6i_smp_boot_secondary,
188 --- a/arch/arm/mach-sunxi/sunxi.c
189 +++ b/arch/arm/mach-sunxi/sunxi.c
191 #include <asm/mach/map.h>
192 #include <asm/system_misc.h>
196 #define SUN4I_WATCHDOG_CTRL_REG 0x00
197 #define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
198 #define SUN4I_WATCHDOG_MODE_REG 0x04
199 @@ -147,6 +149,7 @@ DT_MACHINE_START(SUN6I_DT, "Allwinner su
200 .init_time = sun6i_timer_init,
201 .dt_compat = sun6i_board_dt_compat,
202 .restart = sun6i_restart,
203 + .smp = smp_ops(sun6i_smp_ops),
206 static const char * const sun7i_board_dt_compat[] = {