1 From f22c157f44c93d61058d2e2aa5626ee2899fde5a Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 22 Jan 2013 18:24:34 +0100
4 Subject: [PATCH 114/121] GPIO: MIPS: ralink: adds ralink gpio support
6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/Kconfig | 1 +
12 arch/mips/include/asm/mach-ralink/gpio.h | 24 ++++
13 drivers/gpio/Kconfig | 6 +
14 drivers/gpio/Makefile | 1 +
15 drivers/gpio/gpio-ralink.c | 176 ++++++++++++++++++++++++++++++
16 5 files changed, 208 insertions(+)
17 create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
18 create mode 100644 drivers/gpio/gpio-ralink.c
20 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
21 index 490d769..1db6ce9 100644
22 --- a/arch/mips/Kconfig
23 +++ b/arch/mips/Kconfig
24 @@ -443,6 +443,7 @@ config RALINK
25 select SYS_HAS_EARLY_PRINTK
26 select HAVE_MACH_CLKDEV
28 + select ARCH_REQUIRE_GPIOLIB
31 bool "SGI IP22 (Indy/Indigo2)"
32 diff --git a/arch/mips/include/asm/mach-ralink/gpio.h b/arch/mips/include/asm/mach-ralink/gpio.h
34 index 0000000..f68ee16
36 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
39 + * Ralink SoC GPIO API support
41 + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
42 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
44 + * This program is free software; you can redistribute it and/or modify it
45 + * under the terms of the GNU General Public License version 2 as published
46 + * by the Free Software Foundation.
50 +#ifndef __ASM_MACH_RALINK_GPIO_H
51 +#define __ASM_MACH_RALINK_GPIO_H
53 +#define ARCH_NR_GPIOS 128
54 +#include <asm-generic/gpio.h>
56 +#define gpio_get_value __gpio_get_value
57 +#define gpio_set_value __gpio_set_value
58 +#define gpio_cansleep __gpio_cansleep
59 +#define gpio_to_irq __gpio_to_irq
61 +#endif /* __ASM_MACH_RALINK_GPIO_H */
62 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
63 index 93aaadf..29add97 100644
64 --- a/drivers/gpio/Kconfig
65 +++ b/drivers/gpio/Kconfig
66 @@ -204,6 +204,12 @@ config GPIO_PXA
68 Say yes here to support the PXA GPIO device
71 + bool "Ralink GPIO Support"
74 + Say yes here to support the Ralink SoC GPIO device
76 config GPIO_SPEAR_SPICS
77 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
79 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
80 index 22e07bc..f7b6603 100644
81 --- a/drivers/gpio/Makefile
82 +++ b/drivers/gpio/Makefile
83 @@ -55,6 +55,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
84 obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
85 obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
86 obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
87 +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
88 obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
89 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
90 obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
91 diff --git a/drivers/gpio/gpio-ralink.c b/drivers/gpio/gpio-ralink.c
93 index 0000000..26e8441
95 +++ b/drivers/gpio/gpio-ralink.c
98 + * This program is free software; you can redistribute it and/or modify it
99 + * under the terms of the GNU General Public License version 2 as published
100 + * by the Free Software Foundation.
102 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
103 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
106 +#include <linux/module.h>
107 +#include <linux/io.h>
108 +#include <linux/gpio.h>
109 +#include <linux/spinlock.h>
110 +#include <linux/platform_device.h>
112 +enum ralink_gpio_reg {
126 +struct ralink_gpio_chip {
127 + struct gpio_chip chip;
128 + u8 regs[GPIO_REG_MAX];
131 + void __iomem *membase;
134 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
136 + struct ralink_gpio_chip *rg;
138 + rg = container_of(chip, struct ralink_gpio_chip, chip);
142 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
144 + iowrite32(val, rg->membase + rg->regs[reg]);
147 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
149 + return ioread32(rg->membase + rg->regs[reg]);
152 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
154 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
156 + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
159 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
161 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
163 + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
166 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
168 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
169 + unsigned long flags;
172 + spin_lock_irqsave(&rg->lock, flags);
173 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
175 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
176 + spin_unlock_irqrestore(&rg->lock, flags);
181 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
182 + unsigned offset, int value)
184 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
185 + unsigned long flags;
188 + spin_lock_irqsave(&rg->lock, flags);
189 + ralink_gpio_set(chip, offset, value);
190 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
192 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
193 + spin_unlock_irqrestore(&rg->lock, flags);
198 +static int ralink_gpio_probe(struct platform_device *pdev)
200 + struct device_node *np = pdev->dev.of_node;
201 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202 + struct ralink_gpio_chip *gc;
203 + const __be32 *ngpio;
206 + dev_err(&pdev->dev, "failed to find resource\n");
210 + gc = devm_kzalloc(&pdev->dev,
211 + sizeof(struct ralink_gpio_chip), GFP_KERNEL);
215 + gc->membase = devm_request_and_ioremap(&pdev->dev, res);
216 + if (!gc->membase) {
217 + dev_err(&pdev->dev, "cannot remap I/O memory region\n");
221 + if (of_property_read_u8_array(np, "ralink,register-map",
222 + gc->regs, GPIO_REG_MAX)) {
223 + dev_err(&pdev->dev, "failed to read register definition\n");
227 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
229 + dev_err(&pdev->dev, "failed to read number of pins\n");
233 + spin_lock_init(&gc->lock);
235 + gc->chip.label = dev_name(&pdev->dev);
236 + gc->chip.of_node = np;
237 + gc->chip.base = -1;
238 + gc->chip.ngpio = be32_to_cpu(*ngpio);
239 + gc->chip.direction_input = ralink_gpio_direction_input;
240 + gc->chip.direction_output = ralink_gpio_direction_output;
241 + gc->chip.get = ralink_gpio_get;
242 + gc->chip.set = ralink_gpio_set;
244 + /* set polarity to low for all lines */
245 + rt_gpio_w32(gc, GPIO_REG_POL, 0);
247 + dev_info(&pdev->dev, "registering %d gpios\n", gc->chip.ngpio);
249 + return gpiochip_add(&gc->chip);
252 +static const struct of_device_id ralink_gpio_match[] = {
253 + { .compatible = "ralink,rt2880-gpio" },
256 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
258 +static struct platform_driver ralink_gpio_driver = {
259 + .probe = ralink_gpio_probe,
261 + .name = "rt2880_gpio",
262 + .owner = THIS_MODULE,
263 + .of_match_table = ralink_gpio_match,
267 +static int __init ralink_gpio_init(void)
269 + return platform_driver_register(&ralink_gpio_driver);
272 +subsys_initcall(ralink_gpio_init);