1 From c4d621e75e865fa5374946515ad0c5e060b9c446 Mon Sep 17 00:00:00 2001
2 From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
3 Date: Wed, 11 Sep 2013 14:17:47 -0500
4 Subject: [PATCH 056/105] MIPS: Fix SMP core calculations when using MT
7 The TCBIND register is only available if the core has MT support. It
8 should not be read otherwise. Secondly, the number of TCs (siblings)
9 are calculated differently depending on if the kernel is configured
12 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
13 Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
14 Cc: linux-mips@linux-mips.org
15 Patchwork: https://patchwork.linux-mips.org/patch/5822/
16 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
17 (cherry picked from commit 670bac3a8c201fc1f5f92ac6b4a8b42dc8172937)
19 arch/mips/kernel/smp-cmp.c | 13 +++++++++++--
20 1 file changed, 11 insertions(+), 2 deletions(-)
22 diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
23 index c2e5d74..5969f1e 100644
24 --- a/arch/mips/kernel/smp-cmp.c
25 +++ b/arch/mips/kernel/smp-cmp.c
26 @@ -99,7 +99,9 @@ static void cmp_init_secondary(void)
28 c->core = (read_c0_ebase() >> 1) & 0x1ff;
29 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
30 - c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
32 + c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
35 #ifdef CONFIG_MIPS_MT_SMTC
36 c->tc_id = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
37 @@ -177,9 +179,16 @@ void __init cmp_smp_setup(void)
41 - unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
42 + unsigned int nvpe = 1;
43 +#ifdef CONFIG_MIPS_MT_SMP
44 + unsigned int mvpconf0 = read_c0_mvpconf0();
46 + nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
47 +#elif defined(CONFIG_MIPS_MT_SMTC)
48 + unsigned int mvpconf0 = read_c0_mvpconf0();
50 nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
52 smp_num_siblings = nvpe;
54 pr_info("Detected %i available secondary CPU(s)\n", ncpu);