1 Index: linux-3.10.21/drivers/spi/spi-rt2880.c
2 ===================================================================
3 --- linux-3.10.21.orig/drivers/spi/spi-rt2880.c 2013-12-09 20:17:54.380713104 +0100
4 +++ linux-3.10.21/drivers/spi/spi-rt2880.c 2013-12-09 20:35:08.004737585 +0100
7 #include <linux/reset.h>
8 #include <linux/spi/spi.h>
9 +#include <linux/of_device.h>
10 #include <linux/platform_device.h>
12 +#include <ralink_regs.h>
14 #define DRIVER_NAME "spi-rt2880"
15 /* only one slave is supported*/
16 #define RALINK_NUM_CHIPSELECTS 1
18 /* SPIFIFOSTAT register bit field */
19 #define SPIFIFOSTAT_TXFULL BIT(17)
21 +#define MT7621_SPI_TRANS 0x00
22 +#define SPITRANS_BUSY BIT(16)
23 +#define MT7621_SPI_OPCODE 0x04
24 +#define MT7621_SPI_DATA0 0x08
25 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
26 +#define SPI_CTL_START BIT(8)
27 +#define MT7621_SPI_POLAR 0x38
28 +#define MT7621_SPI_MASTER 0x28
29 +#define MT7621_SPI_SPACE 0x3c
33 +struct rt2880_spi_ops {
34 + void (*init_hw)(struct rt2880_spi *rs);
35 + void (*set_cs)(struct rt2880_spi *rs, int enable);
36 + int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
37 + unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
41 struct spi_master *master;
48 + struct rt2880_spi_ops *ops;
51 static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
56 +static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
58 +/* u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
60 + // set default clock to hclk/5
61 + master &= ~(0xfff << 16);
62 + master |= 0x3 << 16;
68 * called only when no transfer is active on the bus
72 if (rs->speed != speed) {
73 dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
74 - rc = rt2880_spi_baudrate_set(spi, speed);
75 + rc = rs->ops->baudrate_set(spi, speed);
80 rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
83 +static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
85 + u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
91 + rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
94 static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
101 +static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
105 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
108 + status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
109 + if ((status & SPITRANS_BUSY) == 0) {
120 -rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
121 +rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
123 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
125 @@ -239,6 +303,100 @@
130 +mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
132 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
133 + struct spi_transfer *next = NULL;
134 + const u8 *tx = xfer->tx_buf;
137 + int len = xfer->len;
142 + if (!list_is_last(&xfer->transfer_list, list)) {
143 + next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
147 + trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
148 + trans &= ~SPI_CTL_TX_RX_CNT_MASK;
151 + u32 data0 = 0, opcode = 0;
153 + switch (xfer->len) {
155 + data0 |= tx[7] << 24;
157 + data0 |= tx[6] << 16;
159 + data0 |= tx[5] << 8;
163 + opcode |= tx[3] << 8;
165 + opcode |= tx[2] << 16;
167 + opcode |= tx[1] << 24;
173 + dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
177 + rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
178 + rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
179 + trans |= xfer->len;
183 + trans |= (next->len << 4);
184 + rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
185 + trans |= SPI_CTL_START;
186 + rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
188 + mt7621_spi_wait_till_ready(rs);
191 + u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
192 + u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
194 + switch (next->len) {
196 + rx[7] = (opcode >> 24) & 0xff;
198 + rx[6] = (opcode >> 16) & 0xff;
200 + rx[5] = (opcode >> 8) & 0xff;
202 + rx[4] = opcode & 0xff;
204 + rx[3] = (data0 >> 24) & 0xff;
206 + rx[2] = (data0 >> 16) & 0xff;
208 + rx[1] = (data0 >> 8) & 0xff;
210 + rx[0] = data0 & 0xff;
214 + dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
223 static int rt2880_spi_transfer_one_message(struct spi_master *master,
224 struct spi_message *m)
226 @@ -280,25 +438,25 @@
230 - rt2880_spi_set_cs(rs, 1);
231 + rs->ops->set_cs(rs, 1);
236 - m->actual_length += rt2880_spi_write_read(spi, t);
237 + m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
240 udelay(t->delay_usecs);
243 - rt2880_spi_set_cs(rs, 0);
244 + rs->ops->set_cs(rs, 0);
251 - rt2880_spi_set_cs(rs, 0);
252 + rs->ops->set_cs(rs, 0);
255 spi_finalize_current_message(master);
257 rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
260 +static void mt7621_spi_reset(struct rt2880_spi *rs)
262 + u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
264 + master &= ~(0xfff << 16);
268 + rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
271 +static struct rt2880_spi_ops spi_ops[] = {
273 + .init_hw = rt2880_spi_reset,
274 + .set_cs = rt2880_spi_set_cs,
275 + .baudrate_set = rt2880_spi_baudrate_set,
276 + .write_read = rt2880_spi_write_read,
278 + .init_hw = mt7621_spi_reset,
279 + .set_cs = mt7621_spi_set_cs,
280 + .baudrate_set = mt7621_spi_baudrate_set,
281 + .write_read = mt7621_spi_write_read,
285 +static const struct of_device_id rt2880_spi_match[] = {
286 + { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
287 + { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
290 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
292 static int rt2880_spi_probe(struct platform_device *pdev)
294 + const struct of_device_id *match;
295 struct spi_master *master;
296 struct rt2880_spi *rs;
302 + match = of_match_device(rt2880_spi_match, &pdev->dev);
306 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
307 base = devm_ioremap_resource(&pdev->dev, r);
309 @@ -382,12 +577,13 @@
312 rs->sys_freq = clk_get_rate(rs->clk);
313 + rs->ops = (struct rt2880_spi_ops *) match->data;
314 dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
315 spin_lock_irqsave(&rs->lock, flags);
317 device_reset(&pdev->dev);
319 - rt2880_spi_reset(rs);
320 + rs->ops->init_hw(rs);
322 return spi_register_master(master);
326 MODULE_ALIAS("platform:" DRIVER_NAME);
328 -static const struct of_device_id rt2880_spi_match[] = {
329 - { .compatible = "ralink,rt2880-spi" },
332 -MODULE_DEVICE_TABLE(of, rt2880_spi_match);
334 static struct platform_driver rt2880_spi_driver = {