1 From 2a9b5a9fc1a0707b95dbe61dd1c30b9337cb457d Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 05:26:34 +0000
4 Subject: [PATCH 212/215] GPIO: ralink: add mt7621 gpio controller
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/Kconfig | 5 +-
9 drivers/gpio/Kconfig | 6 ++
10 drivers/gpio/Makefile | 1 +
11 drivers/gpio/gpio-mt7621.c | 183 ++++++++++++++++++++++++++++++++++++++++++++
12 4 files changed, 194 insertions(+), 1 deletion(-)
13 create mode 100644 drivers/gpio/gpio-mt7621.c
15 --- a/arch/mips/Kconfig
16 +++ b/arch/mips/Kconfig
17 @@ -448,7 +448,10 @@ config RALINK
18 select ARCH_REQUIRE_GPIOLIB
22 + select ARCH_HAS_RESET_CONTROLLER
23 + select RESET_CONTROLLER
24 + select ARCH_REQUIRE_GPIOLIB
27 bool "SGI IP22 (Indy/Indigo2)"
29 --- a/drivers/gpio/Kconfig
30 +++ b/drivers/gpio/Kconfig
31 @@ -710,6 +710,12 @@ config GPIO_MSIC
32 Enable support for GPIO on intel MSIC controllers found in
36 + bool "Mediatek GPIO Support"
37 + depends on SOC_MT7621
39 + Say yes here to support the Mediatek SoC GPIO device
41 comment "USB GPIO expanders:"
43 config GPIO_VIPERBOARD
44 --- a/drivers/gpio/Makefile
45 +++ b/drivers/gpio/Makefile
46 @@ -88,3 +88,4 @@ obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x
47 obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
48 obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
49 obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
50 +obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
52 +++ b/drivers/gpio/gpio-mt7621.c
55 + * This program is free software; you can redistribute it and/or modify it
56 + * under the terms of the GNU General Public License version 2 as published
57 + * by the Free Software Foundation.
59 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
60 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
63 +#include <linux/io.h>
64 +#include <linux/err.h>
65 +#include <linux/gpio.h>
66 +#include <linux/module.h>
67 +#include <linux/of_irq.h>
68 +#include <linux/spinlock.h>
69 +#include <linux/irqdomain.h>
70 +#include <linux/interrupt.h>
71 +#include <linux/platform_device.h>
73 +#define MTK_BANK_WIDTH 32
75 +enum mediatek_gpio_reg {
83 +static void __iomem *mtk_gc_membase;
86 + struct gpio_chip chip;
92 +gpio_to_irq(unsigned gpio)
97 +static inline struct mtk_gc
98 +*to_mediatek_gpio(struct gpio_chip *chip)
100 + struct mtk_gc *mgc;
102 + mgc = container_of(chip, struct mtk_gc, chip);
108 +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
110 + iowrite32(val, mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
114 +mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
116 + return ioread32(mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
120 +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
122 + struct mtk_gc *rg = to_mediatek_gpio(chip);
124 + mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
128 +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
130 + struct mtk_gc *rg = to_mediatek_gpio(chip);
132 + return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
136 +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
138 + struct mtk_gc *rg = to_mediatek_gpio(chip);
139 + unsigned long flags;
142 + spin_lock_irqsave(&rg->lock, flags);
143 + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
145 + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
146 + spin_unlock_irqrestore(&rg->lock, flags);
152 +mediatek_gpio_direction_output(struct gpio_chip *chip,
153 + unsigned offset, int value)
155 + struct mtk_gc *rg = to_mediatek_gpio(chip);
156 + unsigned long flags;
159 + spin_lock_irqsave(&rg->lock, flags);
160 + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
162 + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
163 + mediatek_gpio_set(chip, offset, value);
164 + spin_unlock_irqrestore(&rg->lock, flags);
170 +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
172 + const __be32 *id = of_get_property(bank, "reg", NULL);
173 + struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
174 + sizeof(struct mtk_gc), GFP_KERNEL);
178 + spin_lock_init(&rg->lock);
180 + rg->chip.dev = &pdev->dev;
181 + rg->chip.label = dev_name(&pdev->dev);
182 + rg->chip.of_node = bank;
183 + rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
184 + rg->chip.ngpio = MTK_BANK_WIDTH;
185 + rg->chip.direction_input = mediatek_gpio_direction_input;
186 + rg->chip.direction_output = mediatek_gpio_direction_output;
187 + rg->chip.get = mediatek_gpio_get;
188 + rg->chip.set = mediatek_gpio_set;
190 + /* set polarity to low for all gpios */
191 + mtk_gpio_w32(rg, GPIO_REG_POL, 0);
193 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
195 + return gpiochip_add(&rg->chip);
199 +mediatek_gpio_probe(struct platform_device *pdev)
201 + struct device_node *bank, *np = pdev->dev.of_node;
202 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
204 + mtk_gc_membase = devm_request_and_ioremap(&pdev->dev, res);
205 + if (IS_ERR(mtk_gc_membase))
206 + return PTR_ERR(mtk_gc_membase);
208 + for_each_child_of_node(np, bank)
209 + if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
210 + mediatek_gpio_bank_probe(pdev, bank);
215 +static const struct of_device_id mediatek_gpio_match[] = {
216 + { .compatible = "mtk,mt7621-gpio" },
219 +MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
221 +static struct platform_driver mediatek_gpio_driver = {
222 + .probe = mediatek_gpio_probe,
224 + .name = "mt7621_gpio",
225 + .owner = THIS_MODULE,
226 + .of_match_table = mediatek_gpio_match,
231 +mediatek_gpio_init(void)
233 + return platform_driver_register(&mediatek_gpio_driver);
236 +subsys_initcall(mediatek_gpio_init);