1 From ded577553b06a85c12a89b8fbcfa2b51f30bc037 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 18 May 2013 22:06:15 +0200
4 Subject: [PATCH 13/33] PCI: MIPS: adds mt7620a pcie driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/pci/Makefile | 1 +
9 arch/mips/pci/pci-mt7620a.c | 363 +++++++++++++++++++++++++++++++++++++++++++
10 arch/mips/ralink/Kconfig | 1 +
11 3 files changed, 365 insertions(+)
12 create mode 100644 arch/mips/pci/pci-mt7620a.c
14 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
15 index 3cbfd9b..025d3a7 100644
16 --- a/arch/mips/pci/Makefile
17 +++ b/arch/mips/pci/Makefile
18 @@ -43,6 +43,7 @@ obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
19 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
20 obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
21 obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
22 +obj-$(CONFIG_SOC_MT7620) += pci-mt7620a.o
23 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
24 obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
25 obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
26 diff --git a/arch/mips/pci/pci-mt7620a.c b/arch/mips/pci/pci-mt7620a.c
28 index 0000000..271763c
30 +++ b/arch/mips/pci/pci-mt7620a.c
33 + * Ralink MT7620A SoC PCI support
35 + * Copyright (C) 2007-2013 Bruce Chang
36 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
38 + * This program is free software; you can redistribute it and/or modify it
39 + * under the terms of the GNU General Public License version 2 as published
40 + * by the Free Software Foundation.
43 +#include <linux/types.h>
44 +#include <linux/pci.h>
45 +#include <linux/io.h>
46 +#include <linux/init.h>
47 +#include <linux/delay.h>
48 +#include <linux/interrupt.h>
49 +#include <linux/module.h>
50 +#include <linux/of.h>
51 +#include <linux/of_irq.h>
52 +#include <linux/of_pci.h>
53 +#include <linux/reset.h>
54 +#include <linux/platform_device.h>
56 +#include <asm/mach-ralink/ralink_regs.h>
58 +#define RALINK_PCI_MM_MAP_BASE 0x20000000
59 +#define RALINK_PCI_IO_MAP_BASE 0x10160000
61 +#define RALINK_INT_PCIE0 4
62 +#define RALINK_SYSTEM_CONTROL_BASE 0xb0000000
63 +#define RALINK_SYSCFG1 0x14
64 +#define RALINK_CLKCFG1 0x30
65 +#define RALINK_GPIOMODE 0x60
66 +#define RALINK_PCIE_CLK_GEN 0x7c
67 +#define RALINK_PCIE_CLK_GEN1 0x80
68 +#define PCIEPHY0_CFG 0x90
69 +#define PPLL_CFG1 0x9c
70 +#define PPLL_DRV 0xa0
71 +#define RALINK_PCI_HOST_MODE_EN (1<<7)
72 +#define RALINK_PCIE_RC_MODE_EN (1<<8)
73 +#define RALINK_PCIE_RST (1<<23)
74 +#define RALINK_PCI_RST (1<<24)
75 +#define RALINK_PCI_CLK_EN (1<<19)
76 +#define RALINK_PCIE_CLK_EN (1<<21)
77 +#define PCI_SLOTx2 (1<<11)
78 +#define PCI_SLOTx1 (2<<11)
79 +#define PDRV_SW_SET (1<<31)
80 +#define LC_CKDRVPD_ (1<<19)
82 +#define RALINK_PCI_CONFIG_ADDR 0x20
83 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
84 +#define MEMORY_BASE 0x0
85 +#define RALINK_PCIE0_RST (1<<26)
86 +#define RALINK_PCI_BASE 0xB0140000
87 +#define RALINK_PCI_MEMBASE 0x28
88 +#define RALINK_PCI_IOBASE 0x2C
90 +#define RT6855_PCIE0_OFFSET 0x2000
92 +#define RALINK_PCI_PCICFG_ADDR 0x00
93 +#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
94 +#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
95 +#define RALINK_PCI0_ID 0x30
96 +#define RALINK_PCI0_CLASS 0x34
97 +#define RALINK_PCI0_SUBID 0x38
98 +#define RALINK_PCI0_STATUS 0x50
99 +#define RALINK_PCI_PCIMSK_ADDR 0x0C
101 +#define RALINK_PCIE0_CLK_EN (1 << 26)
103 +#define BUSY 0x80000000
104 +#define WAITRETRY_MAX 10
105 +#define WRITE_MODE (1UL << 23)
106 +#define DATA_SHIFT 0
107 +#define ADDR_SHIFT 8
110 +static void __iomem *bridge_base;
111 +static void __iomem *pcie_base;
113 +static struct reset_control *rstpcie0;
115 +static inline void bridge_w32(u32 val, unsigned reg)
117 + iowrite32(val, bridge_base + reg);
120 +static inline u32 bridge_r32(unsigned reg)
122 + return ioread32(bridge_base + reg);
125 +static inline void pcie_w32(u32 val, unsigned reg)
127 + iowrite32(val, pcie_base + reg);
130 +static inline u32 pcie_r32(unsigned reg)
132 + return ioread32(pcie_base + reg);
135 +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
137 + u32 val = pcie_r32(reg);
140 + pcie_w32(val, reg);
143 +int wait_pciephy_busy(void)
145 + unsigned long reg_value = 0x0, retry = 0;
148 + //reg_value = rareg(READMODE, PCIEPHY0_CFG, 0);
149 + reg_value = pcie_r32(PCIEPHY0_CFG);
151 + if (reg_value & BUSY)
155 + if (retry++ > WAITRETRY_MAX){
156 + printk("PCIE-PHY retry failed.\n");
163 +static void pcie_phy(unsigned long addr, unsigned long val)
165 + wait_pciephy_busy();
166 + pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
168 + wait_pciephy_busy();
171 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
173 + unsigned int slot = PCI_SLOT(devfn);
174 + u8 func = PCI_FUNC(devfn);
178 + address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
179 + bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
180 + data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
184 + *val = (data >> ((where & 3) << 3)) & 0xff;
187 + *val = (data >> ((where & 3) << 3)) & 0xffff;
194 + return PCIBIOS_SUCCESSFUL;
197 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
199 + unsigned int slot = PCI_SLOT(devfn);
200 + u8 func = PCI_FUNC(devfn);
204 + address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
205 + bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
206 + data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
210 + data = (data & ~(0xff << ((where & 3) << 3))) |
211 + (val << ((where & 3) << 3));
214 + data = (data & ~(0xffff << ((where & 3) << 3))) |
215 + (val << ((where & 3) << 3));
222 + bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
224 + return PCIBIOS_SUCCESSFUL;
227 +struct pci_ops mt7620a_pci_ops= {
228 + .read = pci_config_read,
229 + .write = pci_config_write,
232 +static struct resource mt7620a_res_pci_mem1 = {
233 + .name = "pci memory",
234 + .start = RALINK_PCI_MM_MAP_BASE,
235 + .end = (u32) ((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
236 + .flags = IORESOURCE_MEM,
238 +static struct resource mt7620a_res_pci_io1 = {
240 + .start = RALINK_PCI_IO_MAP_BASE,
241 + .end = (u32) ((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
242 + .flags = IORESOURCE_IO,
245 +struct pci_controller mt7620a_controller = {
246 + .pci_ops = &mt7620a_pci_ops,
247 + .mem_resource = &mt7620a_res_pci_mem1,
248 + .io_resource = &mt7620a_res_pci_io1,
249 + .mem_offset = 0x00000000UL,
250 + .io_offset = 0x00000000UL,
251 + .io_map_base = 0xa0000000,
254 +static int mt7620a_pci_probe(struct platform_device *pdev)
256 + struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
257 + struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
259 + rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
260 + if (IS_ERR(rstpcie0))
261 + return PTR_ERR(rstpcie0);
263 + bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
267 + pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
271 + iomem_resource.start = 0;
272 + iomem_resource.end= ~0;
273 + ioport_resource.start= 0;
274 + ioport_resource.end = ~0;
276 + /* PCIE: bypass PCIe DLL */
277 + pcie_phy(0x0, 0x80);
278 + pcie_phy(0x1, 0x04);
279 + /* PCIE: Elastic buffer control */
280 + pcie_phy(0x68, 0xB4);
282 + reset_control_assert(rstpcie0);
283 + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
284 + rt_sysc_m32(1<<19, 1<<31, PPLL_DRV);
285 + rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
287 + reset_control_deassert(rstpcie0);
288 + rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
292 + if (!(rt_sysc_r32(PPLL_CFG1) & 1<<23)) {
293 + printk("MT7620 PPLL unlock\n");
294 + reset_control_assert(rstpcie0);
295 + rt_sysc_m32(BIT(26), 0, RALINK_CLKCFG1);
298 + rt_sysc_m32((0x1<<18) | (0x1<<17), (0x1 << 19) | (0x1 << 31), PPLL_DRV);
301 + reset_control_assert(rstpcie0);
302 + rt_sysc_m32(0x30, 2 << 4, RALINK_SYSCFG1);
304 + rt_sysc_m32(~0x7fffffff, 0x80000000, RALINK_PCIE_CLK_GEN);
305 + rt_sysc_m32(~0x80ffffff, 0xa << 24, RALINK_PCIE_CLK_GEN1);
308 + reset_control_deassert(rstpcie0);
309 + pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
312 + if (( pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
313 + reset_control_assert(rstpcie0);
314 + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
315 + rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
316 + printk("PCIE0 no card, disable it(RST&CLK)\n");
319 + bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
320 + bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
322 + pcie_w32(0x7FFF0000, RALINK_PCI0_BAR0SETUP_ADDR);
323 + pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
324 + pcie_w32(0x08021814, RALINK_PCI0_ID);
325 + pcie_w32(0x06040001, RALINK_PCI0_CLASS);
326 + pcie_w32(0x28801814, RALINK_PCI0_SUBID);
327 + pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
329 + register_pci_controller(&mt7620a_controller);
334 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
336 + const struct resource *res;
341 + if ((dev->bus->number == 0) && (slot == 0)) {
342 + pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
343 + pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
344 + pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
345 + } else if ((dev->bus->number == 1) && (slot == 0x0)) {
346 + irq = RALINK_INT_PCIE0;
348 + printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
352 + for (i = 0; i < 6; i++) {
353 + res = &dev->resource[i];
356 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
357 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
358 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
361 + cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
362 + pci_write_config_word(dev, PCI_COMMAND, cmd);
363 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
364 + //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
369 +int pcibios_plat_dev_init(struct pci_dev *dev)
374 +static const struct of_device_id mt7620a_pci_ids[] = {
375 + { .compatible = "ralink,mt7620a-pci" },
378 +MODULE_DEVICE_TABLE(of, mt7620a_pci_ids);
380 +static struct platform_driver mt7620a_pci_driver = {
381 + .probe = mt7620a_pci_probe,
383 + .name = "mt7620a-pci",
384 + .owner = THIS_MODULE,
385 + .of_match_table = of_match_ptr(mt7620a_pci_ids),
389 +static int __init mt7620a_pci_init(void)
391 + return platform_driver_register(&mt7620a_pci_driver);
394 +arch_initcall(mt7620a_pci_init);
395 diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
396 index 592e5f9..992e365 100644
397 --- a/arch/mips/ralink/Kconfig
398 +++ b/arch/mips/ralink/Kconfig
399 @@ -24,6 +24,7 @@ choice