1 From 08c3b38a75ca47b74c81d14e1715ab9dc7b0e5cb Mon Sep 17 00:00:00 2001
2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 Date: Fri, 5 Jul 2013 14:54:24 +0200
4 Subject: [PATCH 050/203] bus: mvebu-mbus: Remove name -> target, attribute
7 This tables were used together with the name-based MBus window
8 creation API. Since that's has been removed, we can also remove
11 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 Tested-by: Andrew Lunn <andrew@lunn.ch>
13 Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
15 drivers/bus/mvebu-mbus.c | 150 +++--------------------------------------------
16 1 file changed, 7 insertions(+), 143 deletions(-)
18 --- a/drivers/bus/mvebu-mbus.c
19 +++ b/drivers/bus/mvebu-mbus.c
22 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
24 -struct mvebu_mbus_mapping {
32 - * Masks used for the 'attrmask' field of mvebu_mbus_mapping. They
33 - * allow to get the real attribute value, discarding the special bits
34 - * used to select a PCI MEM region or a PCI WA region. This allows the
35 - * debugfs code to reverse-match the name of a device from its
36 - * target/attr values.
38 - * For all devices except PCI, all bits of 'attr' must be
39 - * considered. For most SoCs, only bit 3 should be ignored (it allows
40 - * to select between PCI MEM and PCI I/O). On Orion5x however, there
41 - * is the special bit 5 to select a PCI WA region.
43 -#define MAPDEF_NOMASK 0xff
44 -#define MAPDEF_PCIMASK 0xf7
45 -#define MAPDEF_ORIONPCIMASK 0xd7
47 -/* Macro used to define one mvebu_mbus_mapping entry */
48 -#define MAPDEF(__n, __t, __a, __m) \
49 - { .name = __n, .target = __t, .attr = __a, .attrmask = __m }
51 struct mvebu_mbus_state;
53 struct mvebu_mbus_soc_data {
54 @@ -133,7 +106,6 @@ struct mvebu_mbus_soc_data {
55 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
56 int (*show_cpu_target)(struct mvebu_mbus_state *s,
57 struct seq_file *seq, void *v);
58 - const struct mvebu_mbus_mapping *map;
61 struct mvebu_mbus_state {
62 @@ -430,8 +402,7 @@ static int mvebu_devs_debug_show(struct
70 mvebu_mbus_read_window(mbus, win,
71 &enabled, &wbase, &wsize,
72 @@ -442,18 +413,9 @@ static int mvebu_devs_debug_show(struct
77 - for (i = 0; mbus->soc->map[i].name; i++)
78 - if (mbus->soc->map[i].target == wtarget &&
79 - mbus->soc->map[i].attr ==
80 - (wattr & mbus->soc->map[i].attrmask))
83 - name = mbus->soc->map[i].name ?: "unknown";
85 - seq_printf(seq, "[%02d] %016llx - %016llx : %s",
86 + seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
87 win, (unsigned long long)wbase,
88 - (unsigned long long)(wbase + wsize), name);
89 + (unsigned long long)(wbase + wsize), wtarget, wattr);
91 if (win < mbus->soc->num_remappable_wins) {
92 seq_printf(seq, " (remap %016llx)\n",
93 @@ -578,45 +540,12 @@ mvebu_mbus_dove_setup_cpu_target(struct
94 mvebu_mbus_dram_info.num_cs = cs;
97 -static const struct mvebu_mbus_mapping armada_370_map[] = {
98 - MAPDEF("bootrom", 1, 0xe0, MAPDEF_NOMASK),
99 - MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
100 - MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
101 - MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
102 - MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
103 - MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
104 - MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
105 - MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
109 static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
111 .num_remappable_wins = 8,
112 .win_cfg_offset = armada_370_xp_mbus_win_offset,
113 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
114 .show_cpu_target = mvebu_sdram_debug_show_orion,
115 - .map = armada_370_map,
118 -static const struct mvebu_mbus_mapping armada_xp_map[] = {
119 - MAPDEF("bootrom", 1, 0x1d, MAPDEF_NOMASK),
120 - MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
121 - MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
122 - MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
123 - MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
124 - MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
125 - MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
126 - MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
127 - MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
128 - MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
129 - MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
130 - MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
131 - MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
132 - MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
133 - MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
134 - MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
138 static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
139 @@ -625,15 +554,6 @@ static const struct mvebu_mbus_soc_data
140 .win_cfg_offset = armada_370_xp_mbus_win_offset,
141 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
142 .show_cpu_target = mvebu_sdram_debug_show_orion,
143 - .map = armada_xp_map,
146 -static const struct mvebu_mbus_mapping kirkwood_map[] = {
147 - MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
148 - MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK),
149 - MAPDEF("sram", 3, 0x01, MAPDEF_NOMASK),
150 - MAPDEF("nand", 1, 0x2f, MAPDEF_NOMASK),
154 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
155 @@ -642,16 +562,6 @@ static const struct mvebu_mbus_soc_data
156 .win_cfg_offset = orion_mbus_win_offset,
157 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
158 .show_cpu_target = mvebu_sdram_debug_show_orion,
159 - .map = kirkwood_map,
162 -static const struct mvebu_mbus_mapping dove_map[] = {
163 - MAPDEF("pcie0.0", 0x4, 0xe0, MAPDEF_PCIMASK),
164 - MAPDEF("pcie1.0", 0x8, 0xe0, MAPDEF_PCIMASK),
165 - MAPDEF("cesa", 0x3, 0x01, MAPDEF_NOMASK),
166 - MAPDEF("bootrom", 0x1, 0xfd, MAPDEF_NOMASK),
167 - MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK),
171 static const struct mvebu_mbus_soc_data dove_mbus_data = {
172 @@ -660,18 +570,6 @@ static const struct mvebu_mbus_soc_data
173 .win_cfg_offset = orion_mbus_win_offset,
174 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
175 .show_cpu_target = mvebu_sdram_debug_show_dove,
179 -static const struct mvebu_mbus_mapping orion5x_map[] = {
180 - MAPDEF("pcie0.0", 4, 0x51, MAPDEF_ORIONPCIMASK),
181 - MAPDEF("pci0.0", 3, 0x51, MAPDEF_ORIONPCIMASK),
182 - MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK),
183 - MAPDEF("devbus-cs0", 1, 0x1e, MAPDEF_NOMASK),
184 - MAPDEF("devbus-cs1", 1, 0x1d, MAPDEF_NOMASK),
185 - MAPDEF("devbus-cs2", 1, 0x1b, MAPDEF_NOMASK),
186 - MAPDEF("sram", 0, 0x00, MAPDEF_NOMASK),
191 @@ -684,7 +582,6 @@ static const struct mvebu_mbus_soc_data
192 .win_cfg_offset = orion_mbus_win_offset,
193 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
194 .show_cpu_target = mvebu_sdram_debug_show_orion,
195 - .map = orion5x_map,
198 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
199 @@ -693,21 +590,6 @@ static const struct mvebu_mbus_soc_data
200 .win_cfg_offset = orion_mbus_win_offset,
201 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
202 .show_cpu_target = mvebu_sdram_debug_show_orion,
203 - .map = orion5x_map,
206 -static const struct mvebu_mbus_mapping mv78xx0_map[] = {
207 - MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
208 - MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
209 - MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
210 - MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
211 - MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
212 - MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
213 - MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
214 - MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
215 - MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
216 - MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
220 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
221 @@ -716,7 +598,6 @@ static const struct mvebu_mbus_soc_data
222 .win_cfg_offset = mv78xx0_mbus_win_offset,
223 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
224 .show_cpu_target = mvebu_sdram_debug_show_orion,
225 - .map = mv78xx0_map,
229 @@ -895,33 +776,16 @@ static int __init mbus_dt_setup_win(stru
233 - const struct mvebu_mbus_mapping *map = mbus->soc->map;
237 - /* Search for a suitable window in the existing mappings */
238 - for (i = 0; map[i].name; i++)
239 - if (map[i].target == target &&
240 - map[i].attr == (attr & map[i].attrmask))
243 - name = map[i].name;
245 - pr_err("window 0x%x:0x%x is unknown, skipping\n",
250 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
251 - pr_err("cannot add window '%s', conflicts with another window\n",
253 + pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
258 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
260 - pr_err("cannot add window '%s', too many windows\n",
262 + pr_err("cannot add window '%04x:%04x', too many windows\n",