target/linux/coldfire/files-2.6.31/drivers/net/fec_m547x.c

   1 /*
   2  * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Author: Kurt Mahan, kmahan@freescale.com
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/string.h>
  13 #include <linux/ptrace.h>
  14 #include <linux/errno.h>
  15 #include <linux/ioport.h>
  16 #include <linux/slab.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20 #include <linux/phy.h>
  21 #include <linux/delay.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/bitops.h>
  28
  29 #include <asm/coldfire.h>
  30 #include <asm/mcfsim.h>
  31
  32 #include <asm/dma.h>
  33 #include <asm/MCD_dma.h>
  34 #include <asm/m5485sram.h>
  35 #include <asm/virtconvert.h>
  36 #include <asm/irq.h>
  37
  38 #include "fec_m547x.h"
  39
  40 #ifdef  CONFIG_FEC_548x_ENABLE_FEC2
  41 #define FEC_MAX_PORTS   2
  42 #define FEC_2
  43 #else
  44 #define FEC_MAX_PORTS   1
  45 #undef  FEC_2
  46 #endif
  47
  48 #define VERSION "0.20"
  49 MODULE_DESCRIPTION("DMA Fast Ethernet Controller driver ver " VERSION);
  50
  51 /* fec private */
  52 struct fec_priv {
  53         struct net_device *netdev;              /* owning net device */
  54         void *fecpriv_txbuf[FEC_TX_BUF_NUMBER]; /* tx buffer ptrs */
  55         MCD_bufDescFec *fecpriv_txdesc;         /* tx descriptor ptrs */
  56         volatile unsigned int fecpriv_current_tx; /* current tx desc index */
  57         volatile unsigned int fecpriv_next_tx;  /* next tx desc index */
  58         unsigned int fecpriv_current_rx;        /* current rx desc index */
  59         MCD_bufDescFec *fecpriv_rxdesc;         /* rx descriptor ptrs */
  60         struct sk_buff *askb_rx[FEC_RX_BUF_NUMBER]; /* rx SKB ptrs */
  61         unsigned int fecpriv_initiator_rx;      /* rx dma initiator */
  62         unsigned int fecpriv_initiator_tx;      /* tx dma initiator */
  63         int fecpriv_fec_rx_channel;             /* rx dma channel */
  64         int fecpriv_fec_tx_channel;             /* tx dma channel */
  65         int fecpriv_rx_requestor;               /* rx dma requestor */
  66         int fecpriv_tx_requestor;               /* tx dma requestor */
  67         void *fecpriv_interrupt_fec_rx_handler; /* dma rx handler */
  68         void *fecpriv_interrupt_fec_tx_handler; /* dma tx handler */
  69         unsigned char *fecpriv_mac_addr;        /* private fec mac addr */
  70         struct net_device_stats fecpriv_stat;   /* stats ptr */
  71         spinlock_t fecpriv_lock;
  72         int fecpriv_rxflag;
  73         struct tasklet_struct fecpriv_tasklet_reinit;
  74         int index;                              /* fec hw number */
  75         struct phy_device *phydev;
  76         struct mii_bus *mdio_bus;
  77         int  duplex;
  78         int  link;
  79         int  speed;
  80 };
  81
  82 struct net_device *fec_dev[FEC_MAX_PORTS];
  83
  84 /* FEC functions */
  85 static int __init fec_init(void);
  86 static struct net_device_stats *fec_get_stat(struct net_device *dev);
  87 static int fec_open(struct net_device *dev);
  88 static int fec_close(struct net_device *nd);
  89 static int fec_tx(struct sk_buff *skb, struct net_device *dev);
  90 static void fec_set_multicast_list(struct net_device *nd);
  91 static int fec_set_mac_address(struct net_device *dev, void *p);
  92 static void fec_tx_timeout(struct net_device *dev);
  93 static void fec_interrupt_fec_tx_handler(struct net_device *dev);
  94 static void fec_interrupt_fec_rx_handler(struct net_device *dev);
  95 static irqreturn_t fec_interrupt_handler(int irq, void *dev_id);
  96 static void fec_interrupt_fec_tx_handler_fec0(void);
  97 static void fec_interrupt_fec_rx_handler_fec0(void);
  98 static void fec_interrupt_fec_reinit(unsigned long data);
  99
 100 /* default fec0 address */
 101 unsigned char fec_mac_addr_fec0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x50 };
 102
 103 #ifdef FEC_2
 104 /* default fec1 address */
 105 unsigned char fec_mac_addr_fec1[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x51 };
 106 #endif
 107
 108 extern unsigned char uboot_enet0[];
 109 extern unsigned char uboot_enet1[];
 110
 111 #ifndef MODULE
 112 int fec_str_to_mac(char *str_mac, unsigned char* addr);
 113 int __init fec_mac_setup0(char *s);
 114 #endif
 115
 116
 117 #ifdef FEC_2
 118 void fec_interrupt_fec_tx_handler_fec1(void);
 119 void fec_interrupt_fec_rx_handler_fec1(void);
 120 #endif
 121
 122 #ifndef MODULE
 123 int __init fec_mac_setup1(char *s);
 124 #endif
 125
 126 module_init(fec_init);
 127 /* module_exit(fec_cleanup); */
 128
 129 __setup("mac0=", fec_mac_setup0);
 130
 131 #ifdef FEC_2
 132 __setup("mac1=", fec_mac_setup1);
 133 #endif
 134
 135 #define mk_mii_read(REG)        (0x60020000 | ((REG & 0x1f) << 18))
 136 #define mk_mii_write(REG, VAL)  (0x50020000 | ((REG & 0x1f) << 18) | \
 137                 (VAL & 0xffff))
 138 /* ----------------------------------------------------------- */
 139 static int coldfire_fec_mdio_read(struct mii_bus *bus,
 140         int phy_id, int reg)
 141 {
 142         int ret;
 143         struct net_device *dev = bus->priv;
 144 #ifdef CONFIG_FEC_548x_SHARED_PHY
 145         unsigned long base_addr = (unsigned long)FEC_BASE_ADDR_FEC0;
 146 #else
 147         unsigned long base_addr = (unsigned long) dev->base_addr;
 148 #endif
 149         int tries = 100;
 150
 151         /* Clear the MII interrupt bit */
 152         FEC_EIR(base_addr) = FEC_EIR_MII;
 153
 154         /* Write to the MII management frame register */
 155         FEC_MMFR(base_addr) = mk_mii_read(reg) | (phy_id << 23);
 156
 157         /* Wait for the reading */
 158         while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) {
 159                 udelay(10);
 160
 161                 if (!tries) {
 162                         printk(KERN_ERR "%s timeout\n", __func__);
 163                         return -ETIMEDOUT;
 164                 }
 165                 tries--;
 166         }
 167
 168         /* Clear the MII interrupt bit */
 169         FEC_EIR(base_addr) = FEC_EIR_MII;
 170         ret = FEC_MMFR(base_addr) & 0x0000FFFF;
 171         return ret;
 172 }
 173
 174 static int coldfire_fec_mdio_write(struct mii_bus *bus,
 175         int phy_id, int reg, u16 data)
 176 {
 177         int ret;
 178         struct net_device *dev = bus->priv;
 179 #ifdef CONFIG_FEC_548x_SHARED_PHY
 180         unsigned long base_addr = (unsigned long)FEC_BASE_ADDR_FEC0;
 181 #else
 182         unsigned long base_addr = (unsigned long) dev->base_addr;
 183 #endif
 184         int tries = 100;
 185
 186         printk(KERN_ERR "%s base_addr %x, phy_id %x, reg %x, data %x\n",
 187                 __func__, base_addr, phy_id, reg, data);
 188         /* Clear the MII interrupt bit */
 189         FEC_EIR(base_addr) = FEC_EIR_MII;
 190
 191         /*  Write to the MII management frame register */
 192         FEC_MMFR(base_addr) = mk_mii_write(reg, data) | (phy_id << 23);
 193
 194         /* Wait for the writing */
 195         while (!(FEC_EIR(base_addr) & FEC_EIR_MII)) {
 196                 udelay(10);
 197                 if (!tries) {
 198                         printk(KERN_ERR "%s timeout\n", __func__);
 199                         return -ETIMEDOUT;
 200                 }
 201                 tries--;
 202         }
 203         /* Clear the MII interrupt bit */
 204         FEC_EIR(base_addr) = FEC_EIR_MII;
 205         ret = FEC_MMFR(base_addr) & 0x0000FFFF;
 206
 207         return ret;
 208 }
 209
 210 static void fec_adjust_link(struct net_device *dev)
 211 {
 212         struct fec_priv *priv = netdev_priv(dev);
 213         struct phy_device *phydev = priv->phydev;
 214         int new_state = 0;
 215
 216         if (phydev->link != PHY_DOWN) {
 217                 if (phydev->duplex != priv->duplex) {
 218                         new_state = 1;
 219                         priv->duplex = phydev->duplex;
 220                 }
 221
 222                 if (phydev->speed != priv->speed) {
 223                         new_state = 1;
 224                         priv->speed = phydev->speed;
 225                 }
 226
 227                 if (priv->link == PHY_DOWN) {
 228                         new_state = 1;
 229                         priv->link = phydev->link;
 230                 }
 231         } else if (priv->link) {
 232                 new_state = 1;
 233                 priv->link = PHY_DOWN;
 234                 priv->speed = 0;
 235                 priv->duplex = -1;
 236         }
 237
 238         if (new_state)
 239                 phy_print_status(phydev);
 240 }
 241
 242 static int coldfire_fec_init_phy(struct net_device *dev)
 243 {
 244         struct fec_priv *priv = netdev_priv(dev);
 245         struct phy_device *phydev = NULL;
 246         int i;
 247         int startnode;
 248
 249 #ifdef CONFIG_FEC_548x_SHARED_PHY
 250         if (priv->index == 0)
 251                 startnode = 0;
 252         else if (priv->index == 1) {
 253                 struct fec_priv *priv0 = netdev_priv(fec_dev[0]);
 254                 startnode = priv0->phydev->addr + 1;
 255         } else
 256                 startnode = 0;
 257 #else
 258         startnode = 0;
 259 #endif
 260 #ifdef FEC_DEBUG
 261         printk(KERN_ERR "%s priv->index %x, startnode %x\n",
 262                 __func__, priv->index, startnode);
 263 #endif
 264         /* search for connect PHY device */
 265         for (i = startnode; i < PHY_MAX_ADDR; i++) {
 266                 struct phy_device *const tmp_phydev =
 267                         priv->mdio_bus->phy_map[i];
 268
 269                 if (!tmp_phydev) {
 270 #ifdef FEC_DEBUG
 271                         printk(KERN_INFO "%s no PHY here at"
 272                                 "mii_bus->phy_map[%d]\n",
 273                                 __func__, i);
 274 #endif
 275                         continue; /* no PHY here... */
 276                 }
 277                 phydev = tmp_phydev;
 278 #ifdef FEC_DEBUG
 279                 printk(KERN_INFO "%s find PHY here at"
 280                                 "mii_bus->phy_map[%d]\n",
 281                                 __func__, i);
 282 #endif
 283                 break; /* found it */
 284         }
 285
 286         /* now we are supposed to have a proper phydev, to attach to... */
 287         if (!phydev) {
 288                 printk(KERN_INFO "%s: Don't found any phy device at all\n",
 289                         dev->name);
 290                 return -ENODEV;
 291         }
 292
 293         priv->link = 0;
 294         priv->speed = 0;
 295         priv->duplex = 0;
 296 #ifdef FEC_DEBUG
 297         printk(KERN_INFO "%s phydev_busid %s\n", __func__, dev_name(&phydev->dev));
 298 #endif
 299         phydev = phy_connect(dev, dev_name(&phydev->dev),
 300                         &fec_adjust_link, 0, PHY_INTERFACE_MODE_MII);
 301         if (IS_ERR(phydev)) {
 302                 printk(KERN_ERR " %s phy_connect failed\n", __func__);
 303                 return PTR_ERR(phydev);
 304         }
 305
 306         printk(KERN_INFO "attached phy %i to driver %s\n",
 307         phydev->addr, phydev->drv->name);
 308         priv->phydev = phydev;
 309         return 0;
 310 }
 311
 312 static int fec_mdio_register(struct net_device *dev,
 313         int slot)
 314 {
 315         int err = 0;
 316         struct fec_priv *fp = netdev_priv(dev);
 317
 318         fp->mdio_bus = mdiobus_alloc();
 319         if (!fp->mdio_bus) {
 320                 printk(KERN_ERR "ethernet mdiobus_alloc fail\n");
 321                 return -ENOMEM;
 322         }
 323
 324         if (slot == 0) {
 325                 fp->mdio_bus->name = "Coldfire FEC MII 0 Bus";
 326                 strcpy(fp->mdio_bus->id, "0");
 327         } else if (slot == 1) {
 328                 fp->mdio_bus->name = "Coldfire FEC MII 1 Bus";
 329                 strcpy(fp->mdio_bus->id, "1");
 330         } else {
 331                 printk(KERN_ERR "Now coldfire can not"
 332                         "support more than 2 mii bus\n");
 333         }
 334
 335         fp->mdio_bus->read = &coldfire_fec_mdio_read;
 336         fp->mdio_bus->write = &coldfire_fec_mdio_write;
 337         fp->mdio_bus->priv = dev;
 338         err = mdiobus_register(fp->mdio_bus);
 339         if (err) {
 340                 mdiobus_free(fp->mdio_bus);
 341                 printk(KERN_ERR "%s: ethernet mdiobus_register fail %d\n",
 342                         dev->name, err);
 343                 return -EIO;
 344         }
 345
 346         printk(KERN_INFO "mdiobus_register %s ok\n",
 347                 fp->mdio_bus->name);
 348         return err;
 349 }
 350
 351 static const struct net_device_ops fec_netdev_ops = {
 352         .ndo_open               = fec_open,
 353         .ndo_stop               = fec_close,
 354         .ndo_start_xmit         = fec_tx,
 355         .ndo_set_multicast_list = fec_set_multicast_list,
 356         .ndo_tx_timeout         = fec_tx_timeout,
 357         .ndo_get_stats          = fec_get_stat,
 358         .ndo_validate_addr      = eth_validate_addr,
 359         .ndo_set_mac_address    = fec_set_mac_address,
 360 };
 361
 362 /*
 363  * Initialize a FEC device
 364  */
 365 int fec_enet_init(struct net_device *dev, int slot)
 366 {
 367         struct fec_priv *fp = netdev_priv(dev);
 368         int i;
 369
 370         fp->index = slot;
 371         fp->netdev = dev;
 372         fec_dev[slot] = dev;
 373
 374         if (slot == 0) {
 375                 /* disable fec0 */
 376                 FEC_ECR(FEC_BASE_ADDR_FEC0) = FEC_ECR_DISABLE;
 377
 378                 /* setup the interrupt handler */
 379                 dev->irq = 64 + ISC_FEC0;
 380
 381                 if (request_irq(dev->irq, fec_interrupt_handler,
 382                         IRQF_DISABLED, "ColdFire FEC 0", dev)) {
 383                         dev->irq = 0;
 384                         printk(KERN_ERR "Cannot allocate FEC0 IRQ\n");
 385                 } else {
 386                         /* interrupt priority and level */
 387                         MCF_ICR(ISC_FEC0) = ILP_FEC0;
 388                 }
 389
 390                 /* fec base address */
 391                 dev->base_addr = FEC_BASE_ADDR_FEC0;
 392
 393                 /* requestor numbers */
 394                 fp->fecpriv_rx_requestor = DMA_FEC0_RX;
 395                 fp->fecpriv_tx_requestor = DMA_FEC0_TX;
 396
 397                 /* fec0 handlers */
 398                 fp->fecpriv_interrupt_fec_rx_handler =
 399                         fec_interrupt_fec_rx_handler_fec0;
 400                 fp->fecpriv_interrupt_fec_tx_handler =
 401                         fec_interrupt_fec_tx_handler_fec0;
 402
 403                 /* tx descriptors */
 404                 fp->fecpriv_txdesc = (void *)FEC_TX_DESC_FEC0;
 405
 406                 /* rx descriptors */
 407                 fp->fecpriv_rxdesc = (void *)FEC_RX_DESC_FEC0;
 408
 409                 /* mac addr
 410                 if (uboot_enet0[0] || uboot_enet0[1] || uboot_enet0[2] ||
 411                     uboot_enet0[3] || uboot_enet0[4] || uboot_enet0[5]) {
 412                          use uboot enet 0 addr
 413                         memcpy(fec_mac_addr_fec0, uboot_enet0, 6);
 414                 }*/
 415                 fec_mac_addr_fec0[0] =
 416                         (FEC_PALR(FEC_BASE_ADDR_FEC0) >> 24) & 0xFF;
 417                 fec_mac_addr_fec0[1] =
 418                         (FEC_PALR(FEC_BASE_ADDR_FEC0) >> 16) & 0xFF;
 419                 fec_mac_addr_fec0[2] =
 420                         (FEC_PALR(FEC_BASE_ADDR_FEC0) >> 8) & 0xFF;
 421                 fec_mac_addr_fec0[3] =
 422                         (FEC_PALR(FEC_BASE_ADDR_FEC0)) & 0xFF;
 423                 fec_mac_addr_fec0[4] =
 424                         (FEC_PAUR(FEC_BASE_ADDR_FEC0) >> 24) & 0xFF;
 425                 fec_mac_addr_fec0[5] =
 426                         (FEC_PAUR(FEC_BASE_ADDR_FEC0) >> 16) & 0xFF;
 427
 428                 fp->fecpriv_mac_addr = fec_mac_addr_fec0;
 429         } else {
 430                 /* disable fec1 */
 431                 FEC_ECR(FEC_BASE_ADDR_FEC1) = FEC_ECR_DISABLE;
 432 #ifdef FEC_2
 433                 /* setup the interrupt handler */
 434                 dev->irq = 64 + ISC_FEC1;
 435
 436                 if (request_irq(dev->irq, fec_interrupt_handler,
 437                         IRQF_DISABLED, "ColdFire FEC 1", dev)) {
 438                         dev->irq = 0;
 439                         printk(KERN_ERR "Cannot allocate FEC1 IRQ\n");
 440                 } else {
 441                         /* interrupt priority and level */
 442                         MCF_ICR(ISC_FEC1) = ILP_FEC1;
 443                 }
 444
 445                 /* fec base address */
 446                 dev->base_addr = FEC_BASE_ADDR_FEC1;
 447
 448                 /* requestor numbers */
 449                 fp->fecpriv_rx_requestor = DMA_FEC1_RX;
 450                 fp->fecpriv_tx_requestor = DMA_FEC1_TX;
 451
 452                 /* fec1 handlers */
 453                 fp->fecpriv_interrupt_fec_rx_handler =
 454                         fec_interrupt_fec_rx_handler_fec1;
 455                 fp->fecpriv_interrupt_fec_tx_handler =
 456                         fec_interrupt_fec_tx_handler_fec1;
 457
 458                 /* tx descriptors */
 459                 fp->fecpriv_txdesc = (void *)FEC_TX_DESC_FEC1;
 460
 461                 /* rx descriptors */
 462                 fp->fecpriv_rxdesc = (void *)FEC_RX_DESC_FEC1;
 463
 464                 /* mac addr
 465                 if (uboot_enet1[0] || uboot_enet1[1] || uboot_enet1[2] ||
 466                     uboot_enet1[3] || uboot_enet1[4] || uboot_enet1[5]) {
 467                         use uboot enet 1 addr
 468                         memcpy(fec_mac_addr_fec1, uboot_enet1, 6);
 469                 }*/
 470                 fec_mac_addr_fec1[0] =
 471                         (FEC_PALR(FEC_BASE_ADDR_FEC1) >> 24) & 0xFF;
 472                 fec_mac_addr_fec1[1] =
 473                         (FEC_PALR(FEC_BASE_ADDR_FEC1) >> 16) & 0xFF;
 474                 fec_mac_addr_fec1[2] =
 475                         (FEC_PALR(FEC_BASE_ADDR_FEC1) >> 8) & 0xFF;
 476                 fec_mac_addr_fec1[3] =
 477                         (FEC_PALR(FEC_BASE_ADDR_FEC1)) & 0xFF;
 478                 fec_mac_addr_fec1[4] =
 479                         (FEC_PAUR(FEC_BASE_ADDR_FEC1) >> 24) & 0xFF;
 480                 fec_mac_addr_fec1[5] =
 481                         (FEC_PAUR(FEC_BASE_ADDR_FEC1) >> 16) & 0xFF;
 482
 483                 fp->fecpriv_mac_addr = fec_mac_addr_fec1;
 484 #endif
 485         }
 486
 487         /* clear MIB */
 488         memset((void *) (dev->base_addr + 0x200), 0, FEC_MIB_LEN);
 489
 490         /* clear the statistics structure */
 491         memset((void *) &(fp->fecpriv_stat), 0,
 492                sizeof(struct net_device_stats));
 493
 494         /* grab the FEC initiators */
 495         dma_set_initiator(fp->fecpriv_tx_requestor);
 496         fp->fecpriv_initiator_tx = dma_get_initiator(fp->fecpriv_tx_requestor);
 497         dma_set_initiator(fp->fecpriv_rx_requestor);
 498         fp->fecpriv_initiator_rx = dma_get_initiator(fp->fecpriv_rx_requestor);
 499
 500         /* reset the DMA channels */
 501         fp->fecpriv_fec_rx_channel = -1;
 502         fp->fecpriv_fec_tx_channel = -1;
 503
 504         for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
 505                 fp->askb_rx[i] = NULL;
 506
 507         /* initialize the pointers to the socket buffers */
 508         for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
 509                 fp->fecpriv_txbuf[i] = NULL;
 510
 511         ether_setup(dev);
 512
 513         dev->netdev_ops = &fec_netdev_ops;
 514         dev->watchdog_timeo = FEC_TX_TIMEOUT * HZ;
 515
 516         memcpy(dev->dev_addr, fp->fecpriv_mac_addr, ETH_ALEN);
 517
 518         spin_lock_init(&fp->fecpriv_lock);
 519
 520         /* Initialize FEC/I2C/IRQ Pin Assignment Register*/
 521         FEC_GPIO_PAR_FECI2CIRQ &= 0xF;
 522         FEC_GPIO_PAR_FECI2CIRQ |= FEC_FECI2CIRQ;
 523
 524         return 0;
 525 }
 526
 527 /*
 528  * Module Initialization
 529  */
 530 int __init fec_init(void)
 531 {
 532         struct net_device *dev;
 533         int i;
 534         int err;
 535         struct fec_priv *fep;
 536         DECLARE_MAC_BUF(mac);
 537
 538         printk(KERN_INFO "FEC ENET (DMA) Version %s\n", VERSION);
 539
 540         for (i = 0; i < FEC_MAX_PORTS; i++) {
 541                 dev = alloc_etherdev(sizeof(struct fec_priv));
 542                 if (!dev)
 543                         return -ENOMEM;
 544                 err = fec_enet_init(dev, i);
 545                 if (err) {
 546                         free_netdev(dev);
 547                         continue;
 548                 }
 549
 550                 fep = netdev_priv(dev);
 551                 FEC_MSCR(dev->base_addr) = FEC_MII_SPEED;
 552 #ifdef CONFIG_FEC_548x_SHARED_PHY
 553                 if (i == 0)
 554                         err = fec_mdio_register(dev, i);
 555                 else {
 556                         struct fec_priv *priv0 = netdev_priv(fec_dev[0]);
 557                         fep->mdio_bus = priv0->mdio_bus;
 558                         printk(KERN_INFO "FEC%d SHARED the %s ok\n",
 559                                 i, fep->mdio_bus->name);
 560                 }
 561 #else
 562                 err = fec_mdio_register(dev, i);
 563 #endif
 564                 if (err) {
 565                         printk(KERN_ERR "%s: ethernet fec_mdio_register\n",
 566                                 dev->name);
 567                         free_netdev(dev);
 568                         return -ENOMEM;
 569                 }
 570
 571                 if (register_netdev(dev) != 0) {
 572                         free_netdev(dev);
 573                         return -EIO;
 574                 }
 575
 576                 printk(KERN_INFO "%s: ethernet %s\n",
 577                        dev->name, print_mac(mac, dev->dev_addr));
 578         }
 579         return 0;
 580 }
 581
 582 /*
 583  * Stop a device
 584  */
 585 void fec_stop(struct net_device *dev)
 586 {
 587         struct fec_priv *fp = netdev_priv(dev);
 588
 589         dma_remove_initiator(fp->fecpriv_initiator_tx);
 590         dma_remove_initiator(fp->fecpriv_initiator_rx);
 591
 592         if (dev->irq)
 593                 free_irq(dev->irq, dev);
 594 }
 595
 596 /************************************************************************
 597 * NAME: fec_open
 598 *
 599 * DESCRIPTION: This function performs the initialization of
 600 *                               of FEC and corresponding KS8721 transiver
 601 *
 602 * RETURNS: If no error occurs, this function returns zero.
 603 *************************************************************************/
 604 int fec_open(struct net_device *dev)
 605 {
 606         struct fec_priv *fp = netdev_priv(dev);
 607         unsigned long base_addr = (unsigned long) dev->base_addr;
 608         int fduplex;
 609         int i;
 610         int channel;
 611         int error_code = -EBUSY;
 612
 613         fp->link = 0;
 614         fp->duplex = 0;
 615         fp->speed = 0;
 616         coldfire_fec_init_phy(dev);
 617         phy_start(fp->phydev);
 618
 619         /* Receive the DMA channels */
 620         channel = dma_set_channel_fec(fp->fecpriv_rx_requestor);
 621
 622         if (channel == -1) {
 623                 printk(KERN_ERR "Dma channel cannot be reserved\n");
 624                 goto ERRORS;
 625         }
 626
 627         fp->fecpriv_fec_rx_channel = channel;
 628
 629         dma_connect(channel, (int) fp->fecpriv_interrupt_fec_rx_handler);
 630
 631         channel = dma_set_channel_fec(fp->fecpriv_tx_requestor);
 632
 633         if (channel == -1) {
 634                 printk(KERN_ERR "Dma channel cannot be reserved\n");
 635                 goto ERRORS;
 636         }
 637
 638         fp->fecpriv_fec_tx_channel = channel;
 639
 640         dma_connect(channel, (int) fp->fecpriv_interrupt_fec_tx_handler);
 641
 642         /* init tasklet for controller reinitialization */
 643         tasklet_init(&fp->fecpriv_tasklet_reinit,
 644                 fec_interrupt_fec_reinit, (unsigned long) dev);
 645
 646         /* Reset FIFOs */
 647         FEC_FECFRST(base_addr) |= FEC_SW_RST | FEC_RST_CTL;
 648         FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
 649
 650         /* Reset and disable FEC */
 651         FEC_ECR(base_addr) = FEC_ECR_RESET;
 652
 653         udelay(10);
 654
 655         /* Clear all events */
 656         FEC_EIR(base_addr) = FEC_EIR_CLEAR;
 657
 658         /* Reset FIFO status */
 659         FEC_FECTFSR(base_addr) = FEC_FECTFSR_MSK;
 660         FEC_FECRFSR(base_addr) = FEC_FECRFSR_MSK;
 661
 662         /* Set the default address */
 663         FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) |
 664                               (fp->fecpriv_mac_addr[1] << 16) |
 665                               (fp->fecpriv_mac_addr[2] << 8) |
 666                               fp->fecpriv_mac_addr[3];
 667         FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) |
 668                               (fp->fecpriv_mac_addr[5] << 16) | 0x8808;
 669
 670         /* Reset the group address descriptor */
 671         FEC_GALR(base_addr) = 0x00000000;
 672         FEC_GAUR(base_addr) = 0x00000000;
 673
 674         /* Reset the individual address descriptor */
 675         FEC_IALR(base_addr) = 0x00000000;
 676         FEC_IAUR(base_addr) = 0x00000000;
 677
 678         /* Set the receive control register */
 679         FEC_RCR(base_addr) = FEC_RCR_MAX_FRM_SIZE | FEC_RCR_MII;
 680
 681         /* Set the receive FIFO control register */
 682         /*FEC_FECRFCR(base_addr) =
 683         * FEC_FECRFCR_FRM | FEC_FECRFCR_GR | FEC_FECRFCR_MSK;*/
 684         FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR
 685                         | (FEC_FECRFCR_MSK
 686                         /* disable all but ...*/
 687                         & ~FEC_FECRFCR_FAE
 688                         /* enable frame accept error*/
 689                         & ~FEC_FECRFCR_RXW
 690                         /* enable receive wait condition*/
 691                         /*& ~FEC_FECRFCR_UF*/
 692                         /* enable FIFO underflow*/
 693                                 );
 694
 695         /* Set the receive FIFO alarm register */
 696         FEC_FECRFAR(base_addr) = FEC_FECRFAR_ALARM;
 697
 698         /* Set the transmit FIFO control register */
 699         /*FEC_FECTFCR(base_addr) =
 700         FEC_FECTFCR_FRM | FEC_FECTFCR_GR | FEC_FECTFCR_MSK;*/
 701         FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR
 702                         | (FEC_FECTFCR_MSK
 703                         /* disable all but ... */
 704                         & ~FEC_FECTFCR_FAE
 705                         /* enable frame accept error */
 706                         /* & ~FEC_FECTFCR_TXW */
 707                         /*enable transmit wait condition*/
 708                         /*& ~FEC_FECTFCR_UF*/
 709                         /*enable FIFO underflow*/
 710                         & ~FEC_FECTFCR_OF);
 711                         /* enable FIFO overflow */
 712
 713         /* Set the transmit FIFO alarm register */
 714         FEC_FECTFAR(base_addr) = FEC_FECTFAR_ALARM;
 715
 716         /* Set the Tx FIFO watermark */
 717         FEC_FECTFWR(base_addr) = FEC_FECTFWR_XWMRK;
 718
 719         /* Enable the transmitter to append the CRC */
 720         FEC_CTCWR(base_addr) = FEC_CTCWR_TFCW_CRC;
 721
 722         /* Enable the ethernet interrupts */
 723         /*FEC_EIMR(base_addr) = FEC_EIMR_MASK;*/
 724         FEC_EIMR(base_addr) = FEC_EIMR_DISABLE
 725                         | FEC_EIR_LC
 726                         | FEC_EIR_RL
 727                         | FEC_EIR_HBERR
 728                         | FEC_EIR_XFUN
 729                         | FEC_EIR_XFERR
 730                         | FEC_EIR_RFERR;
 731
 732 #if 0
 733         error_code = init_transceiver(base_addr, &fduplex);
 734         if (error_code != 0) {
 735                 printk(KERN_ERR "Initialization of the "
 736                         "transceiver is failed\n");
 737                 goto ERRORS;
 738         }
 739 #else
 740         fduplex = 1;
 741 #endif
 742         if (fduplex)
 743                 /* Enable the full duplex mode */
 744                 FEC_TCR(base_addr) = FEC_TCR_FDEN | FEC_TCR_HBC;
 745         else
 746                 /* Disable reception of frames while transmitting */
 747                 FEC_RCR(base_addr) |= FEC_RCR_DRT;
 748
 749         /* Enable MIB */
 750         FEC_MIBC(base_addr) = FEC_MIBC_ENABLE;
 751
 752         /* Enable FEC */
 753         FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
 754         FEC_MSCR(dev->base_addr) = FEC_MII_SPEED;
 755         /* Initialize tx descriptors and start DMA for the transmission */
 756         for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
 757                 fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
 758
 759         fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
 760
 761         fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
 762
 763         MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
 764                      (unsigned char *) &(FEC_FECTFDR(base_addr)), 0,
 765                      FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx,
 766                      FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
 767                      MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
 768
 769         /* Initialize rx descriptors and start DMA for the reception */
 770         for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
 771                 fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_DMA);
 772                 if (!fp->askb_rx[i]) {
 773                         fp->fecpriv_rxdesc[i].dataPointer = 0;
 774                         fp->fecpriv_rxdesc[i].statCtrl = 0;
 775                         fp->fecpriv_rxdesc[i].length = 0;
 776                 } else {
 777                         skb_reserve(fp->askb_rx[i], 16);
 778                         fp->askb_rx[i]->dev = dev;
 779                         fp->fecpriv_rxdesc[i].dataPointer =
 780                         (unsigned int)virt_to_phys(fp->askb_rx[i]->tail);
 781                         fp->fecpriv_rxdesc[i].statCtrl =
 782                                 MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
 783                         fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
 784                 }
 785         }
 786
 787         fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
 788         fp->fecpriv_current_rx = 0;
 789
 790         MCD_startDma(fp->fecpriv_fec_rx_channel, (char *) fp->fecpriv_rxdesc, 0,
 791                      (unsigned char *) &(FEC_FECRFDR(base_addr)), 0,
 792                      FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_rx,
 793                      FEC_RX_DMA_PRI, MCD_FECRX_DMA | MCD_INTERRUPT,
 794                      MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
 795
 796         netif_start_queue(dev);
 797         return 0;
 798
 799 ERRORS:
 800
 801         /* Remove the channels and return with the error code */
 802         if (fp->fecpriv_fec_rx_channel != -1) {
 803                 dma_disconnect(fp->fecpriv_fec_rx_channel);
 804                 dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel);
 805                 fp->fecpriv_fec_rx_channel = -1;
 806         }
 807
 808         if (fp->fecpriv_fec_tx_channel != -1) {
 809                 dma_disconnect(fp->fecpriv_fec_tx_channel);
 810                 dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel);
 811                 fp->fecpriv_fec_tx_channel = -1;
 812         }
 813
 814         return error_code;
 815 }
 816
 817 /************************************************************************
 818 * NAME: fec_close
 819 *
 820 * DESCRIPTION: This function performs the graceful stop of the
 821 *                               transmission and disables FEC
 822 *
 823 * RETURNS: This function always returns zero.
 824 *************************************************************************/
 825 int fec_close(struct net_device *dev)
 826 {
 827         struct fec_priv *fp = netdev_priv(dev);
 828         unsigned long base_addr = (unsigned long) dev->base_addr;
 829         unsigned long time;
 830         int i;
 831
 832         netif_stop_queue(dev);
 833         phy_disconnect(fp->phydev);
 834         phy_stop(fp->phydev);
 835         /* Perform the graceful stop */
 836         FEC_TCR(base_addr) |= FEC_TCR_GTS;
 837
 838         time = jiffies;
 839
 840         /* Wait for the graceful stop */
 841         while (!(FEC_EIR(base_addr) & FEC_EIR_GRA) && jiffies - time <
 842                         (FEC_GR_TIMEOUT * HZ))
 843                 schedule();
 844
 845         /* Disable FEC */
 846         FEC_ECR(base_addr) = FEC_ECR_DISABLE;
 847
 848         /* Reset the DMA channels */
 849         spin_lock_irq(&fp->fecpriv_lock);
 850         MCD_killDma(fp->fecpriv_fec_tx_channel);
 851         spin_unlock_irq(&fp->fecpriv_lock);
 852         dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel);
 853         dma_disconnect(fp->fecpriv_fec_tx_channel);
 854         fp->fecpriv_fec_tx_channel = -1;
 855
 856         for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
 857                 if (fp->fecpriv_txbuf[i]) {
 858                         kfree(fp->fecpriv_txbuf[i]);
 859                         fp->fecpriv_txbuf[i] = NULL;
 860                 }
 861         }
 862
 863         spin_lock_irq(&fp->fecpriv_lock);
 864         MCD_killDma(fp->fecpriv_fec_rx_channel);
 865         spin_unlock_irq(&fp->fecpriv_lock);
 866
 867         dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel);
 868         dma_disconnect(fp->fecpriv_fec_rx_channel);
 869         fp->fecpriv_fec_rx_channel = -1;
 870
 871         for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
 872                 if (fp->askb_rx[i]) {
 873                         kfree_skb(fp->askb_rx[i]);
 874                         fp->askb_rx[i] = NULL;
 875                 }
 876         }
 877
 878         return 0;
 879 }
 880
 881 /************************************************************************
 882 * +NAME: fec_get_stat
 883 *
 884 * RETURNS: This function returns the statistical information.
 885 *************************************************************************/
 886 struct net_device_stats *fec_get_stat(struct net_device *dev)
 887 {
 888         struct fec_priv *fp = netdev_priv(dev);
 889         unsigned long base_addr = dev->base_addr;
 890
 891         /* Receive the statistical information */
 892         fp->fecpriv_stat.rx_packets = FECSTAT_RMON_R_PACKETS(base_addr);
 893         fp->fecpriv_stat.tx_packets = FECSTAT_RMON_T_PACKETS(base_addr);
 894         fp->fecpriv_stat.rx_bytes = FECSTAT_RMON_R_OCTETS(base_addr);
 895         fp->fecpriv_stat.tx_bytes = FECSTAT_RMON_T_OCTETS(base_addr);
 896
 897         fp->fecpriv_stat.multicast = FECSTAT_RMON_R_MC_PKT(base_addr);
 898         fp->fecpriv_stat.collisions = FECSTAT_RMON_T_COL(base_addr);
 899
 900         fp->fecpriv_stat.rx_length_errors =
 901                 FECSTAT_RMON_R_UNDERSIZE(base_addr) +
 902                 FECSTAT_RMON_R_OVERSIZE(base_addr) +
 903                 FECSTAT_RMON_R_FRAG(base_addr) +
 904                 FECSTAT_RMON_R_JAB(base_addr);
 905         fp->fecpriv_stat.rx_crc_errors = FECSTAT_IEEE_R_CRC(base_addr);
 906         fp->fecpriv_stat.rx_frame_errors = FECSTAT_IEEE_R_ALIGN(base_addr);
 907         fp->fecpriv_stat.rx_over_errors = FECSTAT_IEEE_R_MACERR(base_addr);
 908
 909         fp->fecpriv_stat.tx_carrier_errors = FECSTAT_IEEE_T_CSERR(base_addr);
 910         fp->fecpriv_stat.tx_fifo_errors = FECSTAT_IEEE_T_MACERR(base_addr);
 911         fp->fecpriv_stat.tx_window_errors = FECSTAT_IEEE_T_LCOL(base_addr);
 912
 913         /* I hope that one frame doesn't have more than one error */
 914         fp->fecpriv_stat.rx_errors = fp->fecpriv_stat.rx_length_errors +
 915                 fp->fecpriv_stat.rx_crc_errors +
 916                 fp->fecpriv_stat.rx_frame_errors +
 917                 fp->fecpriv_stat.rx_over_errors +
 918                 fp->fecpriv_stat.rx_dropped;
 919         fp->fecpriv_stat.tx_errors = fp->fecpriv_stat.tx_carrier_errors +
 920                 fp->fecpriv_stat.tx_fifo_errors +
 921                 fp->fecpriv_stat.tx_window_errors +
 922                 fp->fecpriv_stat.tx_aborted_errors +
 923                 fp->fecpriv_stat.tx_heartbeat_errors +
 924                 fp->fecpriv_stat.tx_dropped;
 925
 926         return &fp->fecpriv_stat;
 927 }
 928
 929 /************************************************************************
 930 * NAME: fec_set_multicast_list
 931 *
 932 * DESCRIPTION: This function sets the frame filtering parameters
 933 *************************************************************************/
 934 void fec_set_multicast_list(struct net_device *dev)
 935 {
 936         struct dev_mc_list *dmi;
 937         unsigned int crc, data;
 938         int i, j, k;
 939         unsigned long base_addr = (unsigned long) dev->base_addr;
 940
 941         if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI) {
 942                 /* Allow all incoming frames */
 943                 FEC_GALR(base_addr) = 0xFFFFFFFF;
 944                 FEC_GAUR(base_addr) = 0xFFFFFFFF;
 945                 return;
 946         }
 947
 948         /* Reset the group address register */
 949         FEC_GALR(base_addr) = 0x00000000;
 950         FEC_GAUR(base_addr) = 0x00000000;
 951
 952         /* Process all addresses */
 953         for (i = 0, dmi = dev->mc_list; i < dev->mc_count;
 954                         i++, dmi = dmi->next) {
 955                 /* Processing must be only for the group addresses */
 956                 if (!(dmi->dmi_addr[0] & 1))
 957                         continue;
 958
 959                 /* Calculate crc value for the current address */
 960                 crc = 0xFFFFFFFF;
 961                 for (j = 0; j < dmi->dmi_addrlen; j++) {
 962                         for (k = 0, data = dmi->dmi_addr[j];
 963                                         k < 8;  k++, data >>= 1) {
 964                                 if ((crc ^ data) & 1)
 965                                         crc = (crc >> 1) ^ FEC_CRCPOL;
 966                                 else
 967                                         crc >>= 1;
 968                         }
 969                 }
 970
 971                 /* Add this value */
 972                 crc >>= 26;
 973                 crc &= 0x3F;
 974                 if (crc > 31)
 975                         FEC_GAUR(base_addr) |= 0x1 << (crc - 32);
 976                 else
 977                         FEC_GALR(base_addr) |= 0x1 << crc;
 978         }
 979 }
 980
 981 /************************************************************************
 982 * NAME: fec_set_mac_address
 983 *
 984 * DESCRIPTION: This function sets the MAC address
 985 *************************************************************************/
 986 int fec_set_mac_address(struct net_device *dev, void *p)
 987 {
 988         struct fec_priv *fp = netdev_priv(dev);
 989         unsigned long base_addr = (unsigned long) dev->base_addr;
 990         struct sockaddr *addr = p;
 991
 992         if (netif_running(dev))
 993                 return -EBUSY;
 994
 995         /* Copy a new address to the device structure */
 996         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 997
 998         /* Copy a new address to the private structure */
 999         memcpy(fp->fecpriv_mac_addr, addr->sa_data, 6);
1000
1001         /* Set the address to the registers */
1002         FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) |
1003                 (fp->fecpriv_mac_addr[1] << 16) |
1004                 (fp->fecpriv_mac_addr[2] << 8) |
1005                 fp->fecpriv_mac_addr[3];
1006         FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) |
1007                 (fp->fecpriv_mac_addr[5] << 16) |
1008                 0x8808;
1009
1010         return 0;
1011 }
1012
1013 /************************************************************************
1014 * NAME: fec_tx
1015 *
1016 * DESCRIPTION: This function starts transmission of the frame using DMA
1017 *
1018 * RETURNS: This function always returns zero.
1019 *************************************************************************/
1020 int fec_tx(struct sk_buff *skb, struct net_device *dev)
1021 {
1022         struct fec_priv *fp = netdev_priv(dev);
1023         void *data, *data_aligned;
1024         int offset;
1025
1026         data = kmalloc(skb->len + 15, GFP_DMA | GFP_ATOMIC);
1027
1028         if (!data) {
1029                 fp->fecpriv_stat.tx_dropped++;
1030                 dev_kfree_skb(skb);
1031                 return 0;
1032         }
1033
1034         offset = (((unsigned long)virt_to_phys(data) + 15) & 0xFFFFFFF0) -
1035                 (unsigned long)virt_to_phys(data);
1036         data_aligned = (void *)((unsigned long)data + offset);
1037         memcpy(data_aligned, skb->data, skb->len);
1038
1039         /* flush data cache before initializing
1040          * the descriptor and starting DMA */
1041
1042         spin_lock_irq(&fp->fecpriv_lock);
1043
1044         /* Initialize the descriptor */
1045         fp->fecpriv_txbuf[fp->fecpriv_next_tx] = data;
1046         fp->fecpriv_txdesc[fp->fecpriv_next_tx].dataPointer
1047                 = (unsigned int) virt_to_phys(data_aligned);
1048         fp->fecpriv_txdesc[fp->fecpriv_next_tx].length = skb->len;
1049         fp->fecpriv_txdesc[fp->fecpriv_next_tx].statCtrl
1050                 |= (MCD_FEC_END_FRAME | MCD_FEC_BUF_READY);
1051         fp->fecpriv_next_tx = (fp->fecpriv_next_tx + 1) & FEC_TX_INDEX_MASK;
1052
1053         if (fp->fecpriv_txbuf[fp->fecpriv_current_tx]
1054                 && fp->fecpriv_current_tx == fp->fecpriv_next_tx)
1055                 netif_stop_queue(dev);
1056
1057         spin_unlock_irq(&fp->fecpriv_lock);
1058
1059         /* Tell the DMA to continue the transmission */
1060         MCD_continDma(fp->fecpriv_fec_tx_channel);
1061
1062         dev_kfree_skb(skb);
1063
1064         dev->trans_start = jiffies;
1065
1066         return 0;
1067 }
1068
1069 /************************************************************************
1070 * NAME: fec_tx_timeout
1071 *
1072 * DESCRIPTION: If the interrupt processing of received frames was lost
1073 *              and DMA stopped the reception, this function clears
1074 *              the transmission descriptors and starts DMA
1075 *
1076 *************************************************************************/
1077 void fec_tx_timeout(struct net_device *dev)
1078 {
1079         int i;
1080         struct fec_priv *fp = netdev_priv(dev);
1081         unsigned long base_addr = (unsigned long) dev->base_addr;
1082
1083         spin_lock_irq(&fp->fecpriv_lock);
1084         MCD_killDma(fp->fecpriv_fec_tx_channel);
1085         for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
1086                 if (fp->fecpriv_txbuf[i]) {
1087                         kfree(fp->fecpriv_txbuf[i]);
1088                         fp->fecpriv_txbuf[i] = NULL;
1089                 }
1090                 fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
1091         }
1092         fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
1093
1094         fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
1095
1096     /* Reset FIFOs */
1097     FEC_FECFRST(base_addr) |= FEC_SW_RST;
1098     FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
1099
1100         /* Reset and disable FEC */
1101         /* FEC_ECR(base_addr) = FEC_ECR_RESET; */
1102
1103         /* Enable FEC */
1104         FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
1105
1106         MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
1107                      (unsigned char *) &(FEC_FECTFDR(base_addr)), 0,
1108                      FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx,
1109                      FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
1110                      MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
1111
1112         spin_unlock_irq(&fp->fecpriv_lock);
1113
1114         netif_wake_queue(dev);
1115
1116 }
1117
1118 /************************************************************************
1119 * NAME: fec_interrupt_tx_handler
1120 *
1121 * DESCRIPTION: This function is called when the data
1122 *              transmission from the buffer to the FEC is completed.
1123 *
1124 *************************************************************************/
1125 void fec_interrupt_fec_tx_handler(struct net_device *dev)
1126 {
1127         struct fec_priv *fp = netdev_priv(dev);
1128
1129         /* Release the socket buffer */
1130         if (fp->fecpriv_txbuf[fp->fecpriv_current_tx]) {
1131                 kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]);
1132                 fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL;
1133         }
1134         fp->fecpriv_current_tx =
1135                 (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK;
1136
1137         if (MCD_dmaStatus(fp->fecpriv_fec_tx_channel) == MCD_DONE) {
1138                 for (; fp->fecpriv_current_tx != fp->fecpriv_next_tx;
1139                         fp->fecpriv_current_tx =
1140                         (fp->fecpriv_current_tx + 1)
1141                         & FEC_TX_INDEX_MASK) {
1142                         if (fp->fecpriv_txbuf[fp->fecpriv_current_tx]) {
1143                                 kfree(fp->fecpriv_txbuf[
1144                                         fp->fecpriv_current_tx]);
1145                                 fp->fecpriv_txbuf[fp->fecpriv_current_tx]
1146                                         = NULL;
1147                         }
1148                 }
1149         }
1150
1151         if (netif_queue_stopped(dev))
1152                 netif_wake_queue(dev);
1153 }
1154
1155 /************************************************************************
1156 * NAME: fec_interrupt_rx_handler
1157 *
1158 * DESCRIPTION: This function is called when the data
1159 *              reception from the FEC to the reception buffer is completed.
1160 *
1161 *************************************************************************/
1162 void fec_interrupt_fec_rx_handler(struct net_device *dev)
1163 {
1164         struct fec_priv *fp = netdev_priv(dev);
1165         struct sk_buff *skb;
1166         int i;
1167
1168         fp->fecpriv_rxflag = 1;
1169         /* Some buffers can be missed */
1170         if (!(fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl
1171                         & MCD_FEC_END_FRAME)) {
1172                 /* Find a valid index */
1173                 for (i = 0; ((i < FEC_RX_BUF_NUMBER) &&
1174                         !(fp->fecpriv_rxdesc[
1175                         fp->fecpriv_current_rx].statCtrl
1176                         & MCD_FEC_END_FRAME)); i++,
1177                         (fp->fecpriv_current_rx =
1178                         (fp->fecpriv_current_rx + 1)
1179                         & FEC_RX_INDEX_MASK))
1180                         ;
1181
1182                 if (i == FEC_RX_BUF_NUMBER) {
1183                         /* There are no data to process */
1184                         /* Tell the DMA to continue the reception */
1185                         MCD_continDma(fp->fecpriv_fec_rx_channel);
1186
1187                         fp->fecpriv_rxflag = 0;
1188
1189                         return;
1190                 }
1191         }
1192
1193         for (; fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl
1194                         & MCD_FEC_END_FRAME;
1195                 fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1)
1196                                                 & FEC_RX_INDEX_MASK) {
1197                 if ((fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length
1198                         <= FEC_MAXBUF_SIZE) &&
1199                         (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length
1200                                 > 4)) {
1201                         /* --tym-- */
1202                         skb = fp->askb_rx[fp->fecpriv_current_rx];
1203                         if (!skb)
1204                                 fp->fecpriv_stat.rx_dropped++;
1205                         else {
1206                         /*
1207                         * flush data cache before initializing
1208                         * the descriptor and starting DMA
1209                         */
1210                                 skb_put(skb,
1211                                         (fp->fecpriv_rxdesc[
1212                                          fp->fecpriv_current_rx].length - 4));
1213                                 skb->protocol = eth_type_trans(skb, dev);
1214                                 netif_rx(skb);
1215                         }
1216                         fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl &=
1217                                 ~MCD_FEC_END_FRAME;
1218                         /* allocate new skbuff */
1219                         fp->askb_rx[fp->fecpriv_current_rx] =
1220                                 alloc_skb(FEC_MAXBUF_SIZE + 16,
1221                                         /*GFP_ATOMIC |*/ GFP_DMA);
1222                         if (!fp->askb_rx[fp->fecpriv_current_rx]) {
1223                                 fp->fecpriv_rxdesc[
1224                                 fp->fecpriv_current_rx].dataPointer
1225                                         = 0;
1226                                 fp->fecpriv_rxdesc[
1227                                         fp->fecpriv_current_rx].length = 0;
1228                                 fp->fecpriv_stat.rx_dropped++;
1229                         } else {
1230                                 skb_reserve(
1231                                 fp->askb_rx[fp->fecpriv_current_rx], 16);
1232                                 fp->askb_rx[fp->fecpriv_current_rx]->dev = dev;
1233
1234                                 /*
1235                                  * flush data cache before initializing
1236                                  * the descriptor and starting DMA
1237                                  */
1238
1239                                 fp->fecpriv_rxdesc[
1240                                         fp->fecpriv_current_rx].dataPointer =
1241                                         (unsigned int) virt_to_phys(
1242                                         fp->askb_rx[
1243                                                 fp->fecpriv_current_rx]->tail);
1244                                 fp->fecpriv_rxdesc[
1245                                         fp->fecpriv_current_rx].length =
1246                                         FEC_MAXBUF_SIZE;
1247                                 fp->fecpriv_rxdesc[
1248                                         fp->fecpriv_current_rx].statCtrl |=
1249                                         MCD_FEC_BUF_READY;
1250
1251                                 /*
1252                                  * flush data cache before initializing
1253                                  * the descriptor and starting DMA
1254                                  */
1255                         }
1256                 }
1257
1258         }
1259
1260         /* Tell the DMA to continue the reception */
1261         MCD_continDma(fp->fecpriv_fec_rx_channel);
1262
1263         fp->fecpriv_rxflag = 0;
1264 }
1265
1266 /************************************************************************
1267 * NAME: fec_interrupt_handler
1268 *
1269 * DESCRIPTION: This function is called when some special errors occur
1270 *
1271 *************************************************************************/
1272 irqreturn_t fec_interrupt_handler(int irq, void *dev_id)
1273 {
1274
1275         struct net_device *dev = (struct net_device *)dev_id;
1276         struct fec_priv *fp = netdev_priv(dev);
1277         unsigned long base_addr = (unsigned long) dev->base_addr;
1278         unsigned long events;
1279
1280         /* Read and clear the events */
1281         events = FEC_EIR(base_addr) & FEC_EIMR(base_addr);
1282
1283         if (events & FEC_EIR_HBERR) {
1284                 fp->fecpriv_stat.tx_heartbeat_errors++;
1285                 FEC_EIR(base_addr) = FEC_EIR_HBERR;
1286         }
1287
1288         /* receive/transmit FIFO error */
1289         if (((events & FEC_EIR_RFERR) != 0)
1290                 || ((events & FEC_EIR_XFERR) != 0)) {
1291                 /* kill DMA receive channel */
1292                 MCD_killDma(fp->fecpriv_fec_rx_channel);
1293
1294                 /* kill running transmission by DMA */
1295                 MCD_killDma(fp->fecpriv_fec_tx_channel);
1296
1297                 /* Reset FIFOs */
1298                 FEC_FECFRST(base_addr) |= FEC_SW_RST;
1299                 FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
1300
1301                 /* reset receive FIFO status register */
1302                 FEC_FECRFSR(base_addr) = FEC_FECRFSR_FAE |
1303                                          FEC_FECRFSR_RXW |
1304                                          FEC_FECRFSR_UF;
1305
1306                 /* reset transmit FIFO status register */
1307                 FEC_FECTFSR(base_addr) = FEC_FECTFSR_FAE |
1308                                          FEC_FECTFSR_TXW |
1309                                          FEC_FECTFSR_UF |
1310                                          FEC_FECTFSR_OF;
1311
1312                 /* reset RFERR and XFERR event */
1313                 FEC_EIR(base_addr) = FEC_EIR_RFERR | FEC_EIR_XFERR;
1314
1315                 /* stop queue */
1316                 netif_stop_queue(dev);
1317
1318                 /* execute reinitialization as tasklet */
1319                 tasklet_schedule(&fp->fecpriv_tasklet_reinit);
1320
1321                 fp->fecpriv_stat.rx_dropped++;
1322         }
1323
1324         /* transmit FIFO underrun */
1325         if ((events & FEC_EIR_XFUN) != 0) {
1326                 /* reset XFUN event */
1327                 FEC_EIR(base_addr) = FEC_EIR_XFUN;
1328                 fp->fecpriv_stat.tx_aborted_errors++;
1329         }
1330
1331         /* late collision */
1332         if ((events & FEC_EIR_LC) != 0) {
1333                 /* reset LC event */
1334                 FEC_EIR(base_addr) = FEC_EIR_LC;
1335                 fp->fecpriv_stat.tx_aborted_errors++;
1336         }
1337
1338         /* collision retry limit */
1339         if ((events & FEC_EIR_RL) != 0) {
1340                 /* reset RL event */
1341                 FEC_EIR(base_addr) = FEC_EIR_RL;
1342                 fp->fecpriv_stat.tx_aborted_errors++;
1343         }
1344         return 0;
1345 }
1346
1347 /************************************************************************
1348 * NAME: fec_interrupt_reinit
1349 *
1350 * DESCRIPTION: This function is called from interrupt handler
1351 *              when controller must be reinitialized.
1352 *
1353 *************************************************************************/
1354 void fec_interrupt_fec_reinit(unsigned long data)
1355 {
1356         int i;
1357         struct net_device *dev = (struct net_device *)data;
1358         struct fec_priv *fp = netdev_priv(dev);
1359         unsigned long base_addr = (unsigned long) dev->base_addr;
1360
1361         /* Initialize reception descriptors and start DMA for the reception */
1362         for (i = 0; i < FEC_RX_BUF_NUMBER; i++) {
1363                 if (!fp->askb_rx[i]) {
1364                         fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16,
1365                                         GFP_ATOMIC | GFP_DMA);
1366                         if (!fp->askb_rx[i]) {
1367                                 fp->fecpriv_rxdesc[i].dataPointer = 0;
1368                                 fp->fecpriv_rxdesc[i].statCtrl = 0;
1369                                 fp->fecpriv_rxdesc[i].length = 0;
1370                                 continue;
1371                         }
1372                         fp->askb_rx[i]->dev = dev;
1373                         skb_reserve(fp->askb_rx[i], 16);
1374                 }
1375                 fp->fecpriv_rxdesc[i].dataPointer =
1376                         (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
1377                 fp->fecpriv_rxdesc[i].statCtrl =
1378                         MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
1379                 fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
1380         }
1381
1382         fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
1383         fp->fecpriv_current_rx = 0;
1384
1385         /* restart frame transmission */
1386         for (i = 0; i < FEC_TX_BUF_NUMBER; i++) {
1387                 if (fp->fecpriv_txbuf[i]) {
1388                         kfree(fp->fecpriv_txbuf[i]);
1389                         fp->fecpriv_txbuf[i] = NULL;
1390                         fp->fecpriv_stat.tx_dropped++;
1391                 }
1392                 fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
1393         }
1394         fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
1395         fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
1396
1397         /* flush entire data cache before restarting the DMA */
1398
1399         /* restart DMA from beginning */
1400         MCD_startDma(fp->fecpriv_fec_rx_channel,
1401                      (char *) fp->fecpriv_rxdesc, 0,
1402                      (unsigned char *) &(FEC_FECRFDR(base_addr)), 0,
1403                      FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_rx,
1404                      FEC_RX_DMA_PRI, MCD_FECRX_DMA | MCD_INTERRUPT,
1405                      MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
1406
1407         MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
1408                      (unsigned char *) &(FEC_FECTFDR(base_addr)), 0,
1409                      FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx,
1410                      FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
1411                      MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
1412
1413         /* Enable FEC */
1414         FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
1415
1416         netif_wake_queue(dev);
1417 }
1418
1419 /************************************************************************
1420 * NAME: fec_interrupt_tx_handler_fec0
1421 *
1422 * DESCRIPTION: This is the DMA interrupt handler using  for FEC0
1423 *              transmission.
1424 *
1425 *************************************************************************/
1426 void fec_interrupt_fec_tx_handler_fec0(void)
1427 {
1428         fec_interrupt_fec_tx_handler(fec_dev[0]);
1429 }
1430
1431 #ifdef FEC_2
1432 /************************************************************************
1433 * NAME: fec_interrupt_tx_handler_fec1
1434 *
1435 * DESCRIPTION: This is the DMA interrupt handler using for the FEC1
1436 *              transmission.
1437 *
1438 *************************************************************************/
1439 void fec_interrupt_fec_tx_handler_fec1(void)
1440 {
1441         fec_interrupt_fec_tx_handler(fec_dev[1]);
1442 }
1443 #endif
1444
1445 /************************************************************************
1446 * NAME: fec_interrupt_rx_handler_fec0
1447 *
1448 * DESCRIPTION: This is the DMA interrupt handler using for the FEC0
1449 *              reception.
1450 *
1451 *************************************************************************/
1452 void fec_interrupt_fec_rx_handler_fec0(void)
1453 {
1454         fec_interrupt_fec_rx_handler(fec_dev[0]);
1455 }
1456
1457 #ifdef FEC_2
1458 /************************************************************************
1459 * NAME: fec_interrupt_rx_handler_fec1
1460 *
1461 * DESCRIPTION: This is the DMA interrupt handler using for the FEC1
1462 *              reception.
1463 *
1464 *************************************************************************/
1465 void fec_interrupt_fec_rx_handler_fec1(void)
1466 {
1467         fec_interrupt_fec_rx_handler(fec_dev[1]);
1468 }
1469
1470 #endif
1471
1472 #ifndef MODULE
1473 /************************************************************************
1474 * NAME: fec_mac_setup0
1475 *
1476 * DESCRIPTION: This function sets the MAC address of FEC0 from command line
1477 *
1478 *************************************************************************/
1479 int __init fec_mac_setup0(char *s)
1480 {
1481         if (!s || !*s)
1482                 return 1;
1483
1484         if (fec_str_to_mac(s, fec_mac_addr_fec0))
1485                 printk(KERN_ERR "The MAC address of FEC0 "
1486                         "cannot be set from command line");
1487         return 1;
1488 }
1489
1490 #ifdef FEC_2
1491
1492 /************************************************************************
1493 * NAME: fec_mac_setup1
1494 *
1495 * DESCRIPTION: This function sets the MAC address of FEC1 from command line
1496 *
1497 *************************************************************************/
1498 int __init fec_mac_setup1(char *s)
1499 {
1500         if (!s || !*s)
1501                 return 1;
1502
1503         if (fec_str_to_mac(s, fec_mac_addr_fec1))
1504                 printk(KERN_ERR "The MAC address of FEC1 "
1505                         "cannot be set from command line\n");
1506         return 1;
1507 }
1508 #endif
1509
1510 /************************************************************************
1511 * NAME: fec_str_to_mac
1512 *
1513 * DESCRIPTION: This function interprets the character string into MAC addr
1514 *
1515 *************************************************************************/
1516 int fec_str_to_mac(char *str_mac, unsigned char* addr)
1517 {
1518         unsigned long val;
1519         char c;
1520         unsigned long octet[6], *octetptr = octet;
1521         int i;
1522
1523 again:
1524         val = 0;
1525         while ((c = *str_mac) != '\0') {
1526                 if ((c >= '0') && (c <= '9')) {
1527                         val = (val * 16) + (c - '0');
1528                         str_mac++;
1529                         continue;
1530                 } else if (((c >= 'a') && (c <= 'f'))
1531                         || ((c >= 'A') && (c <= 'F'))) {
1532                         val = (val << 4) +
1533                                 (c + 10 -
1534                                 (((c >= 'a') && (c <= 'f')) ? 'a' : 'A'));
1535                         str_mac++;
1536                         continue;
1537                 }
1538                 break;
1539         }
1540         if (*str_mac == ':') {
1541                 *octetptr++ = val, str_mac++;
1542                 if (octetptr >= octet + 6)
1543                         return 1;
1544                 goto again;
1545         }
1546
1547         /* Check for trailing characters */
1548         if (*str_mac && !(*str_mac == ' '))
1549                 return 1;
1550
1551         *octetptr++ = val;
1552
1553         if ((octetptr - octet) == 6) {
1554                 for (i = 0; i <= 6; i++)
1555                         addr[i] = octet[i];
1556         } else
1557                 return 1;
1558
1559         return 0;
1560 }
1561 #endif