1 --- a/drivers/net/ethernet/lantiq_etop.c
2 +++ b/drivers/net/ethernet/lantiq_etop.c
5 #include <lantiq_platform.h>
7 -#define LTQ_ETOP_MDIO 0x11804
8 +#define LTQ_ETOP_MDIO_ACC 0x11804
9 #define MDIO_REQUEST 0x80000000
10 #define MDIO_READ 0x40000000
11 #define MDIO_ADDR_MASK 0x1f
13 #define MDIO_REG_OFFSET 0x10
14 #define MDIO_VAL_MASK 0xffff
16 -#define PPE32_CGEN 0x800
17 -#define LQ_PPE32_ENET_MAC_CFG 0x1840
18 +#define LTQ_ETOP_MDIO_CFG 0x11800
19 +#define MDIO_CFG_MASK 0x6
21 +#define LTQ_ETOP_CFG 0x11808
22 +#define LTQ_ETOP_IGPLEN 0x11820
23 +#define LTQ_ETOP_MAC_CFG 0x11840
25 #define LTQ_ETOP_ENETS0 0x11850
26 #define LTQ_ETOP_MAC_DA0 0x1186C
27 #define LTQ_ETOP_MAC_DA1 0x11870
28 -#define LTQ_ETOP_CFG 0x16020
29 -#define LTQ_ETOP_IGPLEN 0x16080
31 +#define MAC_CFG_MASK 0xfff
32 +#define MAC_CFG_CGEN (1 << 11)
33 +#define MAC_CFG_DUPLEX (1 << 2)
34 +#define MAC_CFG_SPEED (1 << 1)
35 +#define MAC_CFG_LINK (1 << 0)
37 #define MAX_DMA_CHAN 0x8
38 #define MAX_DMA_CRC_LEN 0x4
39 #define MAX_DMA_DATA_LEN 0x600
41 #define ETOP_FTCU BIT(28)
42 -#define ETOP_MII_MASK 0xf
43 -#define ETOP_MII_NORMAL 0xd
44 -#define ETOP_MII_REVERSE 0xe
45 #define ETOP_PLEN_UNDER 0x40
46 -#define ETOP_CGEN 0x800
47 #define ETOP_CFG_MII0 0x01
49 +#define ETOP_CFG_MASK 0xfff
50 +#define ETOP_CFG_FEN0 (1 << 8)
51 +#define ETOP_CFG_SEN0 (1 << 6)
52 +#define ETOP_CFG_OFF1 (1 << 3)
53 +#define ETOP_CFG_REMII0 (1 << 1)
54 +#define ETOP_CFG_OFF0 (1 << 0)
56 #define LTQ_GBIT_MDIO_CTL 0xCC
57 #define LTQ_GBIT_MDIO_DATA 0xd0
58 #define LTQ_GBIT_GCTL0 0x68
59 @@ -355,16 +366,19 @@ ltq_etop_hw_init(struct net_device *dev)
60 /* force the etops link to the gbit to MII */
61 mii_mode = PHY_INTERFACE_MODE_MII;
63 + ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
64 + ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
65 + MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
68 case PHY_INTERFACE_MODE_RMII:
69 - ltq_etop_w32_mask(ETOP_MII_MASK,
70 - ETOP_MII_REVERSE, LTQ_ETOP_CFG);
71 + ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
72 + ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
75 case PHY_INTERFACE_MODE_MII:
76 - ltq_etop_w32_mask(ETOP_MII_MASK,
77 - ETOP_MII_NORMAL, LTQ_ETOP_CFG);
78 + ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
79 + ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
83 @@ -385,9 +399,6 @@ ltq_etop_hw_init(struct net_device *dev)
87 - /* enable crc generation */
88 - ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
93 @@ -521,9 +532,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
94 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
97 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
98 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
100 - ltq_etop_w32(val, LTQ_ETOP_MDIO);
101 + ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
105 @@ -534,12 +545,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
106 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
107 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
109 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
110 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
112 - ltq_etop_w32(val, LTQ_ETOP_MDIO);
113 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
114 + ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
115 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
117 - val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
118 + val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;